NOVEL APPROACHES TO FERROELECTRIC AND GALLIUM NITRIDE VARACTORS. Dissertation. Submitted to. The School of Engineering of the UNIVERSITY OF DAYTON

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1 NOVEL APPROACHES TO FERROELECTRIC AND GALLIUM NITRIDE VARACTORS Dissertation Submitted to The School of Engineering of the UNIVERSITY OF DAYTON In Partial Fulfillment of the Requirements for The Degree of Doctor of Philosophy in Electrical Engineering by Dustin Anthony Brown Dayton, Ohio May, 2014

2 NOVEL APPROACHES TO FERROELECTRIC AND GALLIUM NITRIDE VARACTORS Name: Brown, Dustin Anthony APPROVED BY: Guru Subramanyam, Ph.D. Advisory Committee Chairman Professor & Chair Department of Electrical and Computer Engineering Monish Chatterjee, Ph.D. Committee Member Professor Department of Electrical and Computer Engineering Robert Penno, Ph.D. Committee Member Associate Professor Department of Electrical and Computer Engineering Charles Cerny, Ph.D. Committee Member Air Force Research Laboratory John G. Weber, Ph.D. Associate Dean School of Engineering Tony E. Saliba, Ph.D. Dean, School of Engineering & Wilke Distinguished Professor ii

3 Copyright by Dustin Anthony Brown All rights reserved 2014 iii

4 ABSTRACT NOVEL APPROACHES TO FERROELECTRIC AND GALLIUM NITRIDE VARACTORS Name: Brown, Dustin Anthony University of Dayton Advisor: Dr. Guru Subramanyam This dissertation addresses the implementation of high-electron-mobility transistor (HEMT) based gallium nitride (GaN) varactors and compares them to barium strontium titanate (BST) parallel plate varactors in terms of tunability, quality factor, power handling capability, and size. New designs of multilayered BST varactor devices that utilize three-dimensional packaging of high dielectric ferroelectric materials are described. These structures are designed to improve device quality, while also generating new geometries that explore device physics that have not been previously explored with barium strontium titanate. A GaN foundry process was used to fabricate two varactor topologies, and devices have measured tunability exceeding 40%. Capacitance voltage relationships of the varactors are compared to intrinsic capacitances of transistors of the same gate periphery and bias voltages. Correlations between measurements are described with findings that will support design success of future GaN based varactors. A 1-Port BST varactor device was also generated, and the resulting capacitance has more than 60% tunability in a mm 2 total device size. The resulting device iv

5 geometry is similar to those of previous designs and allows for a direct comparison to the measured performance of 1-Port GaN varactor devices. Nonlinear device models are generated for each varactor technology and used in the design of a radio frequency filter implemented on a printed circuit board. The same filter is used with both GaN and BST varactors so tests of the RF signal power handling capability as well as bias power consumption are compared. v

6 DEDICATION Dedicated to Him who gives me strength vi

7 ACKNOWLEDGMENTS I first must give thanks to my parents. They have been and continue to be my mentors, advisors, and teachers. They taught me the importance of faith, hard work and determination all of which were needed to fulfill this research. I also thank my advisor, Dr. Guru Subramanyam, whose encouragement, optimism, and generosity allowed me to succeed. He has taught me technical material I was initially scared to pursue and more importantly non-technical skills that I will continue to foster throughout my career. I also thank all of the members of my committee for their support and advice throughout this degree. I am grateful to the past and present members of the microwave electronics research team at the University of Dayton. I have enjoyed learning from and alongside all of you. I thank my research peers at the Air Force Research Laboratory for providing me with advice, encouragement, and resources to complete my research. Finally, I could not have done this work without the love and support of my son, Anthony, and my wife, Jen. I am especially grateful to my wife during the period of this research. Without her encouragement I would not have started this educational journey. Without her confidence I would not have endured this educational journey. Without her sacrifice I would not have ended this educational journey. vii

8 TABLE OF CONTENTS ABSTRACT... IV DEDICATION... VI ACKNOWLEDGMENTS... VII LIST OF FIGURES... X LIST OF TABLES... XIII CHAPTER 1 - INTRODUCTION MOTIVATION PROBLEM STATEMENT OBJECTIVES SCIENTIFIC PUBLICATIONS CONTRIBUTIONS TO THE STATE OF THE ART ORGANIZATION OF THE DISSERTATION... 7 CHAPTER 2 LITERATURE REVIEW BARIUM STRONTIUM TITANATE GALLIUM NITRIDE APPLICATIONS OF VARACTORS CHAPTER 3 VARACTOR DESIGNS THREE DIMENSIONAL VARACTOR viii

9 3.2 1-PORT BST VARACTOR GALLIUM NITRIDE VARACTOR CHAPTER 4 INDIVIDUAL DEVICE PERFORMANCE TEST ENVIRONMENT TESTING METHODOLOGY RATIONALE FOR THE VARACTOR SMALL SIGNAL MODEL DEVICE MEASUREMENTS NON-LINEAR VARACTOR MODELING CHAPTER 5 VARACTOR DEVICE IMPLEMENTED IN A FILTER CIRCUIT FILTER DESIGN NON-LINEAR VARACTOR MODELING NON-LINEAR VARACTOR MODELING CHAPTER 6 CONCLUSIONS RESULTS OF VARACTOR COMPARISON FUTURE OPPORTUNITIES SUMMARY BIBLIOGRAPHY APPENDIX A: VERILOG CODE APPENDIX B: TECHNOLOGIES UTILIZING BST THIN FILM VARACTORS ix

10 LIST OF FIGURES Figure 2-1 Curie temperature vs. Barium Content, x Figure 2-2 Dielectric Constant vs. Barium Content, x Figure 2-3 BST Polarization vs. Electric Field For different Barium Content, x Figure 3-1 Cross-section of 3D Varactor Showing Biases Figure 3-2 Top View of 3D Varactor Figure 3-3 Pulsed Laser Deposition System Figure 3-4 Cross-section of 3D Varactor Showing Derived Capacitances Figure 3-5 Evolution of etched silicon electroplating Figure 3-6 Top View of 2-Port Shunt BST Varactor Figure 3-7 Top View of 1-Port BST Varactor Figure 3-8 Cross Section of GaN Transistor Figure 3-9 GaN Device Cross Section with Representative Lumped Elements.. 38 Figure 3-10 Complete Small Signal Transistor Model of GaN HEMT Device Figure 3-11 Top View of GaN HEMT Device Figure 3-12 Top View of GaN HEMT Device Configured as a Varactor Figure 3-13 Top View of 2-Port Series GaN Varactor Figure 3-14 Top View of 1-Port GaN Varactor Figure 3-15 Top View of 6x100 GaN HEMT Transistor Figure 3-16 Top View of 4x100 GaN HEMT Transistor Figure 4-1 RF Test Bench Setup x

11 Figure 4-2 Testing Block Diagram for 1-Port Varactors Figure 4-3 Testing Block Diagram for 2-Port GaN Devices Figure 4-4 Varactor Lumped Element Model Figure 4-5 Simplified Small Signal Model for HEMT Devices Figure 4-6 CV Curve of the Three 6x100 GaN Devices Analyzed Figure 4-7 CV Curve of the Two Measured HEMT Topologies Figure 4-8 Extracted Individual Element CV Curves of two HEMT Sizes Figure 4-9 Bias Currents for Two HEMT Topologies, Vds = 0V Figure 4-10 Measured BST Varactor CV Curve Figure 4-11 Measured Quality Factor of BST Varactor Figure 4-12 Frequency Dependency of BST Varactor Quality Factor Figure 4-13 Measured GaN Varactor CV Curve Figure 4-14 Measured Quality Factor of GaN Varactor Figure 4-15 Frequency Dependency of BST Varactor Quality Factor Figure 4-16 Capacitance Versus Temperature of BST Varactor Figure 4-17 Series Resistance Versus Temperature of BST Varactor Figure 4-18 Capacitance Versus Temperature of GaN Varactor Figure 4-19 Series Resistance Versus Temperature of GaN Varactor Figure 4-20 DC IV Curve of BST and GaN Varactors Figure 4-21 Capacitance and IV of BST Varactor Figure 4-22 Capacitance and IV of GaN Varactor Figure 4-23 Modeled BST Series Resistance, R s Figure 4-24 Modeled BST Capacitance Figure 4-25 Modeled GaN Series Resistance, R s Figure 4-26 Modeled GaN Capacitance Figure 4-27 GaN Varactor Verilog A Model in Genesys xi

12 Figure 4-28 Measured 1-Port GaN Varactor S Figure 4-29 Verilog Model Simulation 1-Port GaN Varactor S Figure 5-1 Schematic Diagram of Designed Circuit Board Filter Figure 5-2 Realized Circuit Board Filter Figure 5-3 Surface Mount High-Pass Portion of Realized Circuit Board Filter Figure 5-4 Genesys Model of Circuit Board Filter with Verilog A Varactors Figure 5-5 Simulated Circuit Board Filter Using BST Varactor Verilog-A Model. 80 Figure 5-6 Simulated Circuit Board Filter Using GaN Varactor Verilog-A Model 81 Figure 5-7 Measured Circuit Board Filter Using 1-Port BST Varactor Figure 5-8 Measured Circuit Board Filter Using 1-Port GaN Varactor Figure 5-9 Filter Response to Power, 1-Port BST Varactor 0V Bias Figure 5-10 Filter Response to Power, 1-Port BST Varactor 1V Bias Figure 5-11 Filter Response to Power, 1-Port GaN Varactor -3V Bias Figure 5-12 Filter Response to Power, 1-Port GaN Varactor -2.5V Bias Figure 5-13 Measured Current at Bias Line for both 1-Port Varactors xii

13 LIST OF TABLES Table 3-1 3D Varactor Diagrams of Manufacturing Steps Table 3-2 BST Capacitance of FEM Simulations and Fabricated Devices Table Port GaN Varactor Measured and Verilog Model S Table 5-1 Filter Board Parts List Table 5-2 GaN Filter Summary Table 5-3 BST Filter Summary Table B-1 Filters Table B-2 Resonators and Antennas Table B-3 Phase Shifters Table B-4 Hybrid & Active Circuits xiii

14 CHAPTER 1 - INTRODUCTION 1.1 Motivation Engineers are continuously developing physically smaller electrical circuits while also combining multiple operations and functions together. This evolution of technology has led to the creation of system on chip (SoC) and system in package (SIP) concepts. These complex platforms have increasingly more challenging requirements in terms of circuit component tolerances, frequency of operation, power usage, as well as other electrical metrics. Designers are frequently forced to make tradeoffs between these requirements that are often times conflicting with one another. Because of this, any method of providing flexibility to an integrated electrical system without adding substantial size, weight, power, or cost are welcome to circuit designers. Not only the inherent demands of the circuit design itself, but variations in the processing and manufacturing of components, devices, and wafers lead to a need of flexible circuit components. Various circuits and technologies [1], [2], have been created and tested to correct errors in matching networks, frequency of operation, and efficiency to name a few. Use of components that can be tuned or adjusted can lead to in-situ means of calibration and correction. An area of electronics in high demand is the mobile and wireless industry. A recent United Nations study found that six billion of the seven billion people of the world have mobile phones [3]. This widespread use and consumer demand drives a need for capable radio and microwave electronic circuits and systems. The proliferation of 1

15 wireless Internet in addition to cellular technologies demands that systems operate under numerous and changing frequencies of operation and communication standards to meet the ever growing demand for sending and receiving electronic data and media. As the passive electrical components of resistors, capacitors, and inductors are the most basic and fundamental circuit elements used in electronic design, there is strong interest in ways of being able to tune and control these element values to provide the needed system flexibility. Various forms of tunable resistors (varistors), and capacitors (varactors) have been studied over the previous decades. As technology and packaging have changed, however, innovative approaches and techniques of creating these components is an area of research that is always in demand. The underlying material technology utilized to create radio and microwave electronics is also changing. Current technologies include silicon (Si), Silicon Germanium Bipolar Complementary Oxide Semiconductor (SiGe BiCMOS), silicon-onsapphire (SOS), and Gallium Arsenide (GaAs) among others[4]. Regardless of the technology the tunable passives market is growing. It has been forecasted by RBC Capital Markets that the tunable capacitor market is expected to reach $500 Million by This dissertation aligns with this strong market need for innovative devices in a growing industry by analyzing various types of new tunable capacitor circuits with the intended application as a flexible component for integrated circuits and systems used in wireless and radio frequency (RF) platforms. 1.2 Problem Statement The primary objective for this dissertation is to evaluate the tradeoffs of two competing technologies of varactor devices that will be useful to modern radio electronics markets in terms of frequency of operation, physical size, and power 2

16 demands. The first technology selection will be barium strontium titanate (BST). While barium strontium titanate thin film varactors have been researched for several years, devices have only recently been available in the consumer market place. The material is noted for its very high capacitance per area density leading to compact device size compared to previous capacitor technologies. GaN technology is the second technology selected due to the power handling capabilities of this wide bandgap material that allow it to be well suited in radio frequency power amplifiers and transmitter circuitry. While most circuits still utilize silicon processes, there are numerous foundries that have GaN capabilities [5]. This dissertation leverages advances to this still growing technology by focusing on innovative circuit topologies using existing components built by a foundry with no post-processing and still achieve tunable capacitance behaviors with acceptable component quality. This technique thus avoids ambiguous claims of alternative processing techniques performed by researchers that claim devices being foundry compatible. To best compare the two technologies, the metric(s) of comparison must first be determined. The first metric to compare between the two technologies will be tunability, determined according to the following equation: (Eq. 1) Second the voltage range needed to achieve the maximum to minimum tuning will also be evaluated. Third the Quality factor (Q-Factor) at 1 and 10 GHz will be calculated as follows. (Eq. 2) A final set of metrics will be determined based on the performance of a varactor device when implemented within a larger system level implementation. Circuit 3

17 performance in both technologies will be evaluated by comparing expected and actual behavior, power handling capabilities, and DC power consumption. A second outcome is to generate non-linear circuit simulation models for each process. These models will include one or more parameters that can be adjusted to achieve a desired performance metric. This modeling will utilize the same parameters used in the determination of tunability and quality factor, and will prove valuable to the objectives tied to performance of a technology in a more complex circuit system. 1.3 Objectives The primary objective for this dissertation is as follows: 1. Design a barium strontium titanate (BST) thin film varactor with two separate biasing capabilities using advanced layering techniques. 2. Develop thick electroplating processes for implementation on silicon wafers designed to enhance the overall quality factor (Q factor) of RF/microwave devices and circuits 3. Characterize the capacitance voltage curves of GaN-based varactors 4. Compare and contrast the varactor performance between BST-based and GaNbased varactors in terms of Q factor, tunability, and power handling capabilities 5. Generate circuit simulator compatible models for BST and GaN based varactor components 1.4 Scientific Publications Numerous refereed journal and conference articles were published that were directly impacted by the material research and/or process research presented in the following dissertation. The following is a list of these publications: 4

18 Subramanyam, G.; Shin, E.; Brown, D.; Yue, H., "Thermally controlled vanadium dioxide thin film microwave devices," Circuits and Systems (MWSCAS), 2013 IEEE 56th International Midwest Symposium on, vol., no., pp.73,76, 4-7 Aug Hailing Y.; Brown, D.; Subramanyam, G.; Leedy, K.; Cerny, C., "Thin film Barium- Strontium-Titanate Parallel-Plate varactors integrated on low-resistivity silicon and saphhire substrate," Applications of Ferroelectric and Workshop on the Piezoresponse Force Microscopy (ISAF/PFM), 2013 IEEE International Symposium on the, vol., no., pp.291,294, July 2013 Jiang, H.; Patterson, M.; Brown, D.; Zhang, C.; Pan, K.C.; Subramanyam, G.; Kuhl, D.; Leedy, K.; Cerny, C., "Miniaturized and Reconfigurable CPW Square-Ring Slot Antenna Loaded With Ferroelectric BST Thin Film Varactors," Antennas and Propagation, IEEE Transactions on, vol.60, no.7, pp.3111,3119, July 2012 Pan, K.C.; Brown, D. ; Subramanyam, G.; et al., A Reconfigurable Coplanar Waveguide Bowtie Antenna Using an Integrated Ferroelectric Thin-Film Varactor, International Journal of Antennas and Propagation, vol. 2012, Article ID , 6 pages, 2012 Brown, D.; Qumsiyeh, M.; Subramanyam, G.; Patterson, M.; Zhang, C., "Ferroelectric thin-film characterization through use of coplanar waveguide varactors," Aerospace and Electronics Conference (NAECON), 2012 IEEE National, vol., no., pp.149,153, July 2012 Brown, D.; Zhang, C.; Patterson, M.; Subramanyam, G.; Leedy, K.; Cerny, C., Coplanar waveguide varactors with bottom metal trenched in silicon, Aerospace and Electronics Conference (NAECON), Proceedings of the 2011 IEEE National, Vol., no., pp , July

19 Pan, K.C.; Jiang, H.; Brown, D.; Zhang, C.; Patterson, M.; Subramanyam, G.;, Frequency tuning of CPW bowtie antenna by ferroelectric BST thin film varactors, Aerospace and Electronics Conference (NAECON), Proceedings of the 2011 IEEE National, vol, no., pp. 1-4, July 2011 Xu, Y.; Zhang, C.; Brown, D.; Subramanyam, G.; Patterson, M.; Jiang, H., Modeling and analysis of coplanar waveguide (CPW) based multilayer on-chip inductors,; Aerospace and Electronics Conference (NAECON), Proceedings of the 2011 IEEE National, vol, no., pp , July 2011 Yue, H.; Zhang, C.; Patterson, M.; Brown, D.; Subramanyam, G., Thin film Barium Strontium-Titanate varactor-tuned single spiral band-stop filter for X-band applications, Aerospace and Electronics Conference (NAECON), Proceedings of the 2011 IEEE National, vol, no., pp , July 2011 Jiang, H.; Patterson, M.; Brown, D.; Zhang, C.; Pan, K.C.; Subramanyam, G.; Kuhl, D.; Leedy, K.; Cerny, C., Miniaturized and reconfigurable CPW square-ring slot antenna using thin film varactor technology, Microwave Symposium Digest (MTT), 2011 IEEE MTT-S International, vol., no., pp.1-4,5-10 June Contributions to the State of the Art The following dissertation advances the state of the art with regards to varactors in three key areas; varactor modeling and simulations, advancements in multilayer integrated circuit processing, and finally the realization of gallium nitride varactors built by an actual foundry process. Varactor models using the Verilog-A language can be utilized by future engineers in the development of more complex electronic systems. These circuits have been used in the design of a printed circuit board (PCB) filter and were found to have good agreement to the measured filter performance. The same basic model has further been 6

20 used on two separate varactor technologies, BST thin film varactors and GaN transistor based varactors, with the only notable change due to the variations in the capacitancevoltage relationship differences between the two technologies. Techniques to improve the capacitor density without sacrificing overall quality will be necessary to meet the market trends of smaller and more demanding electronic circuits. This improvement will more than likely need to come from developments in utilization of the height parameters of the fabrication. This can be thought of as a switch in manufacturing techniques from primarily planar, or two dimensional, to a truly three dimensional design. The complexities of fabrication to accomplish this task are the first hurdles that need to be surpassed before the analysis and eventual optimization of elements can be determined. This dissertation advances silicon etching and gold electroplating knowledge that can be useful for multiple integrated circuit elements and interconnects not just varactors. Finally, while many papers have presented gallium nitride based varactors over the years [6 16], few have developed existing foundry process compatible devices. Those devices that have been generated are usually in small batches in a lab rather than attempting to go through an existing foundry path. This research explains the performance of a GaN varactor realized through a foundry. This device could thus be quickly and easily included in more complex MMIC designs. 1.6 Organization of the Dissertation The dissertation is organized in terms of increasing complexity of device structure regardless of technology; beginning with understanding of the materials used that make the device possible, followed by device understanding, and finally system level understanding. Chapter 2 is a review of the literature regarding BST and GaN. In Chapter 3, newly designed varactor geometries are defined and the criteria used in the 7

21 evaluation of the design are discussed. In Chapter 4 the discussion of the fabrication and testing of the multiple varactors is presented. These results are analyzed as well as defined by device models. In Chapter 5 these same models were implemented in a RF filter board design. The fabricated board was analyzed with both BST and GaN varactors. The results were also compared to the initial simulation design using the device models. Finally in Chapter 6 are conclusions and opportunities of future research. 8

22 CHAPTER 2 LITERATURE REVIEW 2.1 Barium Strontium Titanate Ferroelectrics Ferroelectrics are materials that exhibit a dielectric polarization when exposed to an external electric field [17]. The dielectric permittivity of a device is described as the slope of the polarization/electric field curve. For typical dielectrics this is a positive line, whereas ferroelectrics exhibit nonlinear polarization curves. These ferroelectric materials typically exhibit one of two polarization forms ferroelectric or paraelectric polarization. Ferroelectric polarization is noteworthy in its presence of hysteresis in the polarization electric field curve. This leads to a dielectric that is dependent on both electric field intensity as well as the history of the applied field. Paraelectric polarization materials do not contain hysteresis effects. It is important to note that materials with ferroelectric phase can possess paraelectric polarization above a phase transition temperature, called the Curie temperature. It is a general practice to use ferroelectrics in a paraelectric phase for electrically tunable microwave device applications [18]. This is due to the fact that many ferroelectrics in ferroelectric phase also have strong piezoelectric effects. Transformations caused by piezoelectric effects can lead to significant losses at microwave frequencies. The variable dielectric constant, r, of ferroelectric materials is especially noteworthy when used in capacitor structures. The parallel plate capacitor, made of two 9

23 metals each of area A, separated by a dielectric material of thickness d, has capacitance defined by Eq. 3 below. (Eq. 3) The capacitance equation is useful for both transmission line characteristic impedance calculations as well as the creation of dedicated capacitors. As can be seen above, the capacitance is proportional to the dielectric constant. By having a material with a variable dielectric constant, capacitors can be tuned, creating varactors. As ferroelectrics require the addition of a new material during fabrication it is important to compare ferroelectric performance to devices and processes currently in place. As silicon is the de-facto process, regions where ferroelectric performance exceeds silicon should be the area of focus if the goal is adoption of the technology. A comparison between ferroelectric and semiconductor varactors shows that above10 20GHz ferroelectric varactors have a steady quality factor whereas silicon varactors quality decreases drastically [18]. Ferroelectric capacitors typically come in two varieties, sandwich-type capacitors and planar capacitors. Both can be described as parallel plate devices where the sandwich capacitors have a top and bottom plate separated by the ferroelectric material, while the planar capacitors exist above the ferroelectric layer on the same horizontal plane [19]. As planar varactors have the ferroelectric material under the contacts and regular dielectric, usually air, above a considerable part of the capacitor electric field is outside the ferroelectric film. The measured effective dielectric constant, tunability, and loss tangent are thus different than the ferroelectric material. Planar varactors inherent capacitances are varied based on criteria such as width of the gap between the planar electrodes, length of the electrodes, and thickness of the ferroelectric film. 10

24 Sandwich-type capacitors electric fields primarily exist in the ferroelectric material. Thus, the behavior is approximately the ideal parallel plate capacitance condition. Sandwich-type capacitors are varied based on electrode area and thickness of the ferroelectric film. The detailed review of [19] discusses the benefits and tradeoffs of the various circuit topologies used in ferroelectric capacitor designs. The most important to consider with regard to the two topologies listed is the applied electric field region. In the planar configuration case, higher voltages are needed as the electric fields are only partially contained in the ferroelectric material. In the sandwich-type, almost all of the electric field is contained in the ferroelectric layer, thus allowing for a smaller voltage to achieve the same field intensity. The trade-off is thus in terms of the voltage bias; small voltages of tuning in the sandwich-type and large voltages in the planar type. The other component of the tradeoff is thus power handling. As power correlated to voltage, the planar case can support more power than the sandwich type. Thus architecture of the varactor should be determined by application. BST Barium Strontium Titanate (BST) is a solid solution of BaTiO 3 and SrTiO 3, which is commonly written as Ba x Sr 1-x TiO 3. The subscript indicates the fractional composition of the two components. The selection of materials is chosen because BaTiO 3 is a ferroelectric material with a Curie temperature of 120 o C, while SrTiO 3 is a paraelectric material with no ferroelectric phase transition. When combining the two materials into a solid, BST is in a ferroelectric phase at room temperature when x is greater than 0.70, and in a paraelectric phase at room temperature when x is less than 0.70 [20]. The BST solid has a cubic structure for x less than 0.70 and tetragonal for x greater than 0.30 [21]. This change in the solid form is 11

25 Figure 2-1 Curie temperature vs. Barium Content, x [21] associated with the paraelectric and ferroelectric phase transition. The Curie temperature increases with increasing Ba content, as shown in Figure 2-1. Barium-strontium-titanate films can be generated by several deposition processes including sputtering, pulsed laser deposition (PLD), metalorganic chemical vapor deposition (MOCVD), and sol gel [22]. BST is also noteworthy for its high relative dielectric constant. This can be seen in Figure 2-2 which plots the dielectric constant of various Ba compositions from a, RF Magnetron sputtering of 400 to 500 nm thick BST on a mirror-polished single crystal R- plane sapphire substrate [23]. The relationship between the dielectric constant of BST versus electric field is significant. In Figure 2-3 the polarization versus electric field for various Ba compositions under room temperature conditions. As the dielectric is the derivatives of these curves, it is seen from the s-shaped curve that the dielectric is highest at no bias, and decreases with increasing bias. 12

26 Summary BST as a dielectric has matured from a ferroelectric material with interesting properties to a material that is being utilized in many circuits and devices. The high dielectric constant of the material lends itself to high capacitances for an equivalent circuit size, which are beneficial for ever decreasing circuits and devices. The tunable behavior of the dielectric is also of interest to make circuits capable of operating in multiple frequencies or to provide in-situ healing capabilities. Figure 2-2 Dielectric Constant vs. Barium Content, x [23] 13

27 Figure 2-3 BST Polarization vs. Electric Field For different Barium Content, x [20] 14

28 2.2 Gallium Nitride Gallium Nitride is a III/V semiconductor material that is of particular interest to the growing demands of integrated circuit designers. While elemental semiconductors, such as silicon, uses an element from column IV of the periodic table, GaN is a compound semiconductor using Gallium from column III and Nitrogen from column V. When researching GaN it is important to first get an understanding of the properties of the material itself and then discuss applications and research trends. Material Properties In [24], [25] comparisons of GaN circuit dielectric properties are compared to other materials used, most notably silicon. In these articles, GaN is often referred to as a wide bandgap material due to its energy gap of 3.4 ev, which is large when compared to silicon which has an energy gap of 1.1 ev. This bandgap represents the energy separation between a conduction band and a valence band. By having a larger energy separation wide bandgap materials such as GaN have a larger electrical breakdown field. This allows for GaN devices to operate under much higher power and/or high temperature conditions compared to the traditional Si based circuits. Other advantages of GaN over Si presented in the reference include lower onresistances/lower conduction losses in GaN-based field effect transistors and Schottky diodes, low switching losses at greater than kilohertz frequencies even with power levels in the kilowatts, and high power per unit length allowing for high impedance lines for easier impedance matching. While GaN is a worthy material to study there are notable disadvantages to consider when utilizing this technology as also mentioned in [25]. GaN currently has a low processing yield, is costly to fabricate compared to Si, there are far fewer manufacturers so the material is not as easily available, and high-temperature packaging techniques are required. 15

29 Because of the fabrication issues mentioned there is not a GaN substrate sized to support a complete circuit yet available. This leads to a need to attach the GaN to another substrate by heteroepitaxy. Compatible substrates include sapphire, SiC, AlN, Si, as well as other complex oxides. Of these, SiC and sapphire are the most common [26]. The epitaxial layers are commonly grown by molecular beam epitaxy, metal-organic chemical vapor deposition (MOCVD), or by vapor phase epitaxy, Transistors Gallium Nitride based transistors typically are designed as high electron mobility transistors (HEMTs). HEMTs are a form of field effect transistors incorporating a heterojunction, referring to a junction between two materials with different bandgaps, in the channel of the device rather than a doped region. The heterojunction created by the different bandgap materials forms a quantum well in the conduction band where electrons can move quickly but cannot exit. This high mobility region, referred to as a two-dimensional electron gas (2DEG), is a byproduct of the lack of dopants in the dielectric material and thus has a very low resistance in the transistor s channel. As voltages are applied across the heterojunction the 2DEG region is altered affecting the conductivity of the layer. This changing conductivity can be manipulated to provide similar nonlinear performance as metal oxide semiconductor field effect transistors (MOSFETs). There are no oxides used in the creation of the HEMT device, so metal contacts come in direct contact with the dielectric. In the absence of specialized ohmic layers being present Schottky-barrier diodes are formed at these metal-semiconductor boundaries [27]. The resulting junction behaves like a diode, with the metal acting as the anode and the semiconductor as the cathode. 16

30 Schottky diodes conduct current by electron majority carriers so do not have the minority-carrier charge-storage effects of typical p-n junctions. As a result, Schottky diodes can be switched faster than p-n junction diodes. To avoid having all contacts of the transistor forming Schottky diodes, the source and drains are typically attached by including ohmic contacts on the metalsemiconductor boundary [24]. This allows current to flow in both directions for these terminals. As previously mentioned, GaN devices are primarily generated on sapphire and SiC substrates by heteroepitaxy. The transistor performance results at microwave frequencies of sapphire substrate devices are lower than those of SiC substrates [26]. To assist in a better understanding of why that is, it is beneficial to be have a reliable means of determining transistor model elements. Several papers have been published that research the behavior of GaN HEMT devices with the aim of creating small signal equivalent models [28 31]. These models can then be utilized in designing tool sets so that more integrated systems can be implemented utilizing the technology. In each of these references, the method of extracting the small signal parameters follows a procedure detailed in [32]. The method described separates the transistor into two categories, intrinsic elements which change with differing bias conditions and extrinsic elements which are independent of biasing. The procedure involves first measuring S Parameters with the device having a drain source voltage of 0 volts DC. This eliminates the effect of any voltage controlled current source element typically included in small signal models. Secondly by measuring the S Parameters at a gate bias below the pinch off voltage, the channel under the gate is turned off eliminating intrinsic gate capacitances and channel conductance. 17

31 Then by assuming symmetry between the gate and drain connections, extrinsic parasitic values can be removed in an outside-in method by use of transformations of the broadband S parameters into Z or Y parameters for both gate biasing above and below pinch off. Once the extrinsic elements have been found, the intrinsic element values can be calculated by creating best fit approximations of the S parameters of the model to actual HEMT device measurements under positive drain source biasing and various gate biasing. The model found for GaN transistors in [28] describes that in order to determine the extrinsic gate resistance by the method described in [32], required high positive gate biasing. This high gate biasing on GaN HEMTs physically alters the performance of the device. To overcome this high biasing condition least squares approximation is used to estimate both the gate resistance and gate inductance by using both real and imaginary Z parameters under low gate bias. The previous method required high biasing to eliminate the inductive effects thus leaving only the real resistive gate value. The resulting procedure showed excellent match to S parameters under four different biasing conditions for frequencies up to 40 GHz. In [29], small signal model parameters were found for GaN HEMT devices on SiC. The reference again attempts to focus on determining small signal element values by use of drain source biasing at 0 volts and positive voltages. However, the reference is primarily interested in quickly eliminating the extrinsic/parasitic capacitances associated with the gate and drain. This is done by use of analyzing the S parameters at 0 volt drain source biasing at high frequencies. This method thus avoids the need for dummy pads to determine these capacitances. In [30], GaN HEMT devices on sapphire substrate were analyzed for determination for small signal parameters. The reference notes the similar problem as described in [29], that the parasitic capacitances limit the ability to determine the rest of 18

32 the parameters in GaN HEMT devices. This reference uses the strong gate biasing to determine the capacitance values instead of the pinch off condition due to measurement uncertainties under those conditions. Gate biasing beyond a point reduces capacitive affects in the channel. It is under this condition that the parasitic capacitances are then determined. Finally in [31], another model extraction technique is described very similar to [30]. The model used includes many more parasitics than other references to be as complete as possible. In this procedure the 0 volt drain source biasing was used to provide initial approximations of extrinsic values. Then by applying strong gate biasing under this 0 V drain biasing, as well as active drain biasing. The values are refined by regressive analysis until a final model is determined. IDC In addition to HEMT devices, researchers have generated dedicated capacitors on GaN. A common approach is to use interdigitated capacitors over the active GaN region. By then including a DC bias condition across the two connections, the active region can be tuned, similar to a transistor, but using only two terminals rather than three. In [8], an interdigitated capacitor (IDC) circuit was placed above an active GaN region. The one port was a Schottky metal, while the other was ohmic contact. This structure thus is similar to a gate source or gate drain topology of a GaN HEMT, and thus is capable of being manufactured with typical HEMT fabrication procedures. The reference notes that by negatively biasing the Schottky contact, the 2DEG channel becomes depleted. This reduces the capacitance thus generating a varactor. The paper shows that the device has great tunability near the pinch off condition around -6VDC. The capacitance remains fairly consistent from biasing of -4V to 0V. The quality factor for devices in the tunable region range from 5 to 15 at 1.1GHz. 19

33 A slightly different device is analyzed in [6] where the two contacts of the IDC both generate Schottky diodes. This device thus has symmetric capacitance and Q Factor for positive and negative bias voltages. The device again has highly nonlinear CV curves near 6 volts of bias, which flattens near 0 bias. The Q factor for this architecture however is much larger than [8], ranging from 5 to 40 at 1.1 GHz. In [11], a very similar design to that in [6] is described, but this time the two terminals are placed above a 10nm thick oxide layer. The inclusion of this oxide layer thus reduces current through the device compared to HEMT compliant devices. By including the oxide layer the device still has a highly nonlinear CV curve, but the tunable range has shifted from the 4 volt bias to 9.8 volt bias. This device is thus capable of higher biasing; however the capacitance tunability has suffered. The capacitor changes from 75 to 10 ff, compared to 150 to 10 ff for the traditional HEMT design. A device similar to that previously described in [6], [8], [11] analyzes the effects of finger widths and separations on the capacitance and tunability of GaN-based IDC varactors is described in [10]. Again a GaN HEMT compliant device is tested with all devices built on Sapphire substrates. When the separation between fingers decreased from 20 m to 3 m, the capacitance of the devices increased by a factor of 4. The bias voltage range was similar for all devices however. A smaller effect on the capacitance was seen with the finger width variations. Wider fingers showed larger capacitances, but changing from 2 to 10 m only had a 40% increase in capacitance. Summary GaN devices continue to be an area of research for applications in microwave electronics. The material properties, particularly the wide bandgap of the semiconductor, lend itself to usability as a platform for high power electronics. Use of tunable electronics 20

34 is also of interest to make circuits capable of operating in multiple frequencies or to provide in-situ healing capabilities. 2.3 Applications of Varactors Possible applications of varactors include filters [33 41], resonators, antennas [42 47], phase shifters [48 62], and components in hybrid packaged circuits [63 68]. A table summarizing some key performance metrics of the applications listed as well as some design description details can be found in Appendix A. As BST films are useful in varactor technologies because of the ferroelectric properties, it is important to consider applications that can leverage the tunable nature of the dielectric. Most of the examples identified use the BST material as a varactor device, rather than a tunable element integrated in a higher order system. Two bandpass filters were generated in [33] which employ planar BST varactors. One filter was centered at 34 GHz while the second at 48 GHz. In each filter the no bias condition led to a 10 percent bandwidth. The center frequencies increased in each case by approximately 10% by applying a 30 volt bias. Importantly however, the filters had an approximately 5 db insertion loss in both designs. Two bandpass filters were created in [40] that had better tunable range than those of [33] though designed for different frequencies. One filter was built at 11.7 GHz center frequency while the other at 8.8 GHz. Both filters also implemented planar varactors. In both filters the center frequency was shifted upward by a little more than 20%. This came by applying a 100 volts bias in both cases. The tradeoff was that the insertion loss was 10 to 5 db depending on the bias condition. As a comparison, the performance of sandwich-type varactors in a bandpass filter centered at 175MHz is described in [41].This filter moves upward 55% when applying a low 6 volts of bias. The insertion loss is also consistently 3dB. As the 21

35 operating frequency is much lower than those previously mentioned, it is hard to compare directly the performance of these three filter topologies. Resonator and antenna BST references are relatively few [42 47]. As such they are hard to provide direct comparisons on tunability and antenna performance. In general the tunable center frequency was very small; changing roughly 2-3%.Devices implementing sandwich-type varactors had bias voltages ranging to volts, while planar designs ranged 200 to 400 volts. The integration of multiple two layer varactors in [43] were used in the tuning of a planar slot antenna. The antenna s match to a 50 ohm reference impedance was tunable across 500 MHz in the 5 GHz band, demonstrating approximately 10% tunability. The paper also demonstrates antenna radiation patterns, showing that the E-Plane beam pattern is similar to the expected shape, and thus the presence of the BST had marginal impact on the beam shape. To provide a comparison of the two varactor types the phase shifter of [48] and [57] are comparable systems. The sandwich varactor based phase shifter of [48] is a high impedance transmission line, with periodical shunt varactors. The reference describes the phase shifter s performance in terms of its highest measured frequency, 10 GHz. By applying up to 17 volts of bias, the phase changed approximately 240 degrees. The insertion loss of the phase shifter at this frequency changed from 3 db to 1.5 db. It is also important to monitor the bandwidth performance of the phase shifter as well. The insertion loss increased with increasing frequency, but was at most approximately 3.5 db. The phase shift also increased with increasing frequency, ranging to 180 degrees of phase shift at 8 GHz compared to the 240 at 10 GHz. The planar varactor based phase shifter of [57] is also best described as a impedance line with periodic shunt varactors along its length. The reference details the phase shifter performance in the 8 to 10 GHz range. The circuit provided an approximate 22

36 40 degree phase shift with applying 120 volts of bias. This phase shift increased with increasing frequency ranging from 30 degrees at 8 GHz and 45 degrees at 10.5 GHz. The insertion loss of this phase shifter also increased with increasing frequency, ranging from 1.8 db at 8 GHz and 4 db at 10 GHz. Insertion loss also improved after applying a bias by approximately 1.2 db for all frequencies. The two phase shifters analyzed above provide a good example of the role of the varactor type to the performance of a circuit. However, as the actual lines used in the circuit and the capacitance range of the varactors is not identical the comparisons are limited. Both devices have similar trends with regards to phase shift and insertion loss compared to frequency. Also the insertion loss improved in both cases under bias. This would seem apparent considering the nature of the phase shifter including shunt capacitances. As bias is applied the capacitance decreasing would decrease insertion loss. The planar phase shifter exhibits a flatter phase versus frequency response but the sandwich varactor phase shifter has better insertion loss performance. It is difficult to extract if this is due to the circuit design or varactor performance. The final area of BST varactor based technologies involves the use of the varactor as a capacitor with tunable capacitance. This includes higher level circuits such as matching networks, couplers, power dividers, and voltage controlled oscillators (VCOs). As these uses are widespread it is difficult to determine the quality that BST varactors provide for many of these circuits. To provide some level of insight the VCO described in [64] is analyzed. The VCO of [64] is comprised of component pieces attached to a circuit board. The BST varactor is a sandwich-type device which is tuned by applying DC voltage biasing up to 4.5 V. The circuit output a signal ranging from 216 MHz at no bias, to 205 MHz with 4.5 V bias, an approximate 5% shift in frequency. The phase noise decreases 23

37 with increasing frequency offset ranging from -90dBc/Hz at 10 khz to -140dBc/Hz at 1 MHz. In [68] the integration of BST layers in GaN technology is discussed. This is of particular interest for this dissertation as the two technologies of focus are combined. The paper does not actually develop any circuit or higher level implementation of high power transistors with varactors but is instead focused on the manufacturability concerns and quality of a single transistor or a single BST varactor. The key take away from the paper was that special SiO 2 layers are needed to protect epitaxial layers during the BST deposition process. If proper manufacturing steps or routines are not followed, the devices quality is severely negatively impacted. The addition of this SiO 2 layer and the associated etch processing is clearly not part of the traditional GaN foundry process, however the fact that a modern semiconductor process is compatible with the extreme fabrication environments necessary to create quality BST films is noteworthy for potential growth in truly integrated high quality ferroelectric varactor circuits. 24

38 CHAPTER 3 VARACTOR DESIGNS 3.1 Three Dimensional Varactor Design. The main objective of researching new varactors is to improve upon the quality of the devices that have already been researched or produced or develop methods of reducing total device size while at a minimum maintaining performance. The three dimensional varactor, utilizing an electroplate filled etched silicon technique, attempts to address both of these objectives simultaneously. The images of Figure 3-1 and Figure 3-2 show a side profile and top view respectively of a three metal layer, folded capacitor varactor structure. The overall design is similar to that described in [69]. The varactor utilizes Ba 0.6 Sr 0.4 TiO 3 as the BST composition. Preliminary rationale for developing the three dimensional varactor was presented in [70]. In this publication an etched silicon wafer was compared to a nonetched wafer. The etched device showed an approximate 60% decrease in capacitance compared to the non-etched case. As the devices from a top view perspective were identical, this change in capacitance could only be attributed to either dielectric thickness variations, or changes in the total device area a planarized vs. non-planarized metal alignment in the device. Evaluation of the tunability of the two devices was performed to reduce the likelihood that the BST material height was a significant change. As the material tunes 25

39 Figure 3-1 Cross-section of 3D Varactor Showing Biases according to an applied electric field, if the tunability curves are completely dissimilar to one another then the dielectric thickness should be considered a leading candidate for the change in net capacitance. In this case the two cases had approximately the same percent change under low bias conditions eliminating this from being a major contributor to the change in capacitance. The only remaining variable unaccounted for is the discontinuity of the metal to metal overlap in the BST varactor itself. Utilizing the parallel plate capacitor equation, this discontinuity can be thought of as a change in the area, as the top plate will have a capacitance along the side wall of the bottom plate. Solving for this change in area, then dividing by the bottom metal s width an increase of length of 2.87 m was observed. This is of note as the metal height of the bottom plate was approximately 1 m, leading to the realization that the non-planar varactor s capacitance was increased by the approximate height of the metal distributed across the two sides of the cross over path. 26

40 (a) (b) Figure 3-2 Top View of 3D Varactor (a) in total and (b) zoomed in to show the three overlapping capacitor regions The key takeaway is thus if a capacitor can be designed with significant height, the resulting capacitance of a two metal device can be increased without increasing the two dimensional area, the typical metric that IC designers are concerned with. The problem with growing metals too high in a non-planarized process is the physical limitations of achieving a conformal covering of one material with another. As the concept of realizing a varactor with a metal trenched in a silicon wafer had been proven however, a resulting planar bottom metal could be developed first, allowing for an approximately flat BST layer to be deposited on top. By then following the traditional non-etched process from this point forward two BST varactors could thus be stacked on top of one another. By carefully designing interconnections and geometries, highly 27

41 dense designs could be established, and thus three dimensional varactor concepts were established. As can be seen in Figure 3-1, this new design utilizes three metal layers, shown in yellow, and two BST layers, shown in blue. This relatively complex fabrication stack requires more fabrication efforts than previously utilized as more lithography steps are needed with the inclusion of more layers. This leads to a greater potential of having processing errors such as misalignment in any of the fabrication steps, hindering net device performance. The BST dielectrics for this device stack are 0.25 m thick deposited by pulsed laser deposition. The pulsed laser deposition system is seen in Figure 3-3. This system is capable of depositing BST over a four inch wafer substrate with good quality across the wafer. Notated in Figure 3-4 are the three overlap locations showing areas of parallel plate capacitance. From inspection of Figure 3-1 it is seen that capacitor C1 and C3 are actually identical in terms of dimensions and the signal biases that reside on the two sides of the capacitor. Both have the signal and bias 1 line on the top plate, and the ground on the bottom plate. This leads to the conclusion that the capacitance of C1 is equal to that of C3. Analyzing the parameters of C2 shows that the separation between its top plate, signal + bias 1, and bias 2 bottom plate, is larger than that of C1 and C3. Referencing equation 1, the capacitance of a parallel plate capacitor, the double thickness of separation of C2 will lead to a capacitance/square that is half that of C1 or C3. 28

42 Figure 3-3 Pulsed Laser Deposition System The separation between the ground on the left and right of Figure 3-1 is a key variable of interest for this dissertation research. As the two signals begin to converge on the horizontal boundaries of the DC bias 2 line, the potential electrical fields inside the barium strontium titanate become less vertical and can begin to take on more lateral shapes based on the bias present on both the signal line as well as the bias line. If the field lines begin to look less homogeneous across the surfaces of the plates, the capacitance will be less likely defined by the simple parallel plate capacitance equation and will become a more challenging task to estimate analytically. 29

43 Figure 3-4 Cross-section of 3D Varactor Showing Derived Capacitances Figure 3-2 shows a top view of the proposed varactor designed for this dissertation. In this image each layer is represented by a different color and pattern to attempt to visualize how the completed system aligns with each layer. As can be seen the device utilizes a coplanar waveguide feed on the left and right portions. This allows for easy on wafer testing by use of ground signal ground (GSG) RF probes. From the close up image in Figure 3-2 (b), it is easier to see the C1 and C3 are shown where the green and blue lines cross, while the C2 capacitor is where the green and violet lines cross. Completing the fabrication of this design is a large undertaking in terms of time. Combined with the previously mentioned complexities in alignment to produce quality components, a fabrication procedure becomes a necessity. This task has also been carefully planned out and a description of the procedure is explained in Table 3-1. A more visual description of how the cross section shown in Figure 3-1 and the top view of Figure 3-2 are created can be seen in the appendix. Simulation. In an effort to predict the performance of the 3D varactor electrical simulations are utilized. The designs previously utilized for BST fabrication by the group at the University of Dayton utilized two dimensional method of moments (MoM) based simulations. This solution works well for planar approximations of circuits, traditionally 30

44 Table 3-1 3D Varactor Diagrams of Manufacturing Steps Step # Description 1 Bare silicon wafer 2 Apply photoresist by spin coating 3 Expose etched metal pattern 4 Develop exposed photoresist & plasma etch underlying silicon 5 Clean unexposed photoresist 6 Deposit seed metal across wafer 7 Apply photoresist by spin coating 8 Expose etched metal pattern 9 Develop exposed photoresist 10 Electroplate to fill etched hole 11 Clean unexposed photoresist 12 Add BST thin film by PLD 13 Apply photoresist by spin coating 14 Expose metal 2 pattern 15 Develop exposed photoresist 16 E-Beam deposition across wafer 17 Liftoff 18 Add BST thin film 2 by PLD 19 Etch BST to expose bottom pads 20 Apply photoresist by spin coating 21 Expose metal 3 pattern 22 Develop exposed photoresist 23 E-Beam deposition across wafer 24 Liftoff done in circuit board simulations where lines can be approximated as being on one of a number of layers or sheets of either dielectric or conductors. The fields in these cases are thus primarily uniform in shape and direction, and the electric fields will either propagate vertically through dielectric layers or will be lateral if there are conductors on the same plane. The initial device concept of [69] has been exhaustively tested, and in [71] a paper describing variation of BST varactor performance on a single wafer was presented. In the paper variations of extracted capacitance as a function of position on the wafer were explained. Shown in the paper is a correlation between distance from center and capacitance. Again using the parallel plate capacitance equation, this change had to be due to variations in BST thickness. These variations however were less than 31

45 20% reduced when moving more than 10 mm away from center. A 10% component value variation could thus be guaranteed for several hundred devices on a wafer. The material s quality factor and tunability were demonstrated in this publication as being consistent across the wafer as well. This demonstrated that the material properties, including those presented for the basis of modeling for this and future works are statistically validated. It is this validation that drives the simulation parameters that effect future designs prior to fabrication. As described in the design of this section, the proposed varactor may produce electric fields in multiple directions and possibly not uniformly. This design will thus be incorrectly modeled by MoM simulations so alternative solvers need to be utilized. To simulate this proposed device, the finite element method (FEM) three dimensional solver EMPro is utilized. As a comparison of the quality of the solver Table 3-2 shows comparisons of the capacitance of a number of varactors under no bias. The first two entries in the table are a comparison of a fabricated and simulated two dimension varactor that has previously been analyzed and discussed [69]. The values of the simulation show a 22% error. This is thus a relatively ineffective solution but other parameters such as parasitic losses as well as the assumptions used in the simulation may be the cause of these errors more than the solver itself. The last row is the expected capacitance of the proposed shunt 3D varactor. This device is approximately 2.5 times the two dimensional simulation case. When comparing this result to the equation 1 parallel plate capacitor equation, this is expected. C1 and C3 have the same physical area and separation as the 2D varactor simulated. As these are in parallel with one another, the expected contribution to the overall capacitance should be double. The C2 capacitance has the same area as C1 and C2, but has twice the 32

46 separation due to the two BST depositions. C2 should thus have half the capacitance as C1 or C3. The sum of the parallel capacitors should thus be 2.5 times the 2D varactor. Table 3-2 BST Capacitance of FEM Simulations and Fabricated Devices Name Capacitance (pf) 2D Device Test D Device Simulation D Device Simulation 2.28 More exploration will need to be done to determine how the bias will affect the parallel combination of these devices. As the FEM tool requires dielectric properties to solve the circuit performance, these simulations cannot be predicted prior to fabrication. Fabrication. The detailed steps of Table 3-1, as mentioned, are labor intensive and through this process minor necessary adjustments were realized. The electroplating process of step 6 proved a lithographic challenge. The problem was in the use of lithographic masks to complete the processes. The same mask was thought to be useful for both the definition of the geometries needing a silicon etch as well as the electroplating growth regions. The challenge was that it was impossible to align the electroplating lithographic hole atop the same sized hole of the existing etched location. The result was that during the electroplating growth, metallic hillocks would appear at most wall boundaries. The size and quantity of these gold hillocks made chemical mechanical polishing difficult. The next evolution in the process was to add an additional mask used in the silicon etch stage that would allow for a larger etch dimension, leading to a planned and predictable over-etching of the silicon substrate material. The openings for the electroplating would be the original dimension, which now appeared as a smaller scaled version of the etched geometry. 33

47 Hillocks still appeared under this operating methodology; however, these were now along a photoresist boundary, which was removed after the completion of the electroplating. After this removal an equally challenging concern was that the metal now no longer stopped flush against all the walls of the etched hole. The final attempt to achieve a cleanly filled silicon etch point was the use of a heat treatment after electroplating. The wafer was placed in a vacuum chamber where it was pumped down to a pressure of approximately 1 Torr. At this point the wafer underwent a 30 minute heat up to 1000 Celsius, maintained that high temperature for 30 minutes before cooling down to room temperature again. The treatment did reduce some height of the peaks at the hillocks, but the metal cohesion also began to pull some content further from the wall boundaries. (a) (b) (c) Figure 3-5 Evolution of etched silicon electroplating Port BST Varactor Design. The images of a Figure 3-6 and Figure 3-7 show top views of first a previously analyzed device described in [69] and a new 1-port device. The varactor utilizes Ba 0.6 Sr 0.4 TiO 3 as the BST composition. The intended application of this device is in a hybrid packaged circuit implementation where this device can provide a shunt or 34

48 adjustable bypass capacitance to ground. This device will thus have two electrical connections, a signal and a ground. The design is thus effectively cut in half in the vertical direction compared to the original layout. The input consists of a ground signal ground coplanar waveguide feed structure, however the signal line ends in the middle of the overall structure. There still exists an overlap parallel plate capacitance between the center signal line and a bottom metal plate. This overlap area is also designed to be the same dimensions as the original design seen in Figure 3-6. Figure 3-6 Top View of 2-Port Shunt BST Varactor 35

49 Figure 3-7 Top View of 1-Port BST Varactor Simulation. In an effort to predict the performance of this single port design again method of moment simulations are utilized. The AWR AXIEM electromagnetic field solver software was used to determine a two dimensional method of moments (MoM) simulation of each varactor. As both the 1-Port device and the original 2-Port shunt device are simple two layer structures, a two dimensional electromagnetic simulator is sufficient. The AXIEM simulation consisted of a two layer dielectric, with the bottom metal residing on layer one, and the top metal on layer two, the BST layer. As the port connections are CPW, the simulation was configured so that three ports were placed on 36

50 each port, one for the signal line and one for each of the associated ground connections. The four ground connections were later set to ground in a post processing environment. The resulting S Parameter outputs of the 2-Port device were matched to a four element schematic resistor, capacitor, and inductor network model. The same model was used to extract the 1-Port device characteristics. Analysis found that the two varactor designs were very well matched to one another in terms of initial design capacitance. The simulation results thus achieve the objective of generating a varactor that should behave extremely similar to those previously designed and reported in [69 71], but is only a single port device. 3.3 Gallium Nitride Varactor GaN varactors have been designed previously by researchers, however while most are foundry system compliant, they almost inevitably avoid foundry manufacturing to allow the researcher tighter control on the actual fabrication. While this can be advantageous in the optimization of a single component s performance, these subtle changes will not necessarily be adopted by foundries. To avoid this, a foundry process as the technology provider was a design criteria chosen in this research. To utilize the GaN transistor as a varactor it is helpful to understand the geometry of the transistor. A cross section is shown in Figure 3-8. In yellow are the gate, source, and drain contacts that are connected to the various circuit components. Based on the physics behind conductor to dielectric transitions, a Schottky diode can be created at the interface if the material resistance is not chosen correctly. An extra ohmic contact, shown in orange, is used to prevent this diode effect. The purple layer is the epitaxial layer indicating the active region of the device. It is in this region that the 2DEG layer will be generated that dictates the HEMT transistor behavior. The 2DEG region is marked by the thin red layer. 37

51 Figure 3-8 Cross Section of GaN Transistor Figure 3-9 GaN Device Cross Section with Representative Lumped Elements The image of Figure 3-9 shows the high level equivalent circuit components associated with the GaN cross section. As can be seen the gate has a diode flowing into the active area of the device. There is a small series resistance path connecting the 2DEG region to the source and drain connections. A small signal equivalent model of a GaN HEMT is shown in Figure The figure includes many parasitic capacitances and inductances generated from the interconnection of the device to the testing probes, as well as other small parasitics due to the device geometry. Each of the three terminations of the device includes a series inductance and resistance, L g, L s, L d, R g, R s, and R d. These are generated by the metal traces and interconnections of the device to other circuits or components. Two similar resistor- 38

52 Figure 3-10 Complete Small Signal Transistor Model of GaN HEMT Device capacitor paths are generated between the gate to the two remaining transistor paths. Each path s capacitance, C gs and C gd, is generated in a small amount by the coupling between the gate contact and the source or drain terminations, and to a larger amount by the 2DEG channel underneath the metal contacts that varies based on the electric fields. The parallel resistor elements, R gsp and R gdp, are thus the quality of the dielectric used in the associated capacitor formations, while the series elements, R gs and R gd, are primarily generated in the lateral current paths through the 2DEG and out the Ohmic contacts of the drain and source. The last path is thus the drain source path which has a current gain path determined by the gate source field presence. Again there are parasitic loss elements, this time generated by the weak air filled capacitance between the source 39

53 and drain, and again the current loss elements of traveling down to the 2DEG layer from the drain and back out on the source side. A top level view of a HEMT transistor is shown in Figure In this topology multiple transistor gates are utilized. If this device were utilized in an amplifier, this would increase the overall device width, and thus increase available gain. However as the desire is to generate a passive capacitor component this is not the intent of using a multiple finger device. As described in [72] by connecting the source and drain, the drain source capacitance becomes marginalized and the two gate capacitances will dominate the circuit performance. If we compare the original HEMT top level implementation to that in Figure 3-12 this tunable capacitance becomes reinforced as the topology resembles that of an interdigital capacitor (IDC). Most of the existing GaN varactors in the literature exist in a cathode to cathode Schottky configuration. In this configuration no ohmic metal is used, thus avoiding a reduction in quality factor from the presence of a series resistance from the metal stack up. Also, even though one diode will always be forward biased, the pair will be reverse biased limiting current through the device. In most foundry processes however, the gate metal for the transistor is done during a different metal process step than those of other metal layers. This much narrower layer can thus be placed within the gap of two adjacent metals leading a smaller gate to source or drain metal distance. Thus by using a transistor as the basis of a varactor, the metal separation distance can be reduced by a factor of two. This can thus improve dielectric series resistance losses also improving quality factor. The tradeoff is thus the addition of the series/drain ohmic losses. As the GaN is developed for this research at an outside foundry, the use of standard transistor templates avoids design tradeoffs to ensure a foundry compatible 40

54 and clean layout. By connection of the source and drain to one another a non-linear gate-source and gate-drain capacitance is created. While the tunable capacitance has been demonstrated in literature, the specific capacitance results of the particular layout with the foundry used are not known initially so seeking specific design parameters to achieve a desired capacitance is not possible. Due to space and budget constraints only two varactor topologies were generated, shown in Figure 3-13 and Figure These two topologies were chosen to have a Figure 3-11 Top View of GaN HEMT Device 41

55 Figure 3-12 Top View of GaN HEMT Device Configured as a Varactor Figure 3-13 Top View of 2-Port Series GaN Varactor 42

56 Figure 3-14 Top View of 1-Port GaN Varactor traditional series tunable element, the 2-Port device of Figure 3-13, as well as a 1-Port device that can be implemented in hybrid packaged circuits and can thus be compared to the BST device described in the previous section. To predict to some degree how a variation to device layout would affect performance, the fundamental transistor used in both varactors was the same as that of a single HEMT device available for characterization, Figure A second single HEMT device was also available for characterization that differed from the device of Figure 3-15 only by a reduction of the number of gate fingers from six to four, Figure By complete analysis of these two HEMT devices, a scalable factor based on gate fingers can be determined and compared to other interdigital circuit results from the literature. 43

57 Figure 3-15 Top View of 6x100 GaN HEMT Transistor Figure 3-16 Top View of 4x100 GaN HEMT Transistor 44

58 CHAPTER 4 INDIVIDUAL DEVICE PERFORMANCE 4.1 Test Environment In order to determine the device performance for the various varactors described in Chapter 3, specific test equipment is needed. As both the GaN and BST varactors are not packaged, a probe station is used to establish electrical connectivity. Common to both device topologies are coplanar waveguide feed networks. For this reason, ground signal ground (GSG) probes from Cascade were utilized. To collect frequency swept S- Parameters, a HP8720B Network Analyzer was utilized. As the varactors will require bias voltages across their one or two ports, bias tees were needed. To accomplish this Picosecond Pulse Labs models 5545 and 5531 were used. Also a Keithley 2400 Source Meter was used to both supply voltage biasing as well as monitor supply current. An image of the complete setup testing a varactor device can be seen in Figure 4-1. Schematic block diagrams of how the bias configurations were implemented in the various test cases can be seen in Figure 4-2 and Figure

59 Figure 4-1 RF Test Bench Setup Figure 4-2 Testing Block Diagram for 1-Port Varactors 46

60 Figure 4-3 Testing Block Diagram for 2-Port GaN Devices 4.2 Testing Methodology For each of the devices; a 2-Port Shunt BST varactor, 1-Port BST varactor, 2- Port GaN varactor, 1-Port GaN varactor, 6x100 GaN HEMT, and a 4x100 GaN HEMT; S-Parameters were collected from 130MHz to 10 GHz at a -10dBm signal level with the network analyzer. These parameters were collected for bias voltages ranging from 0 volts to at least 6 volts in 0.2 or 0.25 volt increments. These measurements were repeated for at least three copies of each of these devices to ensure statistical significance and avoid potential anomalies. Once raw data was collected, the data was input into AWR Microwave Office. For the varactors, a schematic model was built in the engineering software tool identical to that in Figure 4-4. An optimization routine minimizing the error between the measured S- 47

61 Parameters to those of the schematic model by altering the four components respective values was performed. Each of these values was stored in a spreadsheet associated with the given bias voltage condition for plotting and model building purposes. A similar procedure was run on HEMT devices using the schematic of Figure 4-5. This testing method for GaN devices is similar to the Cold testing condition of [30], [31]. Previous testing methods were not as exhaustive in the number of data points sampled, so by combining hot and cold testing the behavior was extracted with fewer measurements. The advantage of following the testing procedure of this research is the potential damaging of over driving a gate source voltage is removed, at the expense of more data points being needed. However, to be complete more points should be used to ensure inherent electrical elements are as predicted. Another advantage to doing this testing is the greater potential of generating a wide frequency applicable model. Most other papers only extract values at a narrow or specific frequency. Others only do parameter extraction based on S-Parameter value extraction. By building a performance matched schematic representation for each data set, more accurate representations of the balances between the parasitic losses are determined. If the device being measured is terminated on the 1 port to ground, or if using either the GaN or BST 1-Port devices, the relationship between the reflection coefficient and load impedance is related by the well-known equation. (Eq. 4) This equation can be restated to find the load impedance if provided an S parameter file as follows. (Eq. 5) 48

62 Knowing that the impedance equation for a capacitor is (Eq. 6) A first order approximation of the capacitance for the 1 port varactor capacitance at a given frequency can be found by utilizing the * + (Eq. 7) Ideally the real component of the load impedance is zero; however, from the measured S parameters a first order approximation of the devices series resistance at a given frequency is equal to the real part of Z L at that frequency. Figure 4-4 Varactor Lumped Element Model 49

63 Figure 4-5 Simplified Small Signal Model for HEMT Devices While this method provides quick approximations of C and R terms, this technique is highly frequency dependent due to the severely simplistic approximations and number of elements used. 4.3 Rationale for the Varactor Small Signal Model The figure of the small signal model of Figure 4-4 can be arrived at abstractly for both GaN and BST varactors based upon device architecture physics. BST The basic architecture of the BST varactor is, as previously described, a parallel plate structure separated by a thin layer of BST dielectric. The C term in the model of Figure 4-4 is thus a direct representation of the capacitance between the two plates. 50

64 As the dielectric material is not perfect there will be the potential of direct current to leak between plates. This leakage current is expressed by the R P term. The last two elements, R S and L, both come from the two electrical plates themselves. As the metals are not perfect conductors, the material s resistivity is responsible for the model resistance. Similarly the top and bottom metals will generate mutual inductance on each other, as well as generating a self-inductance on each plate. The source of both the R S and L terms are generated on either end of the capacitor so the two elements could be placed on either side of the capacitance model term. However, schematically the series resistance and inductance can be combined and placed on one side of the capacitor GaN The evolution of the GaN varactor model can be deduced from the evolution of the established HEMT small signal model, given the parameter constraints brought about from the implementation of the transistor in the layout of the varactor. By starting with the HEMT small signal model of Figure 3-10 the first step is to realize that the varactors all make connections between the source and drain terminations. By shorting these two pins, the small signal s voltage dependent current source cannot generate drain-source current. However, the presence of this current source is still present and will thus effectively act as a gate voltage controlled switch or potentiometer. This is the reason the current source does not appear in the simplistic HEMT model of Figure 4-5, but is instead replaced with an R ds term. As the R ds term was just described as having a short circuit in some cases and resistance in others, the two limiting cases, R ds is a short or R ds is an open, are analyzed in the implementation of a GaN varactor. In either case, the gate-source path and gatedrain path are schematically parallel. As such, the same overall structure in each path can be combined, generating a single path from input to output from the parallel 51

65 combination. At this stage the overall schematic has reduced to a capacitor with series resistors and inductors on either side. As in the BST case, these series elements can be combined and placed on one side of schematic. The final result of the GaN varactor model is the same small signal model of Figure 4-4. The resulting model of Figure 4-4 is similar, and can be thought of as a compromise between, the models of [10] and [9]. The improvement is the inclusion of the inductor L from the lines feeding the terminals of the varactor. 4.4 Device Measurements RF As the GaN varactor devices were all implemented using the same HEMT geometry, it is of interest to demonstrate reproducible results while validating that the simple varactor model above still holds. For this reason Figure 4-6 compares the CV curve of the two different varactor layouts as well as the combination of the two gate capacitances of the HEMT transistor found from extraction of the HEMT model in Figure 4-5. Each of these curves is comprised of an average of results of three individual CV curves measured of the designated circuit type. All three topologies are very similar, with the same voltage transition point around -2.5 volts of gate source bias clearly seen in all cases. 52

66 Capacitance (pf) Capacitance (pf) 6x100 Based Devices Gate Bias (Volts) 1-Port Varactor 2-Port Varactor 6x100 HEMT (Cgs + Cgd) Figure 4-6 CV Curve of the Three 6x100 GaN Devices Analyzed Combination Capacitances in HEMTs Gate Bias (V) 4x100 HEMT (Cgs + Cgd) 6x100 HEMT (Cgs + Cgd) Figure 4-7 CV Curve of the Two Measured HEMT Topologies 53

67 }Gate Current ( A) Capacitance (pf) Extracted HEMT Capacitances Cgs - 4x100 Cgd - 4x100 Cgs - 6x100 Cgd - 6x Gate Bias (V) Figure 4-8 Extracted Individual Element CV Curves of two HEMT Sizes 10 Bias Currents in HEMTs x100 4x Gate Bias (V) Figure 4-9 Bias Currents for Two HEMT Topologies, Vds = 0V As mentioned previously, size constraints on the foundry built wafer limited the exploration of multiple varactor sizes in terms of length and width as parameters affecting capacitance values. However, the addition of a second, four fingered HEMT 54

68 device allows a glimpse into how different sized GaN varactor devices would perform by analyzing a slightly smaller HEMT device. Figure 4-7 again shows the CV curve of the combination of two gate capacitances. The same transition point of approximately -2.5 volts of gate source voltage is seen, however the capacitance value is reduced. This smaller value is approximately 70% that of the larger six finger transistor. The two gate capacitances for each device size are shown on the same graph in Figure 4-8. Again the 4x100 device s capacitances are approximately 70% of the 6x100 device. As mentioned previously the overall topology of the GaN varactors is roughly an IDC. As noted in literature, [73 75], the expected capacitance variation should grow proportionally to the number of gate fingers. As this is comparing 4 fingers to 6, the expected ratio would be 66.7%. The measured 70% is in agreement with these findings. In both HEMT sizes, the gate source capacitance is approximately three times the gate drain capacitance. As both drain and source were grounded in these measurements the two capacitances would be expected to be close to one another. While the source connection was directly tied to the back side metal through a via, the drain was the connection used for measurements and was grounded externally through a bias tee. Due to the method of extracting the values of the components by only using drain source voltages of zero the distribution of the capacitances between the two paths could be slightly off. The agreement of the HEMT to the varactor CV curve leads to the conclusion that while the distribution between gate drain and gate source capacitances may need to be further investigated the total device gate capacitance is properly determined. Another variable to compare in the performance of different sized HEMT devices that can be used in varactor elements is the bias currents. Shown in Figure 4-9 are the gate bias currents of the two sized transistors. From the graph the smaller device draws 55

69 less current, as would be expected due to the lower gate periphery. The proportion of the two currents over the bias sweep changes however. Below the bias where the CV curve begins to change, gate bias of -3V, the 4x100 device is approximately 20% that of the larger device. As the bias increases, slowly the two currents converge. This would be in agreement with the general device physics as the device is beginning to behave as a diode and the formation of the 2DEG layer is generating a low resistance path. This low resistance path appears as a converging of an on resistance despite two differently sized transistors. Key BST varactor results can be seen in Figure 4-10, Figure 4-11, and Figure 4-12 while GaN results are shown in Figure 4-13, Figure 4-14, and Figure The Q- Factor depicted in the two graphs for each type is determined by the extracted 4 element values of Figure 4-4, and then used in Eq. 8. ( ) (( ) ) (( ) ) (Eq. 8) As seen from the CV curve graphs of Figure 4-10 and Figure 4-13, both device technologies cover a 0.7pF to 0.9pF value in their tuning range. Note that Figure 4-13 is now a composite average of both varactor types shown in Figure 4-6. Both devices also have the most tuning range at biases less than 5 volts. The BST device has better tunability, 66.3%, than the GaN varactors at 42.3%. The GaN varactor has an odd function characteristic to its CV curve while BST is even at 0 volt bias. 56

70 Q Factor Capacitance (pf) BST Varactor CV Curve Bias Voltage (V) Figure 4-10 Measured BST Varactor CV Curve Quality Factor of BST Varactor Bias Voltage (V) Q 1 GHz Q 10 GHz Figure 4-11 Measured Quality Factor of BST Varactor 57

71 Capacitance (pf) Quality Factor Quality Factor Versus Frequency (BST) V 1.0 V 2.0 V Frequency (GHz) Figure 4-12 Frequency Dependency of BST Varactor Quality Factor GaN Varactor CV Curve Gate Source Bias (V) Figure 4-13 Measured GaN Varactor CV Curve 58

72 Quality Factor Q Factor Quality Factor of GaN Varactor Gate Source Bias (V) Q 1 GHz Q 10 GHz Figure 4-14 Measured Quality Factor of GaN Varactor Quality Factor Versus Frequency (GaN) V -3.0 V -2.0 V Frequency (GHz) Figure 4-15 Frequency Dependency of GaN Varactor Quality Factor The quality factor in both technologies is approximately similar. Where the GaN varactor really suffers however is in the larger signal biases at higher frequencies, i.e. above -3 volts on the 10GHz Q-Factor graph. This is because the varactor biases to a higher capacitance at these conditions and due to the series resistance presence, the 59

73 devices quality suffers. Also comparing the relationship with frequency there is a quick decline in quality factor as frequency is increased. When recalling that the concept of quality factor is the ratio between energy stored and energy dissipated, which correlates to the imaginary and real impedance components, the quality factor curves are similar to impedance versus frequency curves of a capacitor. The only way to maintain or at minimum extend a high quality factor to higher frequencies is to eliminate any resistive effects. As the varactor tunes the capacitance, the quality factor would tune as well, unless the resistive losses were inversely correlated to the resulting capacitance. Temperature Real electronic systems, particularly RF amplifier circuits, dissipate a lot of heat and may be operating in various temperature environment ranges. These variations in temperature are an important variable that should be explored to validate the usefulness of a device before it can be adopted in a circuit. For this reason RF testing under multiple temperatures for both the GaN and BST one port varactors was performed. The same network analyzer, bias tee configuration, and CPW probes were again used to collect scattering parameters of the devices. To create controlled temperatures, a Melcor MTTC1410 Thermoelectric Temperature Controller and Thermaltake Tribe CL- W0020 radiator cooling system were used to heat the stage that the devices were placed on. The temperature controller was set and maintained at a specified temperature for at least five minutes before data was collected. Four bias conditions were collected for each temperature before moving to the next determined temperature. The temperatures were incremented in ten degree increments ranging from 20 o C to 100 o C. The process was done for both BST and GaN single port varactor designs, with the bias voltages chosen for each case determined by key biases along the CV curves presented previously. 60

74 Series Resistance (Ohms) Capacitance (pf) Measured BST varactor capacitance and series resistance performance over the eighty degree range tested are presented in Figure 4-16 and Figure Similarly, GaN performance is plotted in Figure 4-18 and Figure BST Varactor Capacitance vs. Temperature V 0.5 V 3.0 V 3.5 V Temperature ( o C) Figure 4-16 Capacitance Versus Temperature of BST Varactor BST Varactor Series Resistance vs. Temperature Temperature ( o C) 0.0 V 0.5 V 3.0 V 3.5 V Figure 4-17 Series Resistance Versus Temperature of BST Varactor 61

75 Series Resistance (Ohms) Capacitance (pf) GaN Varactor Capacitance vs. Temperature V -2.5 V -3.0 V -6.0 V Temperature ( o C) Figure 4-18 Capacitance Versus Temperature of GaN Varactor GaN Varactor Series Resistance vs. Temperature Temperature ( o C) -2.0 V -2.5 V -3.0 V -6.0 V Figure 4-19 Series Resistance Versus Temperature of GaN Varactor 62

76 First, the range of capacitance tuning plotted is in close agreement with the curves shown in Figure 4-10 and Figure 4-13 of the room temperature RF testing conditions. In both lumped elements and between both varactor types, variation in the values of the elements were less than 10% across the temperature range, and less than 5% for most test conditions. More importantly however was the presence of correlations within the temperature sweep. The BST film should be above the Curie temperature for all temperatures swept, so there should not be an affect of a ferroelectric/paraelectric phase transition on the results. For the BST varactors the tuning range appeared to reduce as the temperature increased. The low bias capacitance decreased while the high bias condition demonstrated decreasing capacitance. The series resistance element however showed a nonlinear relationship with temperature, but variations again were 5% different than the room temperature condition. For the GaN varactor both the series resistance and the capacitance increased with temperature. This relationship was true for all four bias conditions tested. Temperature effects were generally stronger with decreasing bias voltage with regard to capacitance, while the resistance had stronger correlation with increasing bias voltage as temperature increased. DC The other thing to consider in both varactor cases is the DC operating conditions, primarily current draw. Figure 4-20 shows the current for the two 1- Port varactors described, the BST in blue and GaN in red. As can be seen the two devices draw similar currents in the negative bias voltage conditions. On the positive bias side, the GaN device begins a forward biasing of the Schottky diode, and thus quickly draws a lot of current. 63

77 Capacitance (pf) Current (ma) DC Current (ma) 1.E+02 1.E+01 1.E+00 1.E-01 1.E-02 1.E-03 1.E-04 1.E-05 1.E-06 1.E-07 1.E-08 1.E-09 Varactor IV Curve Bias Voltage (V) BST GaN Figure 4-20 DC IV Curve of BST and GaN Varactors BST Voltage Bias Dependencies Capacitance Current Bias Voltage (V) Figure 4-21 Capacitance and IV of BST Varactor 64

78 Capacitance (pf) Current (ma) GaN Bias Voltage Dependencies Capacitance Current Bias Voltage (V) Figure 4-22 Capacitance and IV of GaN Varactor The overlapping curves of Figure 4-21 and Figure 4-22 are beneficial in identifying the useable range of the varactor devices in RF applications. As the capacitance is variable based on the bias voltage the small signal quiescent current can be established by looking at the respective current curve at the same X-Axis location. It is worth pointing out the steep current increase above 1 volt bias, as above zero volts the diode of the device is forward current biased. As this forward biased current quickly escalates a maximum desirable voltage can be established. As an AC or RF signal will have voltage waves based on supplied signal power, the device can be thought of wavering left and right of the respective DC device curve. The larger the power, the larger the voltage swing, and thus the more dynamic the current and capacitance changing will be. If a signal power should be so large as to forward bias the diode varactor in the GaN device for a brief instance, an undesirably large device current can be generated. Simultaneously if a large swinging voltage is applied across the thin-film BST based varactor, the device may reach or exceed the maximum electric field level the material can support and thus permanently damage the 65

79 component. In both technologies there is thus the need to establish maximum and minimum safe operating conditions. Establishing maximum or minimum desirable voltage or voltage determining current will influence maximum AC voltage peaks. This limit will determine maximum usable power as well maximum and/or minimum bias voltage. This restriction on bias voltage can also negatively impact maximum and minimum tunable capacitance values. By understanding the DC operating conditions presented maximum and minimum safe operating conditions in terms of both DC biasing as well as RF signal power handling can be established. 4.5 Non-Linear Varactor Modeling After the lumped element values of the varactor schematic model had been tabulated, statistical trends of the parameter with respect to the bias voltages were determined. These trends would be put into a Verilog-A model that can be implemented in many electrical simulations tools, such as Agilent s Genesys [76]. Verilog-A is a programming language that has inherent support of electrical current and voltage equations for linear, non-linear and passive expressions. For the BST varactors, both the series resistance element, R s, and the capacitance term had a dependency on voltage, while the inductance and parallel resistance term were relatively constant across the tuning range. A second order expression was used in the model of the series resistance. This model curve and measured curve can be seen in Figure A fourth order expression was used in the capacitance curve shown in Figure Both of these models are relatively low order, but still provide a good match to measured performance. 66

80 Capacitance (pf) Series Resistance (Ohms) BST Varactor Series Resistance Measured Model Bias Voltage (V) Figure 4-23 Modeled BST Series Resistance, R s BST Varactor CV Curve Bias Voltage (V) Measured Model Figure 4-24 Modeled BST Capacitance 67

81 Capacitance (pf) Series Resistance (Ohms) GaN Varactor Series Resistance Measured Model Gate Bias (V) Figure 4-25 Modeled GaN Series Resistance, R s GaN Varactor CV Curve Gate Bias (V) Measured Model Figure 4-26 Modeled GaN Capacitance The GaN parameters were all effectively constant across the bias range with the exception of the capacitance. To demonstrate the flat response and also demonstrate a comparison to the BST device, the series resistance as a function of voltage of the GaN 68

82 device is shown in Figure The CV curve of the GaN varactors is best described as having a hyperbolic tangent dependence on bias voltage. This is in agreement with prior HEMT models [77]. A noticeable change is that the original Angelov model mentioned in [77] is overly simplistic for the presented varactor case. The referenced model lists ( ( ))( ( )) (Eq. 9) ( ( ))( ( )) (Eq. 10) where ( ), ( ), ( ), and ( ). As the varactors are implemented with zero drain source voltage, & reduce to constants resulting in ( ( )) (Eq. 11) ( ( )) (Eq. 12) but the ranges of both expressions are zero to twice the gate coefficient and the newly defined constant. As shown in Figure 4-26, there is a necessary capacitance offset leading to a ( ( )) (Eq. 13) While the capacitance voltage equations can be modeled, it is important to be sure that the CV curves are implemented correctly in the simulator. As a review of the relationships between current voltage and capacitance we start with Maxwell s equations. Starting with Gauss s Law the charge within a parallel plate capacitor volume is determined by ( ) ( ) (Eq. 14) The electric flux density is defined as the convolution of the permittivity of the dielectric of the capacitor and the electric field contained within the volume. In the varactor case, the capacitance is voltage dependent. In the devices explored in this research, the component geometries are unchanged, thus the capacitance variations are from modifications to the dielectric permittivity. Reforming Eq. 3 to reflect this results in 69

83 ( ) ( ) (Eq. 15) Applying this dielectric permittivity to the Gauss s law equation above results in ( ) ( ( )) ( ) (Eq. 16) Again, as the geometry is constant the bounds of the integration are fixed given the volume containing the varactor s electric fields. Also, the time varying electric field is determined only by the voltage across the two conductors of the varactor. The direction of the field is also oriented in the direction of the d dimension. This reduces the integration surface to only the plane parallel to the plates. The combination of these limits results in the following charge expression ( ) { ( ( )) ( ) } (Eq. 17) Combining Eq. 17 and Eq. 15 results in ( ) ( ( )) ( ) ( ( )) ( ) (Eq. 17) Applying the integral form of the Maxwell charge conservation, or continuity equation results in ( ) { ( ( )) ( )} (Eq. 18) Thus to properly simulate the voltage dependent capacitance in the presence of a time varying voltage, the charge equation of Eq. 17 should be used The exact Verilog-A code used for each of the technologies can be seen in the Appendix of this dissertation. An image of the Verilog model being implemented in Genesys can be seen in Figure The various parameters match either capacitance coefficients of the GaN CV expression previously shown, the series resistance, series inductance, and parallel resistance. 70

84 Figure 4-27 GaN Varactor Verilog A Model in Genesys 71

85 Figure 4-28 Measured 1-Port GaN Varactor S 11 Figure 4-29 Verilog Model Simulation 1-Port GaN Varactor S 11 72

86 Table Port GaN Varactor Measured and Verilog Model S 11 Bias 0 V 2 V Magnitude Angle 73

87 Bias 3 V 5 V Magnitude Angle 74

88 Figure 4-28 and Figure 4-29 both show the S 11 response of the 1-Port GaN varactor first measured and second simulated under three DC biases. As seen the Verilog curves are in good agreement with the overall measured results. Also shown in the figures within Table 4-1 are the separated magnitude and phase components under different bias conditions comparing measured and modeled varactor performance. Given the accuracy of the models, they will be utilized in the design of a filter for reasons of comparing performance across both BST and GaN technologies. 75

89 CHAPTER 5 VARACTOR DEVICE IMPLEMENTED IN A FILTER CIRCUIT 5.1 Filter Design Having arrived at Verilog-A models parameters, the next step is to test the validity of the models in a specific application that can compare the two varactor technologies. This design objective can also be used as a proof of concept, validating the use these novel varactor designs in circuits needed by the microwave and RF industry. A rather simple design chosen to test each of these architectures is a singlepole filter with blocking caps to provide a DC offset. The basis of the design is shown in Figure 5-1. The design is a shunt inductor shunt capacitor band pass filter. The two technologies will use the same filter and be tested under different bias voltages to ensure the filter tunes. A second test is to compare the performance of the filter under various signal input power levels. As the focus of the research is microwave and RF applications, components capable of operating under high power conditions can be necessary, particularly in transmitter applications. The filter board is implemented on 2 layer FR4 printed circuit board. An image of the board is shown in Figure 5-2. The board s back side is a solid ground plane, thus resulting in a microstrip implementation. To provide the blocking capacitance and DC bias inductor, surface mount components were included. A close up image of the components mounted to the board can be seen in Figure

90 Figure 5-1 Schematic Diagram of Designed Circuit Board Filter Figure 5-2 Realized Circuit Board Filter 77

91 Figure 5-3 Surface Mount High-Pass Portion of Realized Circuit Board Filter An added design consideration was the avoidance of complicated packaging criteria to connect varactor pieces not originally meant to be packaged. Instead, it was desired to implement a means to use the existing on-wafer GSG probes. To do this an SMA connection with an SMA male to male 90 degree transition connector was implemented seen in the middle of Figure 5-2. This is also a benefit in terms of the comparison of different technologies, as the electrical loading effect of the probes can easily be included or excluded. The downside is packaging losses and integration/packaging challenges that may be more problematic in one technology over another are not given the opportunity of exploration. As the board used is FR4, there is no predictive behavior in regards to the board materials consistent dielectric constant. For this reason it was decided to include a reference transmission line on the same board cut out so that transmission line behavior 78

92 for the board specified could be determined. This reference line is clearly seen at the top of the board image in Figure 5-2. A bill of materials used in the filter portion of the board is listed in Table 5-1. The transmission line section only used two right angle SMA jack connectors. Table 5-1 Filter Board Parts List Quantity Part Number Vendor Description TE Connectivity Right Angle SMA Jack Connector TE Connectivity Straight SMA Jack Connector Molex Right Angle BNC Jack Connector 2 550L104KTT American Technical 0.1 F Capacitor Ceramics (ATC) 1 MLK1005S1N0S TDK 56 nh Inductor 5.2 Non-Linear Varactor Modeling Implementing the Verilog-A models designed in the previous chapter, the expected filter performance was simulated using Agilent Genesys software. An image of the filter model used is seen in Figure 5-4.The resulting simulated response is shown in Figure 5-5 and Figure 5-6. As expected the filters should behave similarly due to their demonstrated similar tunability and bias voltage needs. 79

93 S21 (db) Figure 5-4 Genesys Model of Circuit Board Filter with Verilog A Varactors Simulated Filter (BST) Frequency (MHz) V = 0 V = 1 V = 2 V = 3 V = 4 V = 5 V = 6 Figure 5-5 Simulated Circuit Board Filter Using BST Varactor Verilog-A Model 80

94 S21 (db) Simulated Filter (GaN) Frequency (MHz) V = -6 V = -5 V = -4 V = -3 V = -2 V = -1 V = 0 Figure 5-6 Simulated Circuit Board Filter Using GaN Varactor Verilog-A Model Actual measurements are shown in Figure 5-7 and Figure 5-8.Measurements were collected again using the network analyzer, probe station, and power supply equipment. The measurements are similar to the modeled results, with a few noticeable exceptions. The filter notch depth is not as deep as modeled. This is more than likely due to the simplification of the models to avoid multiple voltage dependent parameters. Second, the BST filter has a much varied filter frequency change. This is more than likely due to the inherent variations to the BST manufacturing. The GaN devices come from a foundry process, where the repetition of business has improved product quality. As the BST films are produced in a university setting, these process controls are limited. Also, as the BST film has such a high dielectric constant in a thin layer, the capacitor s capacitance function is highly dependent on layer thickness. Marginal layer variations can negatively influence model accuracy. 81

95 S21 (db) S21 (db) Measured Filter (BST) Frequency (MHz) V = 0 V = 1 V = 2 V = 3 V = 4 V = 5 V = 6 Figure 5-7 Measured Circuit Board Filter Using 1-Port BST Varactor 0 Measured Filter (GaN) Frequency (MHz) V = -6 V = -5 V = -4 V = -3 V = -2 V = -1 V = 0 Figure 5-8 Measured Circuit Board Filter Using 1-Port GaN Varactor 82

96 Table 5-2 GaN Filter Summary DC Bias Voltage Notch Point (MHz) GaN Measured GaN Modeled Table 5-3 BST Filter Summary DC Bias Voltage Notch Point (MHz) BST Measured BST Modeled Non-Linear Varactor Modeling The next test was to determine the power handling capability of the varactors. To determine this, an Agilent N9310B RF Signal Generator and Agilent N9320B Spectrum Analyzer were used in place of the network analyzer. RF sinusoids were input at 120 frequencies ranging from 25 MHz to 1 GHz. Multiple power levels of the sinusoids were input into each filter system, ranging from -10dBM to 20dBm in approximately 3dB step increments. 83

97 Pout/Pin (db) Pout/Pin (db) BST Filter Bias = 0V Frequency (MHz) 10 dbm 13 dbm 16 dbm Figure 5-9 Filter Response to Power, 1-Port BST Varactor 0V Bias BST Filter Bias = 1V Frequency (MHz) 10 dbm 13 dbm 16 dbm Figure 5-10 Filter Response to Power, 1-Port BST Varactor 1V Bias 84

98 Pout/Pin (db) Pout/Pin (db) GaN Filter Bias = -3 V Frequency (MHz) 10 dbm 13 dbm 16 dbm Figure 5-11 Filter Response to Power, 1-Port GaN Varactor -3V Bias GaN Filter Bias = -2.5 V Frequency (MHz) 10 dbm 13 dbm 16 dbm Figure 5-12 Filter Response to Power, 1-Port GaN Varactor -2.5V Bias 85

99 Bias Current (A) Figure 5-9, Figure 5-10, Figure 5-11, Figure 5-12 show similar curves to those shown previously from the network analyzer measurements. These plots are frequency swept results of a maximum hold on the spectrum analyzer while the signal generator swept the multiple frequencies. For each output result on the spectrum analyzer, the measured value was offset by the referenced signal generator supplied power. The resulting curve is a Pout/Pin curve, essentially the same as S 21 shown previously. The important thing to look for is if there is any noticeable change in the filter characteristics under different signal powers. As shown the responses are all similar to one another, leading one to believe there is little impact on signal power. Finally the bias supply current to the filter was compared between the two technologies. As is seen in Figure 5-13, the currents are almost identical. This figure also shows that the varactor supply power is very minimal, which is good when potentially operating in systems seeking to maximize efficiency. 1.00E-06 Supplied Current to Bias Line 1.00E E E E-10 BST GaN 1.00E Bias Voltage Figure 5-13 Measured Current at Bias Line for both 1-Port Varactors 86

100 CHAPTER 6 CONCLUSIONS 6.1 Results of Varactor Comparison Varactor devices were successfully implemented in BST as well as GaN technologies. The devices were modeled, and included into a higher level of complexity circuit by means of a circuit board implemented filter. Barium strontium titanate varactors outperformed GaN varactors in most comparative criteria. The devices were significantly smaller while having similar capacitance and operated under the same bias voltage range. The quality factor of the devices was marginally worse than GaN at 0V bias, but better at both 1GHz and 10GHz at higher bias voltages. Gallium nitride varactors based on HEMT layouts behaved marginally well, and need to be further analyzed before being fully implemented and adopted by engineers. A significant advantage for GaN varactors is the inherent compatibility with high power transistors. Based on testing, these devices were also able to withstand at least 20dBm of signal power at all of the bias voltages tested. Another benefit is the demonstration that a simple nonlinear varactor model is very similar to those already being implemented for the HEMTs in amplifier situations. 6.2 Future Opportunities Future studies will need to be performed on the physical length, width and area properties of the GaN devices so that engineers can properly design a varactor that 87

101 meets a desired capacitance value. Previous papers have achieved similar levels of success in terms of capacitance/voltage curves and quality factor; however, these were done with highly focused processes that may have a high barrier of entry in the integration of more complex systems. Achieving a higher level integration of GaN varactors with power amplifier and/or filter circuits is a large opportunity. The opportunity to integrate tunable matching and filtering on wafer is a large opportunity in the reconfigurable electronics arena, particularly in the realization of software defined radio systems. Achieving a completely integrated solution can be ideal as the inclusion of bonding interconnecting between various technologies is quality factor limiting. Similar to the work begun in [68], processing techniques that merge the opportunities of GaN IC design in terms of power handling along with the high and tunable dielectric constant of BST is an interesting growth potential. The work presented in [78], demonstrates knowledge of implementing BST varactors on top of ohmic stacks and contacts necessary in the generation of GaN integrated circuits and MMICs. Another large opportunity exists in the further development of three dimensional BST varactor technologies. As shown in this paper BST has excellent tuning and size properties. The fabrication of multiple layered structures should be realizable if the variations and difficulties of lithographic alignment can be better understood and fed into the necessary adjustments to the fabrication procedure. As the knowledge and expertise of the properties of BST have matured, it is quite achievable to combine BST processing with III/V fabrication. This opportunity to combine a high dielectric constant, highly tunable material into a system with high power handling capability can lead to highly noteworthy radio electronic performance. The expertise learned in the fabrication processes in various technologies, particularly those involving three dimensional processing will prove invaluable as the 88

102 demands of the market for smaller and more capable circuits will drive the industry into a denser and more three dimensional intensive architecture. One example of leveraging these processing lessons to other materials has been recently presented [79]. The conference paper, illustrates how similar advanced processing techniques are needed in applications that use vanadium dioxide, a material with a temperature dependent transition between an insulator to a conductor. In the development of integrating heater and electrical connection elements, knowledge of layer stacking and tolerances will be critical to the proper integration of switchable electronics. 6.3 Summary The preceding research makes important advances to the electrical engineering field in the design and analysis of varactors on gallium nitride substrates as well as those that utilize barium strontium titanate thin films. One significant contribution from this research is the generation of a varactor small signal model that when implemented in Verilog-A language can predict the nonlinear behavior of the varactor. The schematic representation of the model is composed of only four passive circuit elements with dependencies on the applied bias voltage. The simple underlying model correctly predicts performance of both GaN and BST varactors as demonstrated in a simple filter circuit. In an effort to meet current market demands for smaller and tunable electronic components a novel BST thin film geometry is presented. The structure is designed with new manufacturing processes that stretch varactors vertically by use of silicon etching and gold electroplating. The processing techniques used in this vertically stretching of devices are improved after analyzing variations in fabricated wafers. This analysis will be useful for future designs of both components and line interconnects in integrated circuits. 89

103 Finally, gallium nitride based varactors have been designed, built, and analyzed. This research explores the correlation of these varactors to the underlying transistor intrinsic performance. The strong correlation between the intrinsic capacitance curves of the transistor and the varactors, regardless of 1-Port or 2-Port topologies was observed. The significant contribution is that by using transistor based varactors, the varactor performance can be predicted if nonlinear transistor models already exist. In conclusion, varactor components built with either barium strontium titanate or gallium nitride technologies are highly useful in modern radio electronic circuits. Advancements in material processing and design techniques, such as those presented here will continue to complement the market needs for small high capability components in the generation of small high functioning electronic systems. 90

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110 APPENDIX A: VERILOG CODE The following are the two Verilog files generated to model the behavior of the barium strontium titanate and gallium nitride varactors. module BSTVaractor(Port_1, Port_2); inout Port_1, Port_2; electrical Port_1, Port_2, rsp, rsn; parameter real l = 1n from [0:inf); // nominal series inductance [H] parameter real rp = 10M from [0:inf); // parallel resistor inductance [Ohm] parameter real cscale = 1G from [0:inf); //offset to change capacitance to pf real rs; // ESR [Ohm] real is, vrc, vrs, vc, q; analog begin is = I(Port_1,Port_2); V(rsn,Port_2) <+ ddt(l*is); vrc = V(Port_1,Port_2)-V(rsn,Port_2); rs=0.1067*vrc*vrc ; vrs = is*rs; vc = vrc-vrs; q=(( e-6*vc*vc*vc*vc*vc*vc*vc)+(2.14e-4*vc*vc*vc*vc*vc)+(- 1.28e-2*vc*vc*vc)+(0.831*vc))/cscale; I(Port_1,Port_2) <+ ddt(q) + vc/rp; end endmodule 97

111 module GaNVaractor(Port_1, Port_2); inout Port_1, Port_2; electrical Port_1, Port_2, rsp, rsn; parameter real c0 = 1p from (0:inf); // nominal capacitance [F] parameter real c1 = 0.5p from [0:c0); // maximum capacitance change from nominal [F] parameter real v0 = 0; // voltage for nominal capacitance [V] parameter real v1 = 1 from (0:inf); // voltage change for maximum capacitance [V] parameter real rs = 1 from (0:inf); // ESR [Ohm] parameter real l = 1n from [0:inf); // nominal series inductance [H] parameter real rp = 1M from [0:inf); // parallel resistor inductance [Ohm] real is, vrs, vc, q; analog begin is = I(Port_1,Port_2); V(rsn,Port_2) <+ ddt(l*is); vrs = is*rs; vc = V(Port_1,Port_2)-V(rsn,Port_2)-vrs; q = c0*vc + c1*v1*ln(cosh((vc-v0)/v1)); I(Port_1,Port_2) <+ ddt(q) + vc/rp; end endmodule 98

112 APPENDIX B: TECHNOLOGIES UTILIZING BST THIN FILM VARACTORS The following tables summarize state of the art device and block level applications of barium strontium titanate (BST) thin film varactors. 99

113 Work [33] [35] [36] Device Description Bandwidth Coupledline CPW filter Coupledline CPW filter Hybrid packaged liquid crystal resonator filters shorted by bonded varactor chips 3-pole (three halfwavelength) resonators with inductive impedance inverter Varactor Type Single Layer Device Single Layer Device Two finger IDC Bias (V) Center Freq No Bias (GHz) Center Freq High Bias (GHz) 30 volts volts volts volts Insertion Loss db db 4.9 to db (0 V) and 2.5 db (30 V) BST Mixture (x) Deposition Method 9% to 9.5% CCVD % to 8.7% 0.45 CCVD % to 10% 0.45 CCVD % 0.23 BST Thickness (μm) Substrate C Plane Sapphire C Plane Sapphire C Plane Sapphire 430 μm thick sapphire Table B-1 Filters 100

114 Work [37] [40] Device Description 4 resonance rings with varactors shorting ring openings 5 line combline filter 5 line combline filter Varactor Type Two finger IDC IDC capacitor IDC capacitor Bias (V) Center Freq No Bias (GHz) Center Freq High Bias (GHz) 30 volts Insertion Loss 5.7 to 3.5 db 100 volts db 100 volts db Bandwidth BST Mixture (x) Deposition Method % 0.23 graded thin film (SrTiO / Ba Sr TiO / BaTiO /Pt/ Ti/ alumina) graded thin film (SrTiO / Ba Sr TiO / BaTiO /Pt/ Ti/ alumina) chemical solution chemical solution BST Thickness (μm) Substrate 430 μm thick sapphire 250 μm alμmina 250 μm alμmina 101

115 Work [34] [38] [39] Device Description CPW Ring resonator with attached varactor chips Two-pole RF tunable active BPF 3 Stub combline bandpass filter Varactor Type 6 finger IDC width = 0.01 mm finger space = 0.01 mm finger length = 0.22 IDC width = 10 μm finger space = 10 μm finger length = 300 μm 12-finger IDC width = 5 μm finger space = 5 μm finger length = 200 μm Bias (V) Center Freq No Bias (GHz) Center Freq High Bias (GHz) 35 volts db 50 volts volts Insertion Loss to db (0 V) and 3.3 db (200 V) Bandwidth BST Mixture (x) Deposition Method 276 to 318 MHz 0.5 PLD MHz PLD MHz 0.75 RF Sputtering 0.6 BST Thickness (μm) Substrate 0.5 mm (001) MgO N Type Silicon 500 μm C plane sapphire 102

116 Work [41] Device Description Third Order LC bandpass filter Third Order LC lowpass filter Fifth Order LC lowpass filter Varactor Type Parallel Plate Parallel Plate Parallel Plate Bias (V) Center Freq No Bias (GHz) Center Freq High Bias (GHz) Insertion Loss Bandwidth BST Mixture (x) Deposition Method 6 volts db 0.7 MOCVD volts 9 volts (3dB cutoff) (3dB cutoff) (3dB cutoff) 0.8 db 0.7 MOCVD (3dB cutoff) 2 db 0.7 MOCVD 0.3 BST Thickness (μm) Substrate 500 μm silicon 500 μm silicon 500 μm silicon 103

117 Work [47] [44] [46] [42] [45] [43] Device Bias Description (V) Varactor loaded antenna used as a temperature sensor 1.35 BST membrane vibrator resonator Varactor Type Center Freq No Bias (GHz) Center Freq High Bias (GHz) Return Loss Bandwidth BST Mixture (x) Deposition Method Parallel Plate PLD 0.65 Slot Antenna db 4% Planar dielectric resonator fed by gunn diode db 0.3 BST membrane vibrator resonator 2 layer IDC Screen Printing 25 Parallel Plate PLD 0.3 Parallel Plate BST Thickness (μm) Substrate High resistivity silicon 0.63 mm Alumina High resistivity silicon db 0.6 PLD 0.25 Sapphire Table B-2 Resonators and Antennas 104

118 Work [59] [58] [61] [62] Device Bias Description (V) LH strip-line transmission line based phase shifter with varactor separation between unit cells IDC Varactor Type Long CPW transmission line 30 Operation Frequency (GHz) 7.5 GHz (best FOM) Phase Change High Bias (degrees) Insertion Loss (no bias) Insertion Loss (high bias) (111) based device: 35 (100) based device BST Mixture (x) Deposition Method BST Thickness (μm) Substrate 650 μm Al2O3 RF Sputtering 0.75 MgO CPW transmission lines periodically loaded by varactors IDC Sol-Gel 0.3 All pass LC network phase shifter 2 Finger IDC and 30 GHz 20 GHz: GHz: GHz: 6 30 GHz: 4 20 GHz: 4 30 GHz: CCVD mm C axis Sapphire 500 μm r- plane sapphire Table B-3 Phase Shifters 105

119 Work [50] [51] [57] Device Description All-pass network phase shifter using 5 element RC ladder type network Full analog reflectiontype phase shifters (RTPSs) all-pass networktype phase shifters (APPSs) CPW transmission lines periodically loaded by varactors Varactor Type Bias (V) Operation Frequency (GHz) Phase Change High Bias (degrees) Insertion Loss (no bias) Insertion Loss (high bias) BST Mixture (x) Deposition Method Parallel Plate PLD 0.4 Coplanar and nonoveralapping plates Coplanar and nonoveralapping BST Thickness (μm) Substrate 430 μm C-Plane Sapphire Screen Printing 8 Sapphire Screen Printing 8 Sapphire plates Finger IDC finger length = 60 μm width = 20 μm spacing = 20 μm PLD 0.3 MgO 106

120 Work [56] [54] [52] Device Description Active all pass phase shifter circuit implemented with discrete components Loaded CPW transmission line that includes four T-unit cells tunable by ferroelectric varactors All-pass continuous variable phase shifter. ¼ wavelength t-lines with series resonant circuits Varactor Type Bias (V) Operation Frequency (GHz) Parallel Plate Phase Change High Bias (degrees) Insertion Loss (no bias) Insertion Loss (high bias) BST Mixture (x) Parallel plate PLD Deposition Method IDC Spacing = 4 μm CCVD 0.45 BST Thickness (μm) Substrate High resistive <111> Silicon 675 μm Sapphire 107

121 Work [53] Device Bias Description (V) Straight Reflectiontype phase shifter. 3-dB coupler, a bias network, and two phasecontrollable LC terminations IDC Folded Type Reflectiontype phase shifter consists of a 3-dB coupler, a bias network, and two phasecontrollable LC terminations IDC Varactor Type Operation Frequency (GHz) Phase Change High Bias (degrees) Insertion Loss (no bias) Insertion Loss (high bias) BST Mixture (x) 1.75 GHz 0 to 125 degrees 3.5 GHz 0 to 65 degrees 1 to 3 1 to CCVD 2.25 GHz 0 to 140 degrees 4 GHz 0 to 110 degrees 1 to 3 1 to CCVD Deposition Method BST Thickness (μm) Substrate 430 μm Sapphire 430 μm Sapphire 108

122 Work [48] [55] [49] [60] Device Description CPW t-lines periodically loaded by varactors High impedance transmission line periodically loaded with varactors High impedance transmission line periodically loaded with capacitors CPW transmission lines periodically loaded by varactors Varactor Type Bias (V) Operation Frequency (GHz) Phase Change High Bias (degrees) Insertion Loss (no bias) Insertion Loss (high bias) Parallel Plate IDC finger width = 2 μm finger spacing = 1 μm Parallel Plate BST Mixture (x) Deposition Method BST Thickness (μm) Substrate RF Sputtering 0.28 Sapphire RF Sputtering 0.1 RF Sputtering finger IDC Length = 30 μm separation = 0.75 to 2 μm Sol-Gel 0.3 C axis Sapphire High resistive Silicon C axis Sapphire 109

123 Work [65] Device Description Wilkinson Power divider implemented on a Rogers RO3010 substrate loaded with flip-chp BSTvaractors Branch line coupler implemented on a Rogers RO3010 substrate loaded with flip-chip BSTvaractors Varactor Type Parallel Plate 15 Parallel Plate 15 Bias Voltage Bias Description Return loss resonance tunes from 1.7 to 2.1 GHz Output is -3.6 to -4.2 db (ideal 3dB) Return loss at least -10dB Tunes from 1.8 to 2.3 GHz Insertion loss is 5 db to 5.7dB (ideal 3dB) Phase is 85 to 95 degrees between two output ports BST Mixture (x) Deposition Method BST Thickness (μm) Substrate Metal Stack Below BST Metal Stack Above BST ceramic alumina Al2O3 Pt Pt/Al ceramic alumina Al2O3 Pt Pt/Al Table B-4 Hybrid & Active Circuits 110

124 Work [66] [64] Device Description CPW based low-pass type output matching network. Hybrid packaged for GSM frequencies (824 to 960 MHz) and DCS/PCS 30 LC tank differential pair oscillator made on highfrequency, printed circuit prototype bread board hybrid packaged Parallel with varactor Plate 5 Varactor Type Bias Voltage Bias Description Impedance changed from j1 87 to j0.02 for GSM operation Impedance change from j0.06 to j0.97 for DCS/PCS operation BST Mixture (x) tuning range from 205 MHz to MHz power dissipation of 5.1 mw phase noise is 90 dbc/hz at 100 khz and 140 dbc/hz at 1 MHz offset 0.5 Deposition Method BST Thickness (μm) Substrate RF Sputtering 100 nm Quartz Metal Stack Below BST Ti (20 nm)/ Pt (200 nm) Metal Stack Above BST Pt (200 nm) 111

125 Work [63] [68] Device Description A microstrip based negative resistance circuit is glued and bonded to BST varactor Varactor Bias Type Voltage 12 finger IDC width = 5 μm length = 200 μm spacing = 5 μm 30 Circuit integrating HEMT transistors and BST on a wafer 20 Bias Description BST Mixtur e (x) Deposition Method BST Thickness (μm) Substrate Peak Q shift from 23.8 GHz to 25.2 GHz MgO Capacitance density at 0 V bias is Capacitance density at no bias is 14.3 ff/(square μm) Tunability is 3.3:1 with a 20 V bias RF Sputter 300 nm Fedoped GaN base layer 29 nm Al0.35G a0.65n barrier layer Metal Stack Below BST Metal Stack Above BST Ag (300 nm) Pt (300 nm) Pt/Au 112

126 Work [67] Device Description MEMS switch, which when closed creates BST parallel plate capacitor Varactor Type Bias Voltage Parallel Plate 5 BST Mixture (x) Bias Description MEMS open capacitance is 10 ff When closed, ~45V bias creates 100 μm x 200 μm parallel plate capacitor BST bias changes capacitance from 130 to 71.2 pf 0.45 CCVD Deposition Method BST Thickness (μm) Substrate Metal Stack Below BST Ti (20 nm)/p t(100 nm) Metal Stack Above BST Ti (20 nm)/au (300 nm)/ti (20 nm) 113