STABILIZATION AND ROBUSTIFICATION OF NEGATIVE OUTPUT SUPERLIFT LUO CONVERTER USING SLIDING MODE CONTROL APPROACH

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1 International Journal of Advances Engeerg & Technology, May. IJAET ISSN: -96 STABIIZATION AND ROBUSTIFICATION OF NEGATIE OUTPUT SUPERIFT UO CONERTER USING SIDING MODE CONTRO APPROACH. Chamundeeswari, R. Seyezhai, A. Arul Rob Assoc. Professor, Department of EEE, St. Joseph s College of Engeerg, Chennai, India Assoc. Professor, Department of EEE, SSN College of Engeerg, Chennai, India. PG. student, St.Joseph s College of Engeerg, Chennai,-9, India ABSTRACT This paper depicts the design and implementation of non-lear control approach called slidg mode control for Negative Output Elementary Superlift uo converter (NOESC).DC-DC converters fds its applications majorly all power electronic dustries nowadays. In order to provide a good regulation of output these converters it is mandatory to make them operate the closed loop mode usg various controllers like P, PI and PID controller. But the usage of these controllers has resulted an unsatisfactory regulation of the output voltage under large variation of system parameters. To overcome this, an approach called slidg mode control (SMC) technique is proposed and discussed here. The NOESC converts the positive put voltage to a negative output voltage geometric progression. The design of the controller is done with the tung of its ga parameter and implemented the circuit by usg the state space model of the converter. The ma advantage of SMC over conventional control is its stability and good response variations with respect to the put. Simulation results are presented usg PSPICE and MATAB to validate the theoretical design and to illustrate the strength of the proposed controller. KEYWORDS: DC-DC converter, Negative output Elementary superlift uo converter, Slidg mode controller (SMC) I. INTRODUCTION oltage lift technique has been successfully employed design of DC/DC converters, e.g., uoconverters. However, the output voltage creases arithmetic progression. Super lift technique this system implements the output voltage creasg geometric progression. It effectively enhances the voltage transfer ga power-law. The slidg mode control for the above system is implemented to achieve a closed loop control. The NOESC performs the voltage conversion from positive source voltage to negative load voltage. The SMC is designed by usg state-space average modelg of NOESC. Conventionally, proportional-tegral-derivative (PID) and (PI) controllers are used for the control of various types of DC-DC power converters which has provided an unsatisfactory regulation of the output voltage a closed loop control. The technique of troducg slidg mode control has resulted good regulation of the output voltage. The followg sections will reveal the entire modelg and design of the controller for the converter. The modes of operation of the converter has been explaed section II followed by the state space model section III. The section I and has been dealt with design of slidg mode controller and the calculation of control and tung parameters. Simulation results of the converter and the gate pulse generated are depicted section I and ended with a conclusion section II. 58 ol., Issue, pp

2 International Journal of Advances Engeerg & Technology, May. IJAET ISSN: -96 II. OPERATION OF THE CONERTER a. Operation of NOESC The NOESC is a new series of DC-DC converters 5 possessg high-voltage transfer ga, high power density, high efficiency, reduced ripple voltage and current. Fig. (Ref.7) shows the elementary circuit of NOESC.It consists of DC supply voltage, capacitors C and C, ductor, power switch S (n-channel MOSFET), freewheelg diodes D and D and the load resistance R.The workg prciple is explaed with the switch 'S on and off as two modes of operation as shown Figs.&. (Ref.7)Durg the on period of the switch S i.e. DT terval, voltage across capacitor C is charged to. Current flowg through ductor creases with slope / and decreases with slope ( o )/ durg switch-off (-D) T. Fig : Circuit diagram of NOESC Fig : Mode - circuit diagram of NOESC Fig : Mode - circuit diagram of NOESC. Durg mode-, the switch is closed and the supply flows through the ductor and C charges durg this time the capacitor C produces a load voltage. Durg mode-, the switch is open and the ductor and capacitor C discharges through the load which gives the boosted output o. b. Energy equations durg ON and OFF state Considerg the modes of operation as by above figures, Energy durg ON state is, Energy durg OFF state is, W I T () on W Therefore output voltage is given by, off I T off on () 59 ol., Issue, pp

3 International Journal of Advances Engeerg & Technology, May. IJAET ISSN: -96 The variation ratio of ductor current i l is, The ripple voltage of output voltage o is, Therefore, the variation ratio of output voltage o is, The variation the ductor current is given by, o i DT ( D ) T The voltage transfer ga is, G D o D D D c. SMC ariable structure system (SS) Nowadays, all the modern power electronics systems need high quality, simple, lightweight, cheap, highly reliable and efficient power supplies. To regulate the output voltage of DC-DC converters 6 irrespective of load variations and le disturbances, it is necessary to operate the converters closed loop mode. In recent days, the use of slidg mode control (SMC) 8 method variable structure system (SS) makes the system very robust to parameter variations and external variations. ariable structure systems are characterized by a discontuous control action which changes structure on reachg a set of switchg surfaces. Here the switchg commutations of a static converter constitute the SS. III. ξ MODEING OF NOESC The state-space modelg of the equivalent circuit of NOESC with state variables i, C and C are given below. Accordg to the switchg condition (Y), the,, are expressed for the ON condition and the status of the switch is determed as, di dt o D I ( D) T ( D) C fc R / [{ S OFF} ] [{ S ON} ] Y Y ξ i R C ( D ) RfC I C d C dt / D( D) T i I G dc dt D( D) R f 5 ol., Issue, pp () (4) (5) (6) (7) (8) (9) ()

4 International Journal of Advances Engeerg & Technology, May. IJAET ISSN: -96 In this, the slidg surface has to be chosen, with the state variables space, where control functions are discontuous. The slidg condition 9 occurs when the system state does not leave the switchg surface and the system dynamics can be described by a reduced order system. In general, two dynamic conditions can be distguished and that is derived by assumg the ideal hypothesis of fite commutation frequency of electronic switches which satisfies the above switchg condition given as Y. Thus the switch off state is taken and the equations are described with respect to the switch off condition as considered mode. Accordg to the switchg condition (Y) of circuit, i.e. OFF condition, the,, are expressed as, i C di i C dt d C dt d C dt () Therefore, di d dt C C d dt C dt C C C + i i C + + Y+ C R C C i RC C () Where, R is ternal resistance of the source. State-space modelg of the circuit is given by, Where, X & & x are the vectors of the state variables and their derivatives respectively and C is the disturbance matrix and ω is the put. I. X & Ax + By + Cw SMC DESIGN AS ARIABE STRUCTURE CONTROER (SC) a. Controller design In slidg mode theory, the SMC requires sensg of all state variables of NOESC and generation of suitable references for each of them as shown fig.4 The prciple of the SMC is to make the capacitors voltage c and c of NOESC follow as faithfully as possible the capacitor voltage references. However, the ductor current reference is difficult to evaluate sce that generally depends on load power demand, supply voltage, and load voltage. To overcome this problem, the state variable error for the ductor current can be obtaed from feedback variable il by means of a high-pass filter the assumption that their low-frequency component is automatically adapted to actual converter operation. The high-pass filter must be suitably lower than the switchg frequency to pass the ripple at the switchg frequency, but high enough to allow a fast converter response. When good output voltage regulation of NOESC is required, a slidg surface equation the state space can be expressed by a lear combation of state-variable errors, can be given by S ( i K ε, C, C ) Kε + Kε + () 5 ol., Issue, pp

5 International Journal of Advances Engeerg & Technology, May. IJAET ISSN: -96 Where coefficients, and are proper gas, is the feedback current error, is the feedback voltage error and is the feedback voltage error. ε i i ref ε ε C C ref C C ref (4) By substitutg (4) () we get, S ( i, C, C ) K( i i ref ) + K ( c cref ) + K ( c c ref ) The signal S ( i, C, C ) obtaed by () and applied to a simple circuit (hysteresis comparator), can generate the pulses to supply the power semiconductor drives. Status of the switch y is controlled by hysteresis block H, which matas the variables near zero. (5) b. Control parameter selection Fig.4: Slidg mode controller of NOESC Once the negative output elementary super lift uo converter parameters are selected, ductance are designed from specified put and output current ripples, capacitors and are designed so as to limit the output voltage ripple the case of fast and large load variations and maximum switchg frequency is selected from the NOESC ratgs and switch type. Accordg to the variable structure system theory, the converter equations must be written the followg form, X & Ax + By + Cw (6) Where X represents the vector of state-variables errors, given by X & v * [ i ] T ref, Cref, C ref Where, * is the vector of references. By substitutg (7) (), we obta, * D A + Cw (7) (8) D C C i RC ref Cref Cref + 5 ol., Issue, pp (9)

6 International Journal of Advances Engeerg & Technology, May. IJAET ISSN: -96 Therefore, C ref C ref i ref D C i ref C ref C RC () Substitutg (7) (5), the slidg function can be rewritten the form, T S( x) K x + K x + K x K x () Where, K T K + K + and [ ] K [ x + x x ] T x + The existence condition of the slidg mode requires that all state trajectories near the surface be directed toward the slidg plane. It is necessary and sufficient that S ( X ) <, if S ( X ) >, if S ( X ) > S ( X ) < () slidg mode control is obtaed by means of the followg feedback control strategy, which relates to the status of the switch with the value of S (x), for S ( x) > Y (), for S ( x) < The existence condition (8) can be expressed the form, T T S( x) K Ax + K D <, S( x) > T T T S( x) K Ax+ K B+ K D >, S( x) < (4) (5) From a simulation pot of view, assumg that error variables X are suitably smaller than references *, () and () can be rewritten the form K T D <, S( x) > T T K B+ K D >, S( x) < (6) (7) By substitutg the matrices B and D (6) and (7), we obta K Ki ref K [ c ref + c ref ] + + [ Ri ref c ref] < C C R K K c ref [ R i ref ] > C R RC The existence condition is satisfied if the equalities (8) and (9) are true. f s t + t (8) (9) () 5 ol., Issue, pp

7 International Journal of Advances Engeerg & Technology, May. IJAET ISSN: -96 Where the conduction is time of the switch S and is the off time of the switch S. The conduction time, is derived from (9) and it is given by, t K C R [ δ K C R ] () RC ref () Where,δ is an arbitrary small positive quantity and time, is derived from (9), and it is given by δ is the amount of hysteresis S(X).The off t K [ Cref + Cref δ K i ] + C ref [ Ri ] () K () + C R ref Cref The maximum value of switchg frequency is obtaed by f K δ cref max + c ref s max max (). DESIGN OF CIRCUIT COMPONENTS AND CONTRO PARAMETERS a. Duty cycle The duty cycle D is defed by the ratio between the conduction time of the switch S and the switch period time, as represented by, t D (4) t + t Considerg the SMC, an stantaneous control, the ratio between the output and the put voltages must satisfy the fundamental relation at any workg condition. D (5) b. Inductor current The high-frequency maximum ductor current ripple is obtaed from Fig.5 (b) and given by (8). i t C.Capacitor voltage (6) The controller operates over the status of the switch to make the voltage (t) to follow the reference. As a consequence, on the capacitor (t), a high C c t (7) RC Frequency voltage ripple (which is a characteristics function switchg frequency) is imposed. The capacitor voltage ripple is given by (5). D.To fd the value of 54 ol., Issue, pp

8 International Journal of Advances Engeerg & Technology, May. IJAET ISSN: -96 From (5) and a simulation pot of view, the output voltage is chosen to produce a variation of the duty cycle close to.66. e. To fd / Substitutg, and.9 () we get / f. To fd / and / From (8) and (9) and takg.5a,one obtas 8 < / < 484 and 8 < / < 484. g. Calculation of The maximum ductor current ripple is chosen to be equal to 5 % of maximum ductor current, and uh which is obtaed from (6). h. Calculation of, and values of the coefficients, and The maximum capacitor ripples voltage and is chosen to be equal to.5 % maximum capacitors voltage, and uf which is obtaed from (7). (.667). Similarly the.7 is computed usg the ratio / and / and the,. I. SIMUATION RESUTS a. Simulation of NOESC without SMC controller Simulation is carried out for the negative output elementary super-lift uo converter with the values,, f KHz, uh, C, CuF, R5Ω, D.667. The simulation is done PSPICE with the calculated values and the diagram is given below Fig.5:Simulation Diagram of NOESC From the simulation, an output voltage of -6 is obtaed for the NOESC which is shown below. This shows the crease of the output voltage geometric progression. With a time period of us the output oltage is depicted. 55 ol., Issue, pp

9 International Journal of Advances Engeerg & Technology, May. IJAET ISSN: -96. Fig 6: Output voltage Wave Form of NOESC without SMC controller b. Simulation of NOESC with SMC controller The simulation study of NOESC with SMC is presented this section. The validation of the system performance is done for five regions viz. transient region, le variations, load variations, steady state region and also components variations. Simulations have been performed on negative output elementary super lift luo converter circuit with parameters calculated. Fig:7 Simulation Diagram of NOESC with SMC controller The static and dynamic performances of SMC for NOESC are evaluated Matlab/Simulk. The Matlab/Simulk simulation of system with control method is depicted Fig 7. The detailed operation of NOESC with SMC is discussed. The output voltage is obtaed to be -4.7 where the geometric progression of put voltage () is shown. It can be observed that put current of NOESC goes up to.5a and output voltage of NOESC travels up to -4.7 without overshoot. 56 ol., Issue, pp

10 International Journal of Advances Engeerg & Technology, May. IJAET ISSN: -96 Fig.8: Output oltage waveform of NOESC with SMC controller c. Gate pulse of the switch given from SMC output The gate pulse of the switch S (MOSFET) is given with a duty ratio of.66 i.e. 66% of the total period. The adapted value of duty ratio is selected to be.66 for an enhanced output voltage. Fig.9: Gate Pulse of the Switch from SMC output d. current through the ductor The ductor current waveform is shown below diagram which has i.a. The ductor energized when the supply is given with switch turned ON and durg OFF condition the current discharges through load. Fig. current through the ductor 57 ol., Issue, pp

11 International Journal of Advances Engeerg & Technology, May. IJAET ISSN: -96 e. Energizg pulse of the Relay The relay is energized based on the summer output. Also a high pass filter is added to the current feedback, which are given to the ga amplifier and the relay is energized based on the range of value taken. Fig.: Relay Energizg Pulse Thus the relay output is considered as put to the switch and a closed loop will be achieved. Based on the variation parameter of load, put voltage, and change component values the ga parameter is chosen and converter closed loop control is executed. II. CONCUSION The design and analysis of Slidg mode control for NOESC has been successfully presented this paper. This control technique will stabilize the output for any change put voltage thereby boostg the output geometric progression. The output capacitor voltage and the ductor current of the converters are taken as the parameters and compared with the reference thus producg the error signal.thus the controller modifies and a proper control action is achieved with the correct matenance of the duty ratio of the pulse applied to the switch. Thus the selection of the proper control parameters proved to provide excellent dynamic, static and transient response which is proved by implementg SMC usg simulation softwares. REFERENCES []. S. Arulselvi, G. Uma and M. Chidambaram, Design of PID controller for boost converter with RHS zero", august 4. [].. Guo, J.Y. Hung and R. M. Nelms, "Design and implementation of a digital PID controller for a buck converter", July/August. []. H. Mgzhi and X.Jianpg, "Nonlear PID Digital Controlled Buck Converters", March 7. [4]. K. Ramash Kumar, S. Jeevananthan, "PI Control for Positive Output Elementary Super ift uo Converter", Summer. [5]. AJ. Foreyth and S. Mollov, "Modelg and control of Dc-Dc converters", IEEE Power Engeerg Journal. [6]. Mahdavi, A Emadi, H.A. Toliyat, "Application of State Space Averagg Method to Slidg Mode Control of PWM DCDC Converters," IEEE Industry Applications Society Annual Meetg New Orleans, October 997. [7]. Y. B. Shtessel, A S.. Zober,. A. Shkolnikov, "Slidg mode control of boost and buck-boost power converters usg the dynamic slidg manifold," International Journal of Robust and Nonlear Control, July. [8]. K. Ramash Kumar, S. Jeevananthan, "Hysteresis Modulation Based Slidg Mode Control for Positive Output Elementary Super ift uo Converter", International Journal of Electrical and Electronics Engeerg, December ol., Issue, pp

12 International Journal of Advances Engeerg & Technology, May. IJAET ISSN: -96 [9]. P.F.Donoso-Garcia, P.C.Cortizo, B.R.de Menezes, M.A.Severo Mendes, Slidg mode control for current distribution parallel-connected DC-DC converters. IEE Proc-Electr, Power ol.45,no.4,july998. []. Pawan Gupta, Amit patra, Hybrid Slidg mode control of DC-DC converters TENCON. []. J.Matas,.G.deicuna, O.opez, M.opez and M.Castilla Discrete slidg mode control of a boost converter for output voltage trackg power electronics and variable speed drives,sep, conference publication No.475 IEE. []. F.Ciccarelli,D.auria Slidg mode control of Bidirectional dc-dc converter for supercapacitor Energy storage applications SPEEDAM /IEEE. []. Emil A.Jimenez Brea, Eduardo I. Ortiz-Rivera,Andres Salazar-las,Jesus Gonzalez-lorente Simple photovoltaic solar cell dynamic slidg mode controlled maximum power pot tracker for battery chargg applications. IEEE. [4]. A.N.K.Nasir, R.M.T.Raja Ismail, M.A.Ahamed, Performance comparison between slidg mode control(smc) and PD-PID controllers for a Non-lear verted pendulum system,world academy of Science,Engeerg and technology 7. [5]. Mart Pavlovsky, Yukori Tsuruta, Atsuo Kawamura, Recent improvements of Efficiency and power density of DC-DC converters for automotive applications - International power conference. [6]. K. Ramash kumar, Dr.S.Jeevanathan Design of slidg mode control for negative output elementary superlift luo converter operated contuous conduction mode IEEE. [7]. Fang l luo Negative output superlift converters IEEE transactions on power electronics, September. [8]. Jhui zhang.robust Adaptive Slidg-Mode Control for Fuzzy Systems With Mismatched Uncertaties IEEE transactions. [9]. Wallace M.Bessa, Max.S.Dutra, Edw kreuzer An adaptive fuzzy slidg mode controller for remotely operated underwater vehicles Robotics and autonomous system,jan. []. G.shashikala. chandralekha, C.shashikala High power luo converter for standalone photovoltaic system IJAEST. Author s profile.chamundeeswari was born Chennai, India on December 5,979.She received the B.E degree Instrumentation and control Engeerg from Sethu stitute of technology, Madurai and M.E degree from college of Engeerg,Gudy,Chennai,India 6.Currently she is pursug Ph.D the field of power electronics at Anna university of technology,chennai,india.her field of terest cludes design of non-lear controllers for converters, modelg of converters, circuit analysis, digital controller design and development of algorithms for control. She has a teachg experience of years Engeerg colleges.currently,she is workg as a Associate professor St.Joseph s college of Engeerg,Chennai,Tamilnadu,India. R. Seyezhai obtaed her B.E. Electronics & Communication Engeerg) from Nooru Islam College of Engeerg, Nagercoil 996 and her M.E Power Electronics & Drives from Shanmugha College of Engeerg, Thanjavur 998 and PhD from Anna University, Chennai. She has been workg the teachg field for about Years. She has published several papers International Journals and International Conferences the area of Power Electronics & Drives. Her areas of terest clude SiC Power Devices, Multilevel Inverters, Modelg of fuel cells, Design of Interleaved Boost Converter, Multiport DC-DC Converter and control techniques for DC-DC Converter. 59 ol., Issue, pp