Design of an Embedded System for Early Detection of Earthquake

Transcription

1 1 Design of an Embedded System for Early Detection of Earthquake Rakesh Tirupathi, Department of ECE, KL University, Green fields, Guntur, Andhra Pradesh, India ABSTRACT This paper presents an efficient design and implementation of a low power Sigma Delta digital decimation filter for the purpose of efficient earthquake early detection and to initiate automatic response systems to reduce the chance of human injury and damage to property. In this project, I targeted embedded system to implement in Altera Cyclone II EP2C20F484C7 and Xilinx Spartan 3e with sample rate from 4000 SPS to 1 SPS. digitizing the signal. Among the ADC s we prefer Δ modulator because it is can digitize the low frequency signals effectively.here I considered the sample rate of the modulator is of 512 kilo samples per second. General block diagram for processing seismic signals is [2] Alarm Microcontroller Keywords Seismic sensor, Primary wave, Secondary wave, Sigma Delta ADC, Field Programmable Gate Array(FPGA), Cascaded Integrator Comb filter, Finite Impulse Response filter. Seismic Sensor Differential Amplifier Δ Analog to Digital Modulator Decimation Filter I. INTRODUCTION Communication Interface Saving life and property loss caused by Earthquake is one of the most challenging tasks. However, due to the capturing time limit of the seismic signals we need a system to process them as early as possible. Earthquake early warning system enables us by Monitoring seismic signals 24x7 generated by seismic sensor. Minimizing the power dissipation and time delays can be achieved by proper design. Among the seismic waves P (Primary) waves are first generated waves, after that S (Secondary) waves, R (Rayleigh) waves and L (Love) Waves. The frequencies generated by these elastic waves (1) Table 1.Frequencies of Seismic waves Frequency(Hz) Type of measurements Earth tides Earth free oscillations, earthquake Surface waves, earthquakes Surface waves, P and S waves, M> P and S waves, earthquake M> P and S waves, earthquake M<2 The signal captured by the seismic sensor has less amplitude and less frequency. The amplitude is in the range of millivolts and the frequency is of below 100 Hz. To process this signal we need differential amplifier stage to amplify the amplitude and sigma delta modulator for Seismic Sensor Fig 1.General System Block Diagram Differential Amplifier Δ Analog to Digital Modulator Fig 2. Modified System block diagram II. DIGITAL DECIMATION FILTER Alarm Decimation Filter in FPGA Communication Interface Decimation is the process of reducing the number of samples in an oversampled Discrete-Time (DT) signal such as the output of an oversampled Δ modulator [3]. Decimation lessens the computational load of the following processing chain by reducing the number of samples to be processed as well as the processing rate, making the hardware that does the downstream processing simpler, hence resulting in reduced complexity and power requirements [4].

2 2 Δ Modulator Output Fig 3. Decimation Filer blocks CIC compensation filter is also a FIR Filter used to reduce the non linear nature of the CIC filter to make whole filter as a linear filter. III. 512 KSPS CIC Filter Decimation Filter CIC FILTER INNER BLOCKS CIC filter is also known as SINC Filter. To get different output rates at the output we use different stages in SINC filter. CIC Filter CIC Compensation Filter 4 FIR Filter 2 Output rate 4000 SPS to 1 SPS decimation 4 and 2 respectively, so it is of decimation 8(from 4*2). Decimation filter total decimation factor is of 2048(from 256*8). So /2048 is equal to 250 SPS. In this way we select different CIC filter stages to get desired output word rate. Table 2.Selection of SINC Filter stages Select SINC SINC SINC FIR Total M O/P SPS bits Filter SINC 1 SINC 2 SINC 3 V. CIC FILTER Fig 4.CIC Filter inner Blocks IV. DIFFERENT STAGES IN CIC FILTER Fig 5 shows the CIC filter stages and table 2 shows the selection of stages to get proper output sample rates because SINC filter or CIC filter main aim is to decimate the high sample frequency input to low sample frequency output. Fig 5.SINC Filter Stages For example if we want to get 250 SPS output rate we have to select SINC1 decimation by 8, SINC2 (Stages1, 2, 3, 4) decimation by 16(from 2*2*2*2), SINC3 stage 7 decimation by 2, so CIC filter total decimation is 256(from 8*16*2). CIC compensation filter and FIR filter is of It is very efficient to use a Cascaded Integrated Comb filter (CIC) for the first stage[5].such CIC filter can be easily implemented in hardware, requiring no multiplication. Furthermore, it can be used to decimate the data by large factor, allowing easier implementation shown in Fig 4. Multipliers represent most of the hardware used to implement a filter as a result; multipliers contribute to most of the power dissipated in a filter. The comb filters do not require multipliers; therefore, they have been cascaded in the beginning of the Comb-FIR chain. Comb filters have a drawback of poor stop band attenuation [6]. RRRR 1 HH(ZZ) = HH NN II (ZZ)HH NN CC (ZZ) = (1 ZZ RRRR ) NN (1 ZZ 1 = ZZ KK ) NN Where I: Integrator C: Comb R: Decimation factor M: Number of Samples for stage N: Number of stages in filter KK=0 This equation shows that even though a CIC filter has integrators in it, which by themselves have an infinite impulse response and CIC filter is equal to N FIR filters, each having a rectangular impulse response. NN

3 3 A. Bit Growth For CIC decimator, the gain G at the output of the final comb section is GG = (RRRR) NN Assuming two's complement arithmetic, we can use this result to calculate the number of bits required for the last comb due to bit growth. If Bin is the number of input bits, then the number of output bits, Bout, is VI. BB oooooo = [NN log 2 RRRR + BB iiii ] CIC FILTER DESCRIPTION Fig.4 shows the basic structure of the CIC decimation filter. The integrator section of CIC filters consists of N ideal digital integrator stages same number of comb stages. It must be stressed that each integrator has a unity feedback coefficient, for CIC decimators this results in register overflow in all integrator stages. This is of no consequence if the following two conditions are met. 1) The filter is implemented with two s complement arithmetic or other number system which allows wraparound between the most positive and most negative numbers. 2) The range of the number system is equal to or exceeds the maximum magnitude expected at the output of the composite filter. For CIC interpolators, the data are preconditioned by the comb section so that overflow will not occur in the integrator stages. The economics of CIC filters derive from the following sources: 1) no multipliers are required; 2) no storage is required for filter coefficients; 3) intermediate storage is reduced by integrating at the high sampling rate and comb filtering at the low sampling rate, compared to the equivalent implementation using cascaded uniform FIR filters; 4) the structure of CIC is very regular consisting of two basic building blocks; 5) little external control or complicated local timing is required ; 6) the same filter design can easily be used for a wide range of rate change factors, R, with the addition of a scaling circuit and minimal changes to the filter timing. VII. FIR FILTER Fig 6.CIC Filter Structure A. Integrator This stage operates at the high sampling rateff ss. Each stage is implemented as a one-pole filter with a unity feedback coefficient. The system function for a single integrator is 1 HH II (ZZ) = 1 ZZ 1 B. Comb This stage operates at the low sampling rate fs/r where R is the integer rate change factor. This section consists of N comb stages with a differential delay of M samples per stage. The differential delay is a filter parameter used to control the filter s frequency response. In practice, the differential delay is usually held to M=1 or 2. The system function for a single comb stage referenced to the high sampling rate is HH CC (ZZ) = 1 ZZ RRRR It is implicit from the last form of the system function that the CIC filter is functionally equivalent to a cascade of N uniform FIR filter stages. A conventional implementation consists of a cascade of N stages each requiring RM storage registers and one accumulator. Taking advantage of the rate change factor, one of the N stages can be simplified to use only M storage registers. In some low-pass or band-selection digital filter applications, the objective is to obtain a reduced sample rate, adequate to describe the information content only within the band of interest. Under this condition, the advantage of finite impulse response (FIR) filters relative to in-finite impulse response (IIR) recursive filters has been recognized by several investigators, e.g.[7][8].two elementary properties of linear phase FIR filters contribute to this advantage. Output of the FIR filter is the convolution of the input samples to the coefficients. And the structure is like shown in Fig 5. NN 1 yy(nn) = h(kk) aa(nn kk) kk A. Direct-form FIR polyphase decimation Filter Polyphase is a way of doing sampling-rate conversion that leads to very efficient implementation. But more than that, this leads to very general viewpoints that are useful in building filter banks.

4 4 Fig bit FIR Filter decimation by 8 Output. Fig 7. Polyphase FIR decimator. Polyphase FIR decimation filter has number of phases branches equal to its decimation factor. Fig 7 is a decimation 2 filter and the h(0),h(1),h(2),...h(7) are coefficients of the filter. The operation of this filter is similar to TDM(Time division multiplexing) as the input of the filter connected to any one of the phases in the input at a time, remaining operation is same as FIR filter. VIII. SIMULATION RESULTS FOR 8 BIT INPUT AND OUTPUT IX. SIMULATION RESULTS FOR 24 BIT INPUT AND OUTPUT A. CIC Filter Fig bit CIC Filter decimation by 8 Output. B. FIR Filter Output A. CIC Filter Fig bit FIR Filter decimation 8 output. Fig 8. 8 bit CIC Filter decimation 8 Output. C. Decimation Filter for 4000 SPS(Selection bits 0111) B. FIR Filter Output Fig 9. 8 bit FIR Filter decimation by 8 Output. C. Decimation Filter for 4000 SPS(Selection bits 0111) Fig bit Decimation Filter output. D. DECIMATION FILTER FOR 1000 SPS(SELECTION BITS 0101) Fig bit FIR Filter decimation by 8 Output. D. Decimation Filter for 4000, 2000 SPS(Selection bits 0111,0110) Fig bit Decimation Filter 1000SPS output.

5 5 X. ALTERA EDA TOOL SUMMARY REPORT Table 3. ALTERA EDA 8 bit Decimation Filter Summary Family Cyclone II Device EP2C20F484C7 Timing Models Final Total logic elements 16,060/18,752(86%) Total combination functions 14,594/18,752(78%) Dedicated logic registers 3,930/18,752(86%) Total registers 3930 Total Pins 21/315(7%) Total virtual pins 0 Total memory bits 400/239,616(<1%) Embedded Multiplier 9-bit 0/52(0%) elements Total PLLs 0/4(0%) Table 4. ALTERA EDA 24 bit Decimation Filter Summary Family Cyclone IV GX Total logic elements 80,191 Total combination functions 72,757 Dedicated logic registers 10,882 Total registers Total Pins 56 Total virtual pins 0 Total memory bits 0 Embedded Multiplier 9-bit elements 720 Total GXB Receiver Channel PCS 0 Total GXB Receiver Channel PMA 0 Total GXB Transmitter Channel PCS 0 Total GXB Transmitter Channel PMA 0 Total PLLs 0 Table bit Decimation Filter Summary Device Utilization Summary Logic Utilization Used Available Utilization Number of Slices % Number of Slice flipflops % Number of 4 input % LUTs Number of Bonded % IOBs Number of MULT % 18X18SIOs Number of GCLKs % XII. CONCLUSION The implementation of an early detection of Earthquake system has been described. The embedded system having decimation filter with different output sample rates is implemented in the target device Altera Cyclone II EP2C20F484C7. An alarm is also included to set after reaching the threshold value. Fig 16. RTL View of Digital Filter. XI. XILINX ISE TOOL SUMMARY REPORT Table 5. 8 bit Decimation Filter Summary Device Utilization Summary Logic Utilization Used Available Utilization Number of Slices % Number of Slice flip-flops % Number of 4 input LUTs % Number of Bonded IOBs % Number of MULT % 18X18SIOs Number of GCLKs % Fig 17. Embedded System in ALTERA DE1 Board.

6 6 XIII. REFERENCES [1] Jens Havskov, Instrumentation in Earthquake Seismology Modern Approaches in Geophysics, University of Bergan, Norway. [2] CRD5378, Single-Channel Seismic Reference Design Cirrus logic. [3] Sevket Cetinsel, Richard C. S. Morling and Izzet Kale An FPGA Based Decimation Filter Processor Design th European Conference on Circuit Theory and Design (ECCTD). [4] Modulator Krukowski, A, Morling, R.C.S, and Kale, I., Quantization Effects in the Polyphase N- Path IIR Structure, IEEE Transactions on instrumentation and measurement, Vol. 51, No.6, December [5] E. C. Ifeachor, B. W. Jervis, Digital Signal Processing - A practical approach. [6] E. B. Hogenauer, An economical class of digital filters for decimation and interpolation, IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-29, pp , Apr [7] S. L. Freeny, R. B. Kieburtz, K. V. Mina, and, S. K. Tewksbury, Systems analysis of a TDM- FDM translator/digital A-type channel bank, IEEE Trans. Commun..Technol., vol. COM-19, pp , Dec [8] R. B. Blackman and J. W. Tukey, The Measurement of Power Spectra. New York: Dover, 1958, pp