UNIVERSITY OF NAIROBI DEPARTMENT OF ELECTRICAL &INFORMATION ENGINEERING INVERTER DRIVE CONTROL OF SYNCHRONOUS MOTORS

Transcription

1 UNIVERSITY OF NAIROBI DEPARTMENT OF ELECTRICAL &INFORMATION ENGINEERING INVERTER DRIVE CONTROL OF SYNCHRONOUS MOTORS PROJECT NO: PRJ 075 PRESENTER: MAUKA N. CHRISTINE REG.NO: F17/2147/2004 SUPERVISOR : MR.OGABA EXAMINER: DR.ABUNGU

2 OBJECTIVES The theory of operation of synchronous motors Design of inverter drive for synchronous motors To implement the designed inverter on a synchronous motor

3 SYNCHRONOUS MOTORS The motor has the following features: i. It runs either at synchronous speed or not at all, that is, while running it maintains a constant speed. The only way to change its speed is to vary is to vary its supply frequency. This is because the speed of the motor is given by Ns=120f/p ii. It is not inherently self starting. It has to run up to synchronous speed by some means before synchronization to the supply. iii. It is capable of being operated under a wide range of power factors both lagging and leading.

4 PRINCIPLE OF OPERATION The three phase alternating current set up a rotating magnetic field Speed of rotation is synchronism with supply frequency Rotor magnetic field interacts with rotating stator flux to produce rotational force

5 DRIVE SCHEMATIC Control Circuit 3 phase ac supply Diode Rectifier DC Link PWM Inverter AC Motor

6 DESIGN AND SIMULATIONS The design entailed designing sub systemssystems of the drive schematic which are: s Gate Firing Circuits Rectifier DC Link Inverter Simulations were done in Proteus Professional Ver.7.4

7 Firing circuits Were designed using the following Two 555 timer ICs 1 Johnson counter IC TTL Logic OR gates Common collector single stage transistor amplifier

8 The timers were connected as follows

9 The Johnson counter and logic circuit U3A 10 VSS 0V VSS CP0 ~CP1 MR VSS U4 VDD 10V VDD O VDD O1 2 O2 4 O3 7 O4 10 O5 1 O6 5 O7 6 O8 9 O9 11 ~O BP_10V U3B U3C U3D U2A U2B U1C

10 The counter produced 6 pulses that were fed to the logic OR gates. The OR gates were connected in such a way that at any instance of time, two were high and the other four were low OR gate produce a voltage of 5V and 0V when high and low respectively. The output current is 0.4mA and 8mA when high and respectively. The common collector amplifier was thus used to amplify current to 8.57mA. The output voltage was 857mV from simulation.

11 The Rectifier and the DC link

12 The 3 phase rectifier was designed using 6 diodes. The dc output voltage is given by Where Vm Is the peak phase voltage. Vm =110V, hence Vdc =182V The dc voltage produced by three phase rectifier had ripples. The ripples were filtered out by the dc link to produce constant dc voltage fed to the pwm inverter.

13 The designed inverter circuit U1 U3 U5 C1 100n C3 100n D1 DIODE D5 U5 L1 B82412A1103K000 L3 B82412A1103K000 L5 B82412A1103K n 100n C5 100n D3 DIODE D5 DIODE B82412A1103K000 L2 B82412A1103K000 L4 B82412A1103K000 L6 B82412A1103K000 U2 U4 U6 C2 100n C4 100n C6 100n D2 DIODE D4 DIODE D6 DIODE

14 The s used were BT 152 with the following specifications Piv =400V Igt=32 g ma Vgt =1V

15 FINAL CIRCUIT Q1 Q3 Q5 L1 100nH L3 100nH L5 100nH D7 1N4004 D8 1N4004 D12 1N4004 C8 1u C9 1u C1 1u R 4 DC 7 Q 3 VCC 8 CV 5 U8 R 4 DC 7 Q 3 VCC 8 CV 5 U9 R25 6.8k R26 100k R27 2k L2 100nH L4 100nH 100nH L6 100nH D9 1N4004 D11 V2 5V V3 110 C10 1u C12 GND 1 TR 2 TH GND 1 TR 2 TH 6 CV C3 6.8n C4 10n C5 10n C6 47n C2 1u Q4 Q6 Q2 1N4004 D10 1N4004 D11 1N4004 G1 1 3 U1 T1 R1 T2 R5 1u C12 1u 1u G LS U2 74LS U3 74LS32 1 U4 BC107BP 6.8k R2 3.3k R3 100k R4 100 BC107BP 6.8k R6 3.3k R7 100k R8 100 T3 BC107BP R9 6.8k R10 3.3k R11 100k R CLK 14 E 13 Q0 3 Q1 2 Q2 4 Q3 7 Q4 10 Q5 1 5 U LS U6 T4 BC107BP R13 6.8k R14 R15 T5 BC107BP R17 6.8k R18 T6 BC107BP R21 6.8k R22 R23 R U5 74LS32 MR 15 CO 12 Q6 5 Q7 6 Q8 9 Q LS32 R14 3.3k R15 100k R R18 3.3k R19 100k R R22 3.3k R23 100k R24 100

16 Implementation The firing circuit was tested in the laboratory. The circuit gave the expected results. The inverter circuit itwas also implemented

17 Rectifier output

18 Firing signals from simulation

19 Output waveforms of the inverter

20 Photograph of gate firing signals

21 CONCLUSION The theory of operation of the 3 phase synchronous motor was covered. The firing circuit was implemented and obtained expected results The prototype inverter was tested in the lb laboratory; the gate firingi signals for the s obtained from the built firing circuit.

22 Recommendations and Further work There be provision of a mounting board for thyristors with heat sinks intact. It is recommended that the next project uses this design to drive the inverter. commutation circuit of the s to be worked on. Use of the designed firing circuit to implement the designed inverter on the available synchronous motor.

23 THE END THANK YOU