1 W High-Voltage Switchmode Regulator

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1 Product is End of Life 3/20 W High-oltage Switchmode Regulator Si908 DESCRIPTION The Si908 high-voltage switchmode regulator is a monolithic BiC/DMOS integrated circuit which contains most of the components necessary to implement a high-efficiency dc/dc converter in ISDN terminals up to 3 watts. A 0.5 ma max supply current makes possible the design of a dc/dc converter with 60 % efficiency at 25 mw, therefore meeting the recommended performance under the CCITT I.30 specifications. This device may be used with an appropriate transformer to implement isolated flyback power converter topologies to provide single or multiple regulated dc outputs (i.e., ± 5 ). The Si908 is available in both standard and lead (Pb)-free 6-pin wide-body SOIC, -pin plastic DIP and 20-pin PLCC packages which are specified to operate over the industrial temperature range of - 0 C to 85 C. FEATURES CCITT Compatible Current-Mode Control Low Power Consumption (less than 5 mw) 0 to 20 Input Range 200, 250 ma MOSFET Internal Start-Up Circuit SHUTDOWN and RESET Maximum Duty Cycle of 99.9 % FUNCTIONAL BLOCK DIAGRAM FB COMP DISCHARGE OSC IN OSC OUT REF Ref Gen Error Amplifier ( %) 2.2 Current-Mode Comparator C/L Comparator OSC R S Clock Q DRAIN - IN (BODY) BIAS Current Sources To Internal Circuits SOURCE IN Undervoltage Comparator Q S R SHUTDOWN RESET

2 Si908 Product is End of Life 3/20 ABSOLUTE MAXIMUM RATINGS Parameter Limit Unit oltages Referenced to - IN ( < IN 0.3 ) 5 Power Dissipation (Package) a IN 20 DS 200 I D (Peak) (300 µs pulse, 2 % duty cycle) 2 A I D (rms) 250 ma Logic Inputs (RESET, SHUTDOWN, OSC IN) to 0.3 Linear Inputs (FEEDBACK, SOURCE) to 7 H Pre-Regulator Input Current (continuous) 5 ma Storage Temperature - 65 to 25 Operating Temperature - 0 to 85 C Junction Temperature (T J ) 50 6-Pin Plastic Wide-Body SOIC (W Suffix) c 900 mw -Pin Plastic DIP (J Suffix) b Pin PLCC (N Suffix) d 00 -Pin Plastic DIP 67 Thermal Impedance (Θ JA ) 6-Pin Plastic Wide-Body SOIC 0 C/W 20-Pin PLCC 90 Notes: a. Device Mounted with all leads soldered or welded to PC board. b. Derate 6 mw/ C above 25 C. c. Derate 7.2 mw/ C above 25 C. d. Derate.2 mw/ C above 25 C. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING RANGE Parameter Limit Unit oltages Referenced to - IN 0 to 3.5 IN 0 to 20 f OSC 0 khz to MHz R OSC 25 kω to MΩ Linear Inputs 0 to - 3 Digital Inputs 0 to SPECIFICATIONS a Parameter Reference Symbol Test Conditions Unless Otherwise Specified DISCHARGE = - IN = 0 = 0, IN = 8 R BIAS = 820 kω, R OSC = 90 kω Limits Temp b Min c Typ d Max c OSC IN = - Output oltage IN (OSC Disabled) R R L = 0 MΩ Room Output Impedance e Z OUT OSC IN = - IN Room kω Short Circuit Current I SREF OSC IN = - IN, REF = - IN Room µa Temperature Stability e T REF OSC IN = - IN Full m/ C Long Term Stability e t = 000 hrs, T A = 25 C Room m Oscillator Maximum Frequency e f MAX R OSC = 0 Room 3 MHz Initial Accuracy f OSC See Note e Room khz oltage Stability Δf/f Δf/f = f (3.5 ) - f (9.5 ) / f (9.5 ) Room 0 5 % Temperature Coefficient e T OSC Full ppm/ C Unit 2

3 Product is End of Life 3/20 Si908 SPECIFICATIONS a Parameter Symbol Test Conditions Unless Otherwise Specified DISCHARGE = - IN = 0 = 0, IN = 8 R BIAS = 820 kω, R OSC = 90 kω SHUTDOWN Pulse Width t Threshold oltage SOURCE R L = 00 Ω from DRAIN to FB = 0 Room Delay to Output e t d R L = 00 Ω from DRAIN to SOURCE =.5, See Figure Room ns Input oltage IN I IN = 0 µa Room 20 Input Leakage Current I IN 0 Room 0 µa Pre-Regulator Start-Up Current I START Pulse Width 300 µs, = 7 Room 8 5 ma Pre-Regulator Turn-Off Threshold oltage REG I PRE-REGULATOR = 0 µa Room Undervoltage Lockout R L = 00 Ω from DRAIN to ULO Room See Detailed Description REG - ULO DELTA Room Supply Supply Current I CC Room ma Bias Current I BIAS Room 7.5 µa SHUTDOWN Delay t SD SOURCE = - IN, See Figure 2 Room Room 50 SW RESET Pulse Width t RW Room 50 ns See Figure 3 Latching Pulse Width 25 SHUTDOWN and RESET Low t LW Room Input Low oltage IL Room 2.0 Input High oltage IH Room 8.0 Input Current Input, oltage High I IH IN = 0 Room 5 Input Current Input, oltage Low I IL IN = 0 Room µa MOSFET Switch Breakdown oltage BR(DSS) I DRAIN = 00 µa Full Drain-Source On Resistance g r DS(on) I DRAIN = 00 ma Room 5 7 Ω Drain Off Leakage Current I DSS DRAIN = 00 Room 0 µa Drain Capacitance C DS Room 35 pf Notes: a. Refer to PROCESS OPTION FLOWCHART for additional information. b. Room = 25 C, Cold and Hot = as determined by the operating temperature suffix. c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. e. Guaranteed by design, not subject to production test. f. C STRAY Pin 8 = 5 pf. g. Temperature coefficient of r DS(on) is 0.75 % per C, typical. Limits Temp b Min c Typ d Max c Error Amplifier Feedback Input oltage FB FB Tied to COMP OSC IN = - IN (OSC Disabled) Room Input BIAS Current I FB OSC IN = - IN, FB = Room na Open Loop oltage Gain e A OL OSC IN = - IN (OSC Disabled) Room db Input Offset oltage OS Room ± 5 ± 0 m Unity Gain Bandwidth e BW OSC IN = - IN Room MHz Dynamic Output Impedance Z OUT Room kω Source ( Output Current I FB = 3. ) Room OUT Sink ( FB =.5 ) Room ma Power Supply Rejection PSRR Room 70 db PWM Maximum Duty Cycle D MAX Room % Dead Time Room 00 ns Minimum Duty Cycle D MIN Room 0 % Minimum Pulse Width Before Pulse Drops Out Room 0 75 ns Current Limit Unit 3

4 Si908 Product is End of Life 3/20 TIMING WAEFORMS.5 - SOURCE 0 - DRAIN 0 50 % t d t r 0 ns 0 % SHUTDOWN 0 DRAIN 0-50 % - t SD t f 0 ns 0 % Figure. Figure 2. SHUTDOWN 0 - t SW 50 % 50 % t LW t f, t f 0 ns RESET 0-50 % 50 % 50 % t RW Figure 3. TYPICAL CHARACTERISTICS 2 M (Hz) f OU T 200 k 20 k 0 k 00 k M r OSC - Oscillator Resistance (Ω) Figure. Output Switching Frequency vs. Oscillator Resistance

5 Product is End of Life 3/20 Si908 PIN CONFIGURATIONS PDIP- SO-6 (Wide-Body) PLCC Top iew Top iew Top iew PIN DESCRIPTION Function Pin Number -Pin Plastic DIP 6-Pin SOIC 20-Pin PLCC SOURCE 7 - IN OSC OUT OSC IN 8 6 DISCHARGE REF 0 8 SHUTDOWN 9 6 RESET COMP 3 8 FB 2 20 BIAS 3 2 IN 2 3 DRAIN NC 3, 5,, 6, 3, 5, 9 ORDERING INFORMATION Standard Lead (Pb)-free Package Part Number Part Number Si908DJ02 Si908DJ02-E3 PDIP- Si908DW Si908DW-T (With Tape and Reel) Si908DN02 Si908DN02-T (With Tape and Reel) Si908DW-T-E3 (With Tape and Reel) Si908DN02-T-E3 (With Tape and Reel) SOIC-6 (WB) PLCC-20 Temperature Range - 0 to 85 C 5

6 Si908 DETAILED DESCRIPTION Pre-Regulator/Start-Up Section Product is End of Life 3/20 Error Amplifier Due to the low quiescent current requirement of the Si908 control circuitry, bias power can be supplied from the unregulated input power source, from an external regulated lowvoltage supply, or from an auxiliary "bootstrap" winding on the output inductor or transformer. When power is first applied during start-up, IN will draw a constant current. The magnitude of this current is determined by a high-voltage depletion MOSFET device which is connected between IN and. This start-up circuitry provides initial power to the IC by charging an external bypass capacitance connected to the pin. The constant current is disabled when exceeds 9.3. If is not forced to exceed the 9.3 threshold, then will be regulated to a nominal value of 9.3 by the pre-regulator circuit. As the supply voltage rises toward the normal operating conditions, an internal undervoltage (U) lockout circuit keeps the output MOSFET disabled until exceeds the undervoltage lockout threshold (typically 8.7 ). This guarantees that the control logic will be functioning properly and that sufficient gate drive voltage is available before the MOSFET turns on. The design of the IC is such that the undervoltage lockout threshold will not exceed the pre-regulator turn-off voltage. Power dissipation can be minimized by providing an external power source to such that the constant current source is always disabled. BIAS To properly set the bias for the Si908, a 820 kω resistor should be tied from BIAS to - IN. This determines the magnitude of bias current in all of the analog sections and the pull-up current for the SHUTDOWN and RESET pins. The current flowing in the bias resistor is nominally 7.5 µa. Reference Section The reference section of the Si908 consists of a temperature compensated buried zener and trimmable divider network. The output of the reference section is connected internally to the non-inverting input of the error amplifier. Nominal reference output voltage is. The trimming procedure that is used on the Si908 brings the output of the error amplifier (which is configured for unity gain during trimming) to within ± % of. This automatically compensates for the input offset voltage in the error amplifier. The output impedance of the reference section has been purposely made high so that a low impedance external voltage source can be used to override the internal voltage source, if desired, without otherwise altering the performance of the device. Closed-loop regulation is provided by the error amplifier, whose kω dynamic output impedance enables it to be used with feedback compensation (unlike transconductance amplifiers). A MOS differential input stage provides for low input current. The noninverting input to the error amplifier ( REF ) is internally connected to the output of the reference supply and should be bypassed with a small capacitor to ground. Oscillator Section The oscillator consists of a ring of CMOS inverters, capacitors, and a capacitor discharge switch. Frequency is set by an external resistor between the OSC IN and OSC OUT pins. (See Typical Characteristics graph of resistor value vs. frequency.) The DISCHARGE pin should be tied to - IN for normal internal oscillator operation. For 98 % duty cycle, the discharge pin must be connected to - IN or can be connected to - IN through a resistor to set the dead time. Remote synchronization can be accomplished by capacitive coupling of a synchronization pulse into the OSC IN terminal. For a 5 pulse amplitude and 0.5 µs pulse width, typical values would be 00 pf in series with 3 kω to OSC IN. SHUTDOWN and RESET SHUTDOWN and RESET are intended for overriding the output MOSFET switch via external control logic. The two inputs are fed through a latch preceding the output switch. Depending on the logic state of RESET, SHUTDOWN can be either a latched or unlatched input. The output is off whenever SHUTDOWN is low. By simultaneously having SHUT- DOWN and RESET low, the latch is set and SHUTDOWN has no effect until RESET goes high. (See the table below.) Table. Truth Table for the SHUTDOWN and RESET Pins SHUTDOWN RESET Output H H Normal Operation H Normal Operation (No Change) L H Off (Not Latched) L L Off (Latched) L Off (Latched, No Change) When power is first applied during start-up, IN will draw a constant current. The magnitude of this current is determined by a high-voltage depletion MOSFET device which is connected between IN and. This start-up circuitry provides initial power to the IC by charging an external bypass capacitance connected to the pin. The constant current is disabled when exceeds 9.3. If is not forced to exceed the 9.3 threshold, then will be regulated to a nominal value of 9.3 by the pre-regulator circuit. 6

7 Product is End of Life 3/20 Si908 DETAIL DESCRIPTION (CONT D) Both pins have internal current source pull-ups and can be left disconnected when not in use. An added feature of the current sources is the ability to connect a capacitor and an open-collector driver to the SHUTDOWN pin to provide variable shutdown time. Output Switch The output switch is a 7 Ω, 200 lateral DMOS transistor. Like discrete MOSFETs, the switch contains an intrinsic body-drain diode. However, the body contact in the Si908 is connected internally to - IN and is independent of the SOURCE. APPLICATIONS IN BYS NC 2 0. µf 220 µf 8 IN SD OSC IN DRAIN OUTPUT 90 k 7 OSC OUT 20 µ F Si908DJ µf NC RESET FB 0 REF COMP k 7.5 k % BYS µf 50 k 7 µf -5 BIAS SOURCE 0.22 µf 2 BYS µf 0. µf 820 k - IN DISCHGR Ω 7.5 k % µf INPUT GND (GND Plane) Figure 5. CCITT Compatible ISDN Terminal Power Supply maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see 7

8 Package Information SOIC (WIDE-BODY): 6-LEAD (POWER IC ONLY) D CAITY NO. ECN: S-0079 Rev. A, 02-Feb-0 DWG: R R R R PIN INDICATOR dp SURFACE POLISHED DETAIL A ( ) R TYP DETAIL A All Dimensions In Inches Document Number: Jan-0

9 Package Information PLCC: 2O-LEAD (POWER IC ONLY) D SQUARE A 2 D SQUARE e B B D 2 MILLIMETERS INCHES Dim Min Max Min Max A A A B B D D D e.27 BSC BSC A ECN: S-008 Rev. A, 02-Feb-0 DWG: 597 A 0.0 mm 0.00 Document Number: Jan-0

10 Package Information PDIP: -LEAD (POWER IC ONLY) E E S D Q A A L B e B C e A 5 MAX MILLIMETERS INCHES Dim Min Max Min Max A A B B C D E E e e A L Q S ECN: S-008 Rev. A, 02-Feb-0 DWG: 599 Document Number: Jan-0

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