EMI Mitigation and Containment in SiC-Based Modular UPS for Commercial Applications

Transcription

1 College of Engineering HDI CPES-Consortium Center for Power Electronics Systems The Bradley Department of Electrical and Computer Engineering College of Engineering Virginia Tech Blacksburg, Virginia, USA WBG HPCS CPES-Consortium EMI Mitigation and Containment in SiC-Based Modular UPS for Commercial Applications Presented by: Rolando Burgos

2 Annual Meeting EMI Mitigation and Containment in SiC-Based Modular UPS for Commercial Applications Rolando Burgos, Dushan Boroyevich Center for Power Electronics December Systems (CPES) Virginia Tech January March 2, 217 Center for Power Electronics Systems 2

3 Commercial UPS System Decentralized power architecture (DPA) ABB Conceptpower DPA 5, 48 V, UL, 1 kw to 3 MW, modular UPS. Each module operates as standalone UPS unit Module features: Rectifier, inverter, bypass switch Back-feed protection Control logic Displays & monitoring Fault tolerant UPS design free of single points of failure March 2, 217 Center for Power Electronics Systems 3

4 Project Objectives Objectives 1. Mitigation and containment strategy for EMI noise generated in SiC-based UPS power modules. 2. Compliance of applicable EMI standards and reliable operation of 1 kw SiCbased UPS module. Why SiC? SiC will boost efficiency and help improve power density of UPS Key approach Use of impedance-based EMI noise channeling to divert it from critical control paths Minimize EMI noise generation within UPS module SiC dv/dt > 5 V/ns, di/dt > 1 A/ns March 2, 217 Center for Power Electronics Systems 4

5 EMI Emissions in SiC Converters March 2, 217 Center for Power Electronics Systems 5

6 UPS Module Architecture 48V Grid Smaller Passives! 8 AC Load With SiC, UPS Module Grid-interface active front-end (AFE) converter DC-DC battery charger Sine-wave voltage-source inverter (VSI) March 2, 217 Center for Power Electronics Systems 6

7 Barrier to Commercialization Internal EMI propagation path EMI Standard IEC624 March 2, 217 Center for Power Electronics Systems 7

8 Topology Selection 5 4 Comparison of CM Noise spectrum W/ f sw = 1kHz 2-level 3-level NPN OPN PPN SVPWM SVPWM 6 db reduction NPP NPO NOO OPO OON PON OOO POO PNN -1-2 NOP OOP ONO PNO -3 SVPWM -4 NNP ONP PNP Frequency [MHz] Three-level is superior to two-level counterpart Inherently lower voltage steps (Vdc/2) and commonmode (CM) voltage generation Greater freedom to mitigate CM voltage generation Higher efficiency at higher switching frequencies March 2, 217 Center for Power Electronics Systems 8

9 Topology Selection Converter Efficiency at Tjunc = 5 2 LEVEL CREE 6 Pack NPC T type 99.% 98.5% 98.% 97.5% 97.% 96.5% 96.% 95.5% Switching Frequency [khz] 2-Level MICROSEMI : 1.2 kv 42 A HB Module ( 49 Ω) CREE : 1.2 kv 59 A 6-pack Module ( 3 Ω) 3-Level T-type MICROSEMI : 1.2 kv 42 A HB Module + 7 V 41 A Discrete MOSFET x 2 3-Level NPC MICROSEMI : 1.2 kv 4 A NPC Module ( 49 Ω) March 2, 217 Center for Power Electronics Systems 9

10 Battery Charger Topology Buck Three-Level Buck NPC PEBB-based Converter Bi-directional dc-dc converter features: CM voltage noise generation Efficiency Battery filter size Neutral point balancing March 2, 217 Center for Power Electronics Systems 1

11 EMI Impact of Battery Charger AC-AC Converter CM Voltage Emissions? Requires formulation of three-port CM circuit model of UPS module March 2, 217 Center for Power Electronics Systems 11

12 CM Circuit Model Derivation Ground of Main Grid Phase Output to Heat Sink DC-Bus to Heat Sink Phase Output to Heat Sink Battery Cabinet to Earth Ground Ground Impedance March 2, 217 Center for Power Electronics Systems 12

13 CM Circuit of UPS Module CM ac-to-ac stage CM dc-to-dc stage March 2, 217 Center for Power Electronics Systems 13

14 Predicted EMI Noise Generation Buck Converter 2 Comparison of CM Noise spectrum Buck Three-level Buck (18deg) Three-level Buck (deg) -2 ~1 db difference Frequency [MHz] Three-Level Buck Converter March 2, 217 Center for Power Electronics Systems 14

15 Single CM-Pulse SVM with Neutral Point Balancing Capability NPN OPN PPN NPN OPN PPN NPN OPN PPN NPO OPO OON PON NPO OPO OON PON NPO OPO OON PON NPP NOO OOO POO PNN NPP NOO OOO POO PNN NPP NOO OOO POO PNN NOP OOP ONO PNO NOP OOP ONO PNO NOP OOP ONO PNO NNP ONP PNP NNP ONP PNP NNP ONP PNP LMZ ( /6,,) MMS (,, /6) MMS2 (,, /6) LMZ: Large + Medium + Zero vector sequence MMS: Medium + Medium + Small vector sequence March 2, 217 Center for Power Electronics Systems 15

16 5 CM Voltage Evaluation F sw = 3kHz time [ms] Comparison of CM Noise spectrum: According to PWM SV PWM SCMVP PWM time [ms] CMVR F sw = 3kHz time [ms] Frequency [MHz] time [ms] March 2, 217 Center for Power Electronics Systems 16

17 Neutral-Point Voltage Balance LMZ NPN OPN PPN dvdc = VdcH-VdcL NPO OPO OON PON -5 NPP NOO OOO POO PNN -1 NOP OOP ONO NNP ONP PNP PNO MMS NPN OPN PPN 2 1 PWM_Type NPO OPO OON PON Sa, Sb, Sc NPP NOO OOO POO PNN MMS2 NPN OPN PPN NOP OOP ONO PNO NPO OPO OON PON NNP ONP PNP 2 Common-Mode Voltage NPP NOO OOO POO PNN -2 NOP OOP ONO PNO I II 1e-2 NNP ONP PNP March 2, 217 Center for Power Electronics Systems 17

18 Gate-Driver with High dv/dt Immunity March 2, 217 Center for Power Electronics Systems 18

19 Impedance-based Channeling of EMI Noise in WBG Converters Successfully applied to gatedrivers for SiC and GaN devices Power circuit presents low impedance path to EMI noise 6 5 GaN-based Three-phase VSI 4 dbua Frequency (Hz) Blue: Gate driver logic path; Green: Gate drive power path; Red: power circuit March 2, 217 Center for Power Electronics Systems 19

20 Digital Control Platform Optical IO interface Gate signals SPI Communication with ADC board Gate driver board High dv/dt immunity (> 5 V/ns) Sensor + ADC board Control Board High computing power: TI28377D + FPGA March 2, 217 Center for Power Electronics Systems Measures at high di/dt and high dv/dt SPI communication with control board 2

21 Next Steps Power Stage Construction Testing Gate-driver testing and SiC module double-pulse test Busbar construction Inverter-rectifier operation testing Battery charger converter testing Controller Testing Sensor + ADC board population Test for SPI communication between main FPGA & multiple sensors Measurement of EMI emissions and design of input and output EMI filters March 2, 217 Center for Power Electronics Systems 21

22 Project Team Sungjae Ohn PhD student Paul Rankin WBGen Fellow MS student Jianghui Yu PhD student Eric Giewont URS, Junior Year John Noon URS, Junior Year March 2, 217 Center for Power Electronics Systems 22