Multitrack Power Factor Correction Architecture

Transcription

1 Multitrack Power Factor Correction Architecture Minjie Chen, Sombuddha Chakraborty, David Perreault Princeton University Texas Instruments Massachusetts Institute of Technology /18/$ IEEE of 20

2 Typical isolated PFC architectures Needed in a wide range of applications Telecom supplies / EV chargers / Adapters / Industry Applications Diode Rectifier Power Factor Correction Energy Buffer Isolated dc-dc Converter V grid L R C B + V B R load n:1 Design targets: (1) Higher efficiency (2) Higher density (3) Better grid interface Challenges and opportunities: (1) Smaller passive component size (2) Higher frequency (3) ZVS with universal input 2 of 20

3 Existing solutions and design targets Conventional single-target methods Diode loss: bridgeless, totem-pole Boost inductor: FCML, Ćuk/SEPIC Energy buffer size: active energy buffer Isolated dc-dc efficiency: DAB, LLC Smaller magnetics: higher frequency o New architecture o 5x - 10x Higher frequency o 50W/inch 3, 92% efficiency TI UCC25600 PFC Demo ~ 10W/inch 3, 200kHz ~ 92% efficiency 5x smaller? Develop a systems method to create mutual advantages 3 of 20

4 Multitrack PFC architecture Switched Capacitor Switched Inductor v Y v BUS S 1 C res1 L res1 Multi-winding Transformer Rectifier v OUT-DC Rectifier C 1 S 2 C 3 L M Q 1 Q 3 -AC C IN L R v X C B C 2 S 3 S 4 C res2 L res2 L M Q 2 Q 4 C OUT PFC Stage Isolation Stage Deliver power in two or more balanced TRACKs AC DC 4 of 20

5 Advantages of the Multitrack PFC Reduced inductor size (Multilevel) Reduced device rating High Performance DCX ZVS of switched-cap Reduced dv/dt ZVS for universal line Switched Capacitor Reduced interleaved winding capacitance Switched Inductor v Y v BUS S 1 Z 1 Magnetics Isolation v OUT-DC Rectifier C 1 S 2 C 3 W 1 Q 1 Q 3 -AC C IN L R v X C B C 2 S 3 S 4 Z 2 W 2 W 3 Q 2 Q 4 C OUT 5 of 20

6 Smaller inductor size and ZVS Boost PFC Hard switching at high line V grid D 420 V 420 V Multitrack PFC Full range ZVS C B V grid 210 V S C B Three operation modes Low Line Mid Line High Line 210V 420V 420V 210V V grid <105V 105V< V grid <210V 210V< V grid <420V 6 of 20

7 Control function blocks of the Multitrack PFC Multitrack PFC Controller Switched Capacitor DCX Controller Voltage Regulation Current Modulation ZVS Timing -AC Mode Selection Rectifier C IN Switched Inductor L R v X v Y C B v BUS C 1 C 2 S 1 S 2 S 3 S 4 C 3 Z 1 W 1 Z 2 W 2 Magnetics Isolation Q 1 W 3 Q 2 Q 3 Q 4 C OUT v OUT-DC 440V 330V 220V 110V v TH V AC 220V AC 265V AC 7 of 20

8 ZVS valley-detection circuits at MHz QSW-ZVS at 1-4 MHz Implemented as logic gates monitor drain voltage v L monitor inductor current (no current sensor) V grid ZVS Controller 2 ZVS Controller 1 C B v ds v d R d i L V ref C d NOR S d I ref v gs [S. Lim, J. Ranson, D. M. Otten and D. J. Perreault, Two-Stage Power Conversion Architecture Suitable for Wide Range Input Voltage, IEEE Transactions on Power Electronics, 2015.] 8 of 20

9 Complete Multitrack PFC controller Mode Selection & Current modulation ZVS #1 ZVS #2 v Y v X v BUS1 I LR modulation ADC Mode Selection ctrlx ctrly disx disy ony V GRID V BUS regulation V thx V thy DAC disy DAC DAC ZVS Loop 1 ctrly disx - + v BUS1 ctrlx ony ADC V REF ZVS Loop 2 Voltage Regulation V GY V GX V BUS /V OUT Multitrack PFC L R v X Logic gates ZVS Controller #1 ZVS Controller #2 v Y Voltage/Current DCX Control DCX TI C2000 MCU 9 of 20

10 Startup and pre-charge of the Multitrack PFC 85V AC -265V AC Rectifier Switched Inductor 420V DC v Y Switched Capacitor v BUS C 1 S 1 S 2 C 3 Z 1 W 1 8:1 Magnetics Isolation Q 1 12V DC Q 3 v OUT-DC -AC C IN L R v X 210V DC C B C 2 S 3 S 4 Z 2 W 2 W 3 Q 2 Q 4 C OUT Startup Strategy: Step 1: Inrush to 210V - keep SC operating, off, on until bus voltage reach 210V (50% of 420V). Step 2: Boost to 330V - force on for a period (e.g., 100ns, 10% duty ratio), keep off until bus voltage reach 315V. Step 3: PI + Non-ZVS - start PI regulation, non-zvs. Step 4: PI + ZVS - continue PI regulation, maintain ZVS. V BUS 410V 420V 330V 210V Time (s) S1 S2 S3 S4 10 of 20

11 Design of the Multitrack DC transformer 2:1 switched cap converter L res1 2-input 1-output LLC converter 7 nf 11 uh Extracted magnetics model 172 pf 785 nh 8:1 1.9 nh C 1 C res1 Q 1 Q 2 R load 7 nf 171 pf 0.7 uh 63 pf S C C3 L res2 Q 3 Q 4 C out 11 uh 776 nh 8:1 C 2 S D C res2 Low-Q LLC operation with ZVS M. Chen, M. Araghchini, K. K. Afridi, J. H. Lang, C. R. Sullivan, and D. J. Perreault, A Systematic Approach to Modeling Impedances and Current Distribution in Planar Magnetics, IEEE Transactions on Power Electronics, of 20

12 Ultra-thin prototype Switched Capacitor Switched Inductor v Y v BUS S 1 Z 1 Magnetics Isolation v OUT-DC Rectifier C 1 S 2 C 3 W 1 Q 1 Q 3 -AC C IN L R v X C B C 2 S 3 S 4 Z 2 W 2 W 3 Q 2 Q 4 C OUT Volume: 3 inch 3 Power: 150W Efficiency target: 92% Peak loss: 15W 3.5 inch 0.4 inch 2.15 inch Electrolytic cap sets the height limit 12 of 20

13 Steady-state grid interface waveforms Multitrack PFC V SW 420V V grid V SW 210V C B Low Line: 110 V AC, 50 W Mid Line: 220 V AC, 100 W High Line: 250 V AC, 120 W 13 of 20

14 Soft-switching operation QSW-ZVS of the Multitrack PFC LLC-ZVS of the Swtched Cap An unique Multitrack ZVS mechanism Capacitive divider ZVS i R V Y V X 14 of 20

15 Startup waveforms Inrush current Boost About 500ms PI control operation with ZVS Startup Strategy: Step 1: Inrush to 210V - keep SC operating, off, on until bus voltage reach 210V. Step 2: Boost to 330V - force on for a period (e.g., 100ns, 10% duty ratio), keep off. Step 3: PI + Non-ZVS - start PI regulation, non-zvs. Step 4: PI + ZVS - continue PI regulation, maintain ZVS. 15 of 20

16 Measured efficiency High line efficiency: 92.0% Low line efficiency: 90.5% Light load: switched-cap loss Heavy load: rectifier loss 16 of 20

17 Summary A Multitrack PFC architecture for single-phase grid-interface. Density 50W/inch % efficiency with 220V input. 90.5% efficiency with 110V input. Reduced inductor size. Reduced dv/dt on transformer. ZVS for MHz grid-interface. ZVS on switched capacitor. 1MHz-4MHz operation, potential to operate at higher frequencies. A new design concept of creating mutual advantages. End-to-end Efficiency (%) Toronto 400W 200kHz TPEL15* Towards high density universal-input low voltage single-phase Isolated PFCs Stanford 250W 450kHz TPEL18* On-Semi 60W 12V, APEC17* TI 310W 24V PMP9640 demo board* CoPEC 600W 24V electrolytic-free APEC16 MIT 250W 24V APEC18 MIT 50W 12V non-universal CPES 65W 20V APEC Power Density (W/inch 3 ) *estimated density This work 150W 12V 17 of 20

18 Thermal imaging of the Multitrack PFC 110Vin, ~50W System works in low line Switched cap circuit has high stress ~200LPF forced air flow from left to right 110Vin, ~100W System works in low line Rectifier loss dominating 220Vin, ~50W System works in high line Switched cap circuit has lower stress 220Vin, ~100W System works in high line Rectifier loss dominating Primary side is very efficient 18 of 20

19 Place your logo here Thanks + Q&A Multitrack PFC Architecture Minjie Chen Sombuddha Chakraborty David Perreault Princeton University Texas Instruments Massachusetts Institute of Technology /18/$ IEEE 1713

20 Benchmark references [TI Demo Board] TI PMP9640 PFC Demo Board: [MIT Thesis] S. Lim, High Frequency Power Conversion Architecture for Grid Interface, Ph.D. Thesis, MIT, [CPEPEC16] Y. C. Li, F. C. Lee, Q. Li, X. Huang and Z. Liu, A novel AC-to-DC adaptor with ultrahigh power density and efficiency, IEEE Applied Power Electronics Conference and Exposition (APEC), [On-Semi APEC17] S. Moon, B. Chung, G. Koo, J. Guo and L. Balogh, A conduction band control AC- DC Buck converter for a high efficiency and high power density adapter, IEEE Applied Power Electronics Conference and Exposition (APEC), [MIT APEC18] Juan Santiago-Gonzalez, David Otten, Seungbum Lim, Khurram Afridi, and David Perreault, Single Phase Universal Input PFC Converter Operating at HF, IEEE Applied Power Electronics Conference and Exposition (APEC), [CoPEC ECCE17] S. Pervaiz, A. Kumar and K. K. Afridi, "GaN-based high-power-density electrolyticfree universal input LED driver," IEEE Energy Conversion Congress and Exposition (ECCE), [Toronto TPEL15] B. Mahdavikhah and A. Prodić, "Low-Volume PFC Rectifier Based on Nonsymmetric Multilevel Boost Converter," IEEE Transactions on Power Electronics, [Stanford TPEL18] L. Gu, W. Liang, M. Praglin, S. Chakraborty and J. M. Rivas Davila, "A Wide-Input- Range High-Efficiency Step-down Power Factor Correction Converter Using Variable Frequency Multiplier Technique," IEEE Transactions on Power Electronics, of 20