Silicon Limit Electrical Characteristics of Power Devices and ICs

Transcription

1 Slco Lmt Electrcal Characterstcs of Power evces ad Cs Ako Nakagawa, Yusuke Kawaguch ad Kazutosh Nakamura Toshba Cororato, Semcoductor Comay 58-, Horkawa-Cho, Sawa-Ku, Kawasak, -85, Jaa; Abstract The reset aer redcts the slco lmt characterstcs of GBTs, ad rooses a ovel devce structure to acheve the lmt. Power MOSFETs have bee greatly mroved for C-C coverter alcatos. t s show that achevg hgher effcecy the coverters ecesstates the tegrato of ower MOSFETs ad the erheral crcuts a sgle ackage. The authors roose a deal gate drve to realze the ultmate hgh seed swtchg of ower MOSFETs. Moolthc tegrato of ower devces ad the gate drve crcut s cosdered to be a deal soluto. The authors reort the develomet of A ch C-C coverters. The authors also roose a ew FOM for swtchg seed comarso of varous ower devces. Keyword: GBT, Slco Lmt, MOSFET, MCM, Low medace gate drve, C-C Coverter. EOLUTON OF POWER ECES Power devces have evolved so radly that.k GBTs have dslaced 4.5k GTOs, whch were develoed the late 8 s for tracto cotrol of bullet tras. Fgure ad comare alcato felds of ower devces 997 ad 5, resectvely[]. The dstgushed dfferece betwee the two fgures s that most of the alcatos of GTO ad BTr have bee relaced by those of GBT ad the module. MOS gate devces are redomatly used most of the alcato felds, cludg LMOS ower Cs, MOSFETs for low voltage ad medum voltage alcatos ad GBTs for hgh ower alcatos. Suer jucto MOSFETs were develoed ad reorted 998[]. They broke through the so-called slco uolar devce lmt the voltage rage from to 9 ad sgfcatly ehaced the otetal of slco devces. Aother recet remarkable advacemets are see hgh seed trech ower MOSFETs ad ower C techologes. Swtchg seed of trech MOSFETs has bee greatly mroved sce 999 order to meet the requremet of hgh effcecy ad hgh d/dt of oltage Regulator Modules for CPUs. The detals are descrbed Secto. Power C techologes are classfed to two categores. Oe s hgh voltage SO ower Cs[,4] for moolthc C motor cotrol ad PP flat ael dslay drve. The other s low voltage ower Cs for motor cotrol ad ower sules[5]. We develoed the world frst 5 oe ch verter Cs for C motor cotrol 994[4]. the reset aer, We demostrate A oerato of ch C-C coverters Secto. Recetly, t has bee ofte oted out that slco devces face the materal lmt. t s mortat to make clear the lmt characterstcs of slco devces ad the future otetal to be exloted. The authors also roose ew FOM[6] order to comare the otetal of varous ower devces. Power (A) M M M K K K MW class Power Cotrol SCR GTO BTr Module Trac Ar Co. K UPS GBT K Frequecy (Hz) Motor Cotrol Robot MOSFET Module MOSFET K Automoble Swtchg Power Suly CR Audo Am. M Fg. Alcato felds of ower devces 997. Power (A) MW class Power Cotrol MW Class Motor Cotrol M M M K K K SCR Press GTO Pack EGT Ar Co. K GBT Module screte GBT K Frequecy (Hz) UPS Robot, Welder Mache MOS FET Automoble K Swtchg Power Suly M Fg. Alcato felds of ower devces 5. CR Audo Am.

2 . GBTs A. Bref Hstory of GBT The cocet of GBTs was frst descrbed the atet by Becke et al[7]. The frst challege for GBT was reorted by Balga et al. 98[8]. Sce the, umerous aers were ublshed to mrove the devce characterstcs such as frst swtchg seed[9,] ad large curret caablty[]. the early develomet stages, GBTs suffered from the latch-u of the arastc thyrstors ad the oor curret caablty. Frst real GBTs, or No-latch-u GBTs, comletely suressg the arastc thyrstor acto, were develoed by the authors grou 984[,]. t was revealed that the o-latch-u GBTs exhbted a extraordarly large safe oeratg area so that they acheved so-called short-crcut-wthstadg caablty, for the frst tme[], the GBT hstory. The electrcal characterstcs of GBTs have bee greatly mroved sce the advet of the frst GBT roducts from Toshba 985. However, the theoretcal lmt of GBTs has ot bee dscussed yet. the reset aer, the authors reset the theory for the slco lmt of GBT[]. B. Theory for Slco Lmt of GBTs Ths secto rooses a theory of the lowest forward voltage dro GBTs ad also rooses a ew trech gate GBT, realzg the theoretcal lmt[]. The adoted assumto s asymmetrcal coducto: all of the curret flows by electros. Holes cotrbute oly to the coductvty modulato. From the assumto of o hole curret flow, the followg three equatos are vald uder the hgh jecto codto: J = q + qμ E = -----Eq.(), x J = J = q ----Eq.() x kt E = -----Eq.() q x The above three equatos are satsfed by the carrer desty dstrbuto whch s aroxmately a learly decreasg fucto from cathode to aode as show Fg.. The electro desty,, s assumed to be equal to the hole desty,. The fal curret desty - voltage relato of Eq.(9) ca be derved by tegratg Eq.() wth the boudary values ad W, defed Fg., together wth Eqs.(5-8). The electro dffuso coeffcet,, s aroxmated by a =, Eq.(4) + b where a ad b are costats (a=.7e8, b=9.9e6). The total curret, J, s equal to the electro dffuso curret flowg to the -emtter ad s gve by J=q e /Q, Eq.(5) where Q ad e deote the total dose of the -emtter ad the electro dffuso coeffcet the -emtter. The forward voltage, F, s gve by the summato of the voltage dro the -base,, ad the dffuso voltage for the carrers the -base, dff. F = + dff Eq.(6) =(kt/q)l( w / ) Eq.(7) dff =(kt/q)l( w / ) Eq.(8) The fal curret voltage relato s gve by Eq.(9). kt QJ JW F = l[ {( + b ) ex( ) b}] q q qa + R ch J.... Eq.(9) the equato, W ad R ch deote the -base wdth ad the chael resstace, resectvely. E m tter + W b Gate W N - Fg. Learly graded carrer dstrbuto N-base Curret esty GBT Eq.(9) Theory & TCA & TCA Sm Forward oltage Fg.4(a) e buff Cov. GBT C ollector X Emtter - buff Collector Y Fg.4 (b) Mesa wdth Fg.4(a) Eq.(9) s lotted ad comared wth covetoal 6 GBTs. The TCA smulato result of the roosed structure Fg.4(b) exactly cocdes wth the Eq.(9). Fg.4(b) Proosed GBTs wth arrow mesa structure. The slco mesa wdth, d, s 4 m ad the trech deth s μm. Fg.4(a) comares Eq.(9) ad the curret-voltage curve of covetoal 6 GBT. Equato (9) redcts that oe order of magtude mrovemet the curret-voltage relato s ossble, comared wth those of covetoal GBTs. order to realze the slco lmt characterstcs, the author rooses a ew GBT structure[], as show Fg.4(b). f the trech to trech dstace (mesa wdth) s as arrow as the thckess of the verso layer, the two verso chael layers o the both trech sde walls merge wth each other ad the whole mesa rego d gate

3 becomes a verso layer. For examle, f the mesa wdth s less tha 4m, the duced electro desty s greater tha 5x 7 cm -. The verso layer effectvely blocks the hole curret flow the mesa, realzg the stuato that most of the curret flows by electros. The calculated curret voltage curve of the roosed arrow mesa GBT exactly agrees wth the curret voltage relato of Eq.(9), as show Fg.4(a). C. Practcal GBT Lmt The curret-voltage curve sgfcatly deeds o the mesa wdth as see Fg.5. Practcally seakg, the forward voltage s substatally low f the mesa wdth s below.5μm. ths secto, we roose ractcal slco lmt of GBTs, usg a assumto: flat carrer rofle the -base. The curret flows the -base oly by drft uder the assumto, ad the electro desty,, s assumed to be equal to the hole desty. The total curret s gve by J = J + J = q( μ + μ E Eq.() Curret esty [A/cm ] ) GBT Mesa wdth=4m Eq.(9).μm Mesa wdth=.5μm Eq.(5) Q e = Cov. GBT Forward oltage [] Fg.5 Calculated - curves of 6 GBT by TCA are show wth mesa wdth as a arameter. Eqs.(9) ad (5) are also lotted ad comared wth calculated results. The curret-voltage relato, Eq.(5), for the ractcal lmt ca be derved usg Eqs.(-4). E =, Eq.() W kt dff = l( ) Eq.() q + J.μm F = dff, Eq.() F = q e Q kt μq J = l + W q q (μ + μ ) e Eq.(4) J qμ (μ + μ )Q μrch + J -----Eq.(5) μ + μ the above equatos, dff W, Q, R ch ad e are defed the same way as before. e Fg.5, Eq.(5) s also lotted, assumg R ch = ad Q e = cm - for 6 GBTs. The ractcal lmt curret-voltage curve, Eq.(5), agrees wth the curret-voltage curve of GBT wth.μm mesa. t should be oted that the ractcal lmt ca be acheved by GBTs wth moderately arrow mesa ad ts o-resstace s stll very close to the deal lmt as show Fg.6.. RoA (mωcm ).... S GBT S SJ -MOS SC MOS GaN HEMT S Lmt SJ-MOS SC Lmt GaN Lmt S GBT Practcal Lmt Slco GBT Lmt Breakdow oltage () Fg.6 The roosed slco GBT lmt s comared wth other state of the art devces. Theoretcally redcted ractcal GBT lmt s show together. Practcal lmt s very close to the deal lmt. GBT theoretcal lmt eve exceed so-called SC lmt for over k rego. The fgure also shows the reorted o-resstaces of Suer-Jucto MOSFETs ad ew materal devces. Curret esty (A/cm ) GBT W tch / Mesa Wdth =.-.5um Gate oxde W tch =.um W tch =.um W tch =7um Forward oltage () Fg. 7 - curves are show wth devce cell tch (W tch ) as a arameter uder the codto that flat carrer rofle s mataed. Forward voltage s large for GBT wth W tch of 7μm because the chael resstace s large ste of a arrow mesa of.5μm.. mrovg GBT Characterstcs Fgure 6 comares the o-resstace of the theoretcal GBT lmt wth state of the art devces. Slco lmt GBT wll realze a low o-resstace, whch s eve below the SC lmt for over.k rage. Hgher oeratg curret desty s ofte demaded for a alcato of hybrd electrc vehcles. Ch shrk or a oeratg curret desty exceedg 5A/cm wll be realzed GBTs, f the ssue of short-crcut-wthstadg caablty s roerly hadled. Fgure 7 shows how the curret-voltage relato chages as the cell tch creases uder the codto that a flat

4 carrer desty dstrbuto s mataed the -base by keeg the mesa wdth as arrow as betwee.μm ad.5μm. As the cell tch creases, the total chael wdth decreases ad, hece, the saturato curret values geerally decreases. However, the forward voltage creases evtably for a hgher curret desty rego such as 5A/cm.. POWER MOSFET A. Recet Advacemet MOSFET R S(ON) Qgd Q (mω C ) R S(ON) U-MOSⅡ UMOSⅡ G =4.5, =4 Hgh Seed U-MOSⅢ Ultra- Hgh Seed U-MOSⅢ Ultra Hgh Seed UMOSⅤ Fg.8 Toshba s roadma for hgh seed MOSFETs Ultra Hgh Seed UMOSⅥ 8 Sce 999, swtchg seed of ower MOSFETs has bee greatly mroved for the alcato of RM (oltage Regulator Module) for CPUs. The FOM, R o Q gd, s covetoally adoted for hgh seed MOSFETs as a desg gude. Fgure 8 shows the Toshba s roadma of ower MOSFET. R o Q gd was mroved from mωc 999 to mωc 5. The buck coverter effcecy was mroved from 85.5% to 9% 4. B. Otmzato of Power Stage C-C Coverter f oe try to ursue hgher effcecy of sychroous buck coverters, t s recogzed that the followg three tems are equally mortat addto to the mrovemet of MOSFETs: ()otmzato arastc ductaces of the ower stage crcuts, () reveto of self-tur-o of the low-sde MOSFET, ad () dead-tme otmzato. Fgure 9 shows the fluece of each arastc ductace o buck coverter effcecy[5]. Each arastc ductace s defed the crcut Fg. 9. The most fluetal oe s the hgh sde MOSFET source ductace, L HS. f the MOSFET s tured-o, the rad dra curret crease rate, d /dt, duces the voltage dro the arastc ductace L HS. The duced voltage dro reduces the actually aled gate-source voltage, resultg the delayed tur-o. order to realze the frst swtchg-o, the arastc source ductace should be mmzed. The other arastc ductaces crease the voltage ske the swtchg trasets of hgh sde MOSFET ad crease the ower loss. The arastc ductaces clude the oes sde the ackage ad the oes the PCB board. order to reduce the arastc ductaces ad resstaces, mult-ch module (MCM) was develoed. Fgure shows MCM, called rmos, roosed by tel. Three chs of hgh-sde ad low-sde MOSFETs ad the drver crcut are mouted a QFN56 ackage, thus mmzg the arastc medaces. rmos mroves the coverter effcecy by % comared wth the dscrete MOSFET soluto as show Fg.. rver Crcut Fg.9 The left fgure shows aalyzed crcut of buck coverter. The rght fgure shows fluece of arastc ductaces o coverter effcecy HS-MOS LS-MOS To vew rver C Bottom vew rver C Hgh sde MOSFET Low sde MOSFET Fg. MCM (rmos) tegrates hgh-sde ad low-sde MOSFETs ad the drver crcut a QFN56 ackage. Effcecy (%) screte MCM Outut Curret out (A) N=,OUT=.,fc=MHz Fg. Comarso of coverter effcecy betwee MCM ad dscrete MOSFET soluto (ut volt:, Outut volt:., Swtchg Freq:MHz) Total ower loss (W) (MOSFET+drver) Q Lx Q L H L HS L L SB L LS out Coverso Effcecy (%) Hgh Sde Source L HS ductace (H) :, g:5,out:a,fsw:mhz,uty:. Low Sde dra L L Rg+Rdrver=.66Ω Rg+Rdrver=.Ω Rg+Rdrver=.4Ω Ls(H) Low Sde Source L LS Hgh Sde ra L H Fgure eedece of ower loss o total arastc ductace, L S (=L HS +L H +L LS +L L ), the ower stage crcut s show wth gate crcut medace as a arameter. The gate crcut medace, R g +R drver, cludes the crcut medace ad the gate resstace of the ch. The total ower loss does ot decrease mootocally as the arastc ductace decrease.

5 Power loss (W) hgh sde tur-off loss hgh sde tur-o loss Power cosumto (W) Ls (H) Fgure eedece of hgh sde MOSFET tur-o ad tur-off loss o total arastc ductace, L S, (= L HS +L H +L LS +L L.) Hgh sde MOSFET tur-o loss crease radly as the arastc ductace (Ls) decreases. The tur-off loss decreases as Ls decrease. the followg, the otmum arastc ductace values are further examed by usg the sub-crcut model develoed ad otmzed for the ower MOSFETs. Fg. shows the deedece of ower loss o the total arastc ductace, L S (=L HS +L H +L LS +L L.) The arameter the fgure s the total resstace value of the gate drver crcut. The total resstace cludes the gate crcut medace ad the gate resstace of the MOSFET ch. t s foud that there s a otmum ductace value that mmzes the total ower loss. Ths s because the tur-o loss of the hgh sde MOSFET creases radly as the arastc ductace value s excessvely decreased, as show Fg.. Whe the total resstace value of the gate drver crcut reduces from.66ω to.4ω, both the otmum ductace value ad the total ower loss decrease smultaeously as show Fg.. d g ds (b) Waveforms for Ls=.H Fgure 4 Calculated waveforms of Hgh sde MOSFET durg tur-o ad tur-off erod are show for the two cases of (a) Ls=.H ad (b) Ls=.H the codto of total gate crcut resstace =.4 Ω. the case of L=. H, a large ower loss occurs durg tur-o erod. the case of L=. H, hgh sde MOSFET dra-source voltage radly decreases because a voltage of L d/dt s aled to the arastc ductace, ad hgh sde MOSFET tur-o loss s reduced. oltage (), Curret (A) 5 5 gs d ds Power cosumto (W) d ds g (a) Waveforms for Ls=.H Tme (sec) Fg.5 TCA results of MOSFET Tur-off wth deal gate drve crcut. The tur-off tme s s. Fgure 4 (a) ad (b) show the tur-o ad tur off waveforms of the MOSFET for the two cases of the total ductace value, Ls,.H ad H, resectvely. the case of Ls=.H, a large ower loss occurs the hgh sde MOSFET durg the erod of the hgh sde MOSFET tur-o, because a large reverse recovery curret of the body dode of the low sde MOSFET flows a short tme erod. A large voltage dro occurs across the hgh sde MOSFET, because the arastc ductace s too small to restrct the d/dt. the case of L=. H, a large d/dt s reveted by the arastc ductace of H ad the tur-o loss of hgh sde MOSFET s reduced. t should be oted that the total arastc ductace the ma curret ath for the develoed MCM module s chose to be the otmum value.

6 C. Future Techology for Mult-Ch-Module[] the covetoal gate drve crcut, swtchg seed s determed by Q gd / g. The total ower loss s exressed as follows: Q gd Ploss = R o + f + Q ds f + Q G G f,... Eq.(6) where the st, d, rd ad the 4th terms show the o-state loss, the swtchg loss, the ma jucto caactace loss ad the gate charge loss, resectvely. The ma jucto caactace loss s assumed as Q ds /, where Q ds deotes the outut charge, Q oss. The coeffcet s /, ot /. The reaso s descrbed Aedx. f the ower loss s determed by the frst two terms Eq.(6), the roduct of R o ad Q gd ca be used reasoably as a fgure of mert (FOM) for MOSFETs. f the gate drve crcut medace s assumed to be very low ad f the value of Q gd / G s eglgbly small, the d term Eq.(6) dsaears. The swtchg loss s determed oly by the ma jucto caactace loss as show Eq.(7). Ploss = Ro + Qds f + QGG f -----Eq.(7) R o Q ds A g f + Q the above equalty equato, the equalty holds f the frst ad the secod terms are equal to each other. The, the ower loss deeds o R o Q ds. Aga, f the thrd term s assumed to be small comared wth the frst two terms, R o Q ds s regarded reasoably as a ew FOM[6], whch s dscussed detal the ext Secto. Effcecy (%) S lmt G G out(a) f :, g:5,out:.,fsw:mhz R G =.4Ω R G =.7Ω Fg.6 eedece of coverter effcecy o total gate crcut resstace, R G. The le S lmt shows the effcecy obtaed wth slco lmt MOSFET of 5mΩmm Ro, as descrbed the text. Fg. 5, t s cofrmed by TCA that MOSFETs ca be swtched-off sec f a very low medace (mω) gate drve s used ad a suffcetly large gate curret s suled. There s o lateau the gate voltage waveform, orgatg from Q gd / G [6]. t should be oted that the swtchg-off loss, Q ds /, does ot deed o the magtude of the dra curret. Ths s the dstgushed dfferece from the covetoal swtchg, whose swtchg loss deeds o the Q gd value ad the dra curret. Fgure 6 comares the effcecy of C-C coverters for the gate drve codtos of covetoal gate drve crcut ad the low medace (.4Ω) gate drve crcut. For the low medace gate drve codto, t s redcted that the effcecy wll mrove ad acheve more tha 9% at A outut curret eve f the same MOSFETs are used. These results mly that the effcecy C-C coverters s stll exected to be mroved future. t s also redcted that more tha 95% coverso effcecy s exected eve for A outut curret, as see Fg.6, f we ca develo ultmate MOSFETs wth the slco lmt secfc o-resstace of 5mΩmm wth retag low Qgd value of.67cmm -. R o Q str [mωc] e e e4 e5 e6 MOSFET S Lmt k k Breakdow oltage [] Fg.7 R o Q str as fucto of breakdow voltage. New FOM [, 6] SC Lmt SJMOS GBT GBT GaN FET GaN Lmt SC MOS ths secto, we troduce a ew fgure of mert, NFOM, based o Equato(7). NFOM = R o Q str = T sw F, Eq.(8) where swtchg tme, T sw, ad forward voltage, F, are exressed as follows: Qstr T sw =, F = Ro Eq.(9) Q str deotes the stored carrer quatty betwee the dra ad the source termals. For MOSFETs, Q str s equvalet to Q ds (=Q oss ). the followg, NFOM s comared wth Balga s FOM. Q str ad R o are rereseted by the followg equatos for deal MOSFETs: Q str =εe C Eq.() R o =4 B /εμe C Eq.() The, the NFOM s exressed as follows for the case of the deal slco MOSFETs. NFOM=4 B /μec =4 B /BHFOM ---Eq.()

7 The NFOM value s closely related to the BHFOM oly f the deal MOSFET s assumed. Equato () assumes that the aled voltage s the same as the breakdow voltage. NFOM ca be defed for varous devces, cludg bolar devces. t should be oted that Q str deeds o the oeratg codtos just lke Q gd. Fgure 7 comares NFOM amog varous devces. NFOM of GBTs deeds o the desg of the devces. The squares show the NFOM of the GBTs roosed Secto B. The crcles show hgh seed GBTs, havg flat carrer desty dstrbuto. Suer-jucto MOSFETs dcated by crcles show the deal smulato results. SC MOSFETs are lotted, usg the reorted o-resstace values. NFOM value of GaN FETs s calculated by multlyg the reorted o-resstace ad two-dmesoal electro gas desty of x cm -. For less tha rage, covetoal slco MOSFETs are sueror, ad the values of ther NFOM are lower tha those of the ew materal devces. A SNGLE CHP C-C CONERTER Fgure 8 shows the techology advacemet ower Cs. The desg rule of ower Cs kees scalg dow, followg the CMOS learg curve. The reaso s show Fg.9, where MOS secfc o-resstace s show as a fucto of the desg rule. Lateral MOS are frequetly used as outut ower devces ower Cs. The secfc o-resstace smly decreases as the desg rule becomes small, ad thus, ch shrk s ossble. Ths s the ma force why we mgrate toward fer desg. (a)nch LMOS (b)pch LMOS Fg. Cross-sectoal vew of 5 outut ower devces. A good method to realze a low medace gate drve crcut s to tegrate the drver crcuts wth the ower MOSFETs. Ths ca be easly realzed usg lateral MOSFET (LMOS) ad BC ower C techology. ths chater, we show the develomet of A ch C-C coverters ad ther hgh seed swtchg caablty. A. evce Structure Fgure shows a cross-sectoal vew of outut LMOS devces based o.6μm BC rocess. The bured N + layer s electrcally coected to the source electrode to reduce the coulg betwee the dra ad the substrate. Three metal layers wth a μm thck to metal layer are utlzed. For the otmzed Nch LMOS, the tycal breakdow voltage, the threshold voltage ad the secfc o-resstace are 5.,.85 ad.mωmm, resectvely. Layout of to metal Hgh Sde MOS Source Source Source Fl-ch ra ra ra Low Sde MOS Solder Bum PCB Fg. Assembled mage of ch o PCB. The dra ad the source bums are electrcally coected by thck Cu metal wres the PCB Fg.8 Techology advacemet ower Cs Secfc O-Resstace (mω/mm ) esg Rule Fg.9 Lateral MOS o-resstace vs. desg rule. B. Bum Techology t s geerally true that the secfc o-resstace of lateral MOS deterorates cosderably wth crease the devce sze due to the creased tercoecto resstace. order to reduce the tercoecto resstace, we adoted the bum techology. Fgure shows the smlfed mages for the layout atter of the to metal of the ch ad the Cu atter o a rted crcut board (PCB). The ch s attached to the PCB board through bum balls. The thck Cu metal layers the PCB ca be used as tercoecto wres ad electrcally coect the dra

8 ad source bums. Ths method sgfcatly reduces the tercoecto resstaces of lateral MOSFETs. C. strbuted Gate rver Layout Whe the area of LMOS s large, the gate curret becomes creasgly large. The whole LMOS devce does t uformly tur-o or -off because the gate drve delay may occur wth the large LMOS devce due to the resstaces ad the arastc caactaces of the tercoecto metal layers. Esecally the tur-off erod, the gate delay may cause sgfcat o-uform swtchg. We roose dstrbuted gate drver crcut layout to overcome the roblem[7] Fgure comares the dstrbuted gate drver crcut layout ad the covetoal cocetrated gate drver crcut layout. the cocetrated gate drver crcut layout (a), large gate curret causes o-uform gate voltage dstrbuto. the dstrbuted drver crcut layout (b), a umber of gate drvers are formed the local regos earest to the segmeted LMOS devces. The legth betwee the each drver ad the each segmeted LMOS s made as short as ossble. The curret magtude the sgal bus le electrcally coectg the re-drver ad the local gate drvers s small, ad does ot cause the gate sgal delay. Fgure (a) ad (b) comares the smulated traset characterstcs of the dra currets for the earest segmet LMOS ad the farthest segmet LMOS. The smulato codto s of the aled voltage ad.ω of the load resstace. The whole LMOS devces ca be uformly tured-o ad -off for the dstrbuted drver case. The LMOS tur-off loss wth dstrbuted drver crcut ca be reduced to 54% of the LMOS wth cocetrated drver crcut.. Exermetal Results Fgure shows the mcrograh of the fabrcated ch based o the.6μm BC rocess. The ch sze s.mm. A umber of local gate drver crcuts for segmeted LMOS are laced betwee N-ch ad P-ch LMOS. Fgure 4 shows the measured outut characterstcs of a large area Nch LMOS (the effectve area.6mm ). The o resstace s 9.7mΩ (@dra curret=5a, gate voltage=5). Fgure 5 shows the swtchg characterstcs of the fabrcated ch at the codto of a ductace of μh. (HghSde), (LowSde) ad (sw) dcate the ut gate sgals for P-ch LMOS ad N-ch LMOS ad the dra termal voltage of the P-ch ad the N-ch LMOS devces, resectvely. The rse tme of (sw) s s. The fabrcated devce the oe-ch C-C coverter exhbted hgh seed ad hgh curret swtchg caablty of A. Fgure 6 shows the measured effcecy vs. outut curret whe the ut voltage ad the outut voltage s ad., resectvely, ad the swtchg frequecy s 78kHz. The measured maxmum effcecy s 89% at 5A of curret. Cocetrated rver Crcut Gate Curret LMOS ra Curret Parastc metal layer resstace & caactace Sgal Bus Le Load Parastc Gate Resstace (a) Cocetrated gate drver crcut layout Pre-drver crcut Sgal Curret strbuted rver Crcut Sgal Bus Le Load LMOS Gate Curret (b) strbuted gate drver crcut layout Fg. Comarso of dstrbuted gate drver crcut ad cocetrated gate drver crcut. The rght had sde fgures show the smulated traset waveforms of the dra currets of the earest ad farthest segmeted LMOS s. Bum PA P-ch LMOS rver Crcut N-ch LMOS PCB Ch Fg. Mcrograh of fabrcated ch based o.6μm rocess. The ch sze s.mm ra Curret ds (A) gs=5,4, ra Curret gs= gs=.5 gs=. gs=. gs=. gs=..e+.e-.e-.e- 4.E- 5.E- ra-source oltage ds () Fg.4 Outut characterstcs of a large area devce wth bum techology(the effectve area.6mm ).

9 (HghSde) (LowSde) sw () 5 5 out=. L=A (HghSde) (sw) -5 s.66e-6.67e-6.68e-6.69e-6.7e-6.7e-6.7e-6.7e-6.74e-6 Tme (sec) Fg.5 The swtchg characterstcs of the fabrcated ch at the codto of a ductace uh. The rse tme of swtchg ode s s. REFERENCES [] A. Nakagawa, Proc. of MEL 6, [] G. eboy et. al. : EM Tech. gest,. 68, 998 [] A.Nakagawa et. al., Proc. of SPS,.6(99) [4] A.Nakagawa et. al., Proc. of SPS,.(999) [5] T. Eflad, Proc. of SPS,. () [6] A. Nakagawa et. al., EEJ Joural,ol.5,.758(5) [7] H.W.Becke et. al., USP 4647(98) [8] B.Balga et. al., EEE EM Tech. gest,.64(98) [9] J.P.Russel et al., EEE EL,.6(98) A.M.Goodma et. al., EEE EM Tech. gest,.79(98) [] M.F. Chag et. al., EEE EM Tech. gest,. 8(98) [] A.Nakagawa et. al., EEE EM Tech. gest,.86(984) [] A.Nakagawa et. al., EEE EM Tech. gest,.5(985) [] A. Nakagawa, Proc. of SPS 6,.5 (6) [4] M.Nato et al., EEE Tras. E-8,.(98) [5] Y. Kawaguch et. al. : Proc. of SPS 5,. 7 [6] M.Tsukuda et. al., Proc. of PEC 5,.8 [7] K.Nakamura et al., Proc. of SPS 7,.45(7) [8] Y.Kawaguch et al, 6 PESC Record,.85 [9] A. Nakagawa, Proc. of LS-TSA,.(8) Fg.6 Measured effcecy vs. outut curret wth swtchg frequecy as arameter. (@ut voltage=, outut voltage=.) APPENX for SECTON C The stored eergy the ma jucto, P str, the tur-off traset ca be calculated, assumg ste jucto aroxmato ad ductve load, where the dra curret,, kees the same value wth the tur-off traset. Usg the voltage,, as a fucto of deleto layer wdth, d, the fal result s easly derved the followg. qn = d, δt = qnδd, = t, = ts, ε εqn εqn,where t s deotes the swtchg tme. ts Qds = ts = (εqn ) Ploss = dt = ts = Qds 6εqN ACKNOWLEGEMENT The authors thak Yoshhro Yamaguch, Toshyuk Naka, Noro Yasuhara, Kech Matsushta, Tomohro Kawao ad Hrosh Take for cotrbutg to the reset work, ad thak Masakazu Yamaguch ad Kouhe Morzuka for rovdg the oortuty for the reset work.