Variable Lateral Silicon Controlled Rectifier as an ESD Protection

Transcription

1 Varable Lateral Slco Cotrolled Rectfer as a ESD Protecto PETR BETAK, VLADISLAV MUSIL Deartmet of Mcroelectrocs, FEEC Bro Uversty of Techology Údolí 53 CZECH REPUBLIC etr.betak@hd.feec.vutbr.cz Abstract: - The Varable lateral Slco Cotrolled Rectfer (VLSCR) s a SCR based structure wth the ossblty to tue I-V saback characterstcs. Ths effect s mortat for a ESD (electrostatc dscharge) rotecto desg. The ESD rotecto structures act as a rotecto of tegrated crcuts agast arastc electrostatc dscharge. Amog ofte used structures belog structures havg saback tye of I-V characterstc. Tycal s a gate-grouded NMOS trasstor [3] or a SCR [3]. Ths text s dealg wth the VLSCR structure whch eables I-V saback characterstcs tug accordg to the alcato demad. Smulated techology was.5µm CMOS very hgh voltage (VHV Itegrated Crcuts). Measuremet was doe 1.5 µm BCMOS rocess. Key-Words: - ESD, SCR, LVTSCR, VLSCR 1 Itroducto Fg.1 llustrates a rcal coecto of some ESD rotecto cells ad requred I-V behavour. A radom ESD stress goes through the ESD clams to groud ad a core crcut s ot edagered. The rotectos must be actve oly durg the ESD evet. ESD clams are based maly o dodes ad they are ofte used as ower clams [3]. The ower clams eed to have a voltage referece uo V DD level otherwse a ower suly could short out. Fg.1 Coecto of ESD rotecto clams The tycal saback I-V characterstc s show Fg.2. The requred saback rotecto devce should fulfl subsequet codtos: the value of a leakage curret s low, the ESD curret the area of the saback s hgh, robustess of the ESD cell s suffcet. A mortat feature of the ESD structure s trgger voltage adjustablty ad holdg voltage adjustablty. For the ESD rotectos desg the holdg voltage adjustablty ad the trgger voltage adjustablty s the key to form requred I-V characterstc. The voltage trggered Fg.2 Sa-back I-V characterstc of commo ESD devce. Nevertheless, the dode strg for the suly clams has several dsadvatages lke hgh resstaces ad slow erformace. The deal ESD rotecto structure s a Slco Cotrolled Rectfer (SCR) for the sake of ts quck erformace, but the roblem s the hgh trgger codto (aroxmately 4-5V) ad low holdg voltage (~1V)[2]. Ths lmts the alcato of SCR as a ower suly rotecto. However, there s a way to desg the SCR havg better trggerg ad hgher holdg voltage. The frst aroach was troduced as a Modfed Lateral SCR [2]. The trgger voltage s determed by N-well to a P-substrate breakdow. I MLSCR s serted the N+ dffuso N-well to ISSN: Issue 8, Volume 5, August 28

2 decrease the trgger voltage. But the holdg voltage the MLSCR s stll too low. The frst ower suly adjustable SCR-based structure was troduced by Chatterjee [1]. The structure was termed as Low Voltage Trggerg SCR (LVTSCR). 2 Covetoal LVTSCR (low voltage-trgger Slco Cotrolled Rectfer) The LVTSCR structure uses a MOS trasstor arallel wth a SCR. Therefore, the trggerg codto s set o the MOS breakdow level ( the submcro CMOS rocess aroxmately 1-15V) ad the holdg voltage level s gve by X ad L dmeso. The dmeso L (Fg.3) reresets a legth of NPN base rego the SCR structure. By chagg L, the curret ga of the arastc bolar trasstors s chaged. Ths yelds dfferet I-V characterstcs. The dmeso L-X reresets a sze of N+ dffuso. Ths dffuso chages the cocetrato N-well rego. Usually the hgher s X+L, the hgher s holdg voltage. Formula (1) determes a latch-u codto [2]. β β 1 (1) β ad β are the curret gas of the NPN ad PNP trasstors. However, the collector of oe s the base of the other. Therefore, t s ot ossble to use the dscrete β whe comutg Equato (1). The llustrato Fg.5 troduces a tycal behavour of LVTSCR as the fucto of szes L ad X. It s evdet that the hgher s sze L, the hgher are holdg voltage ad ON resstace. The trgger voltage s almost costat. The.5µm CMOS techology rovdes a trgger codto at 14.9V. N-tye LVTSCR I-V characterstcs Fg. 3: Cross secto of the LVTSCR structure. The Fg.3 shows the LVTSCR structure of a covetoal rmary ESD rotecto. Fg.4 llustrates a crcut scheme of the structure. Curret (A),29 X=1um,L=16um,24 X=1um,L=18um X=14um,L=22um,19 X=22um,L=36um,14 X=14um,L=48um,9 X=14um,L=68um,4 -, N-tye LVTSCR I-V characterstcs Curret (A) 1,,1,1, X=1um,L=16um X=1um,L=18um X=14um,L=22um X=22um,L=36um X=14um,L=48um X=14um,L=68um, Fg. 4: Crcut scheme ad coecto of the LVTSCR structure. Fg.5: I-V results for.5µm CMOS rocess (TCAD devce smulato). Lear scale s show above, logarthmc scale s show below [4]. The LVTSCR was smulated a TCAD devce smulator to verfy declared erformace [2, 4]. The ISSN: Issue 8, Volume 5, August 28

3 LVTSCR structure s ot adjustable for hgher holdg voltages (for examle to rotect 1V, 15V, 3V as a suly clam). The reaso s the grouded MOS gate whch sets the trgger ad the holdg voltage level close to the MOS breakdow. Temerature(K) 11, 1, 9, 8, 7, 6, 5, 4, Thermal-voltage deedece for N-tye LVTSCR 3, PsubNwell3,X=1um,L=16um PsubNwell4,X=1um,L=18um PsubNwell5,X=14um,L=22um PsubNwell6,X=22um,L=36um PsubNwell7,X=14um,L=48um PsubNwell8,X=14um,L=68um Fg. 6: Smulated thermal-voltage deedece of the LVTSCR structure. But accordg to the Fg.6 s ossble to say that the LVTSCR structure has bg robustess agast secod destructve breakdow. The Fg.6 shows smulato results of the thermal-voltage deedece. We ca see that the thermal breakdow starts at 85 K. Ths ca be also see Fg.7 ad Fg.8. The fgures show the smulato results from the HBM test ad there s a comarso of the LVTSCR structure wth covetoal lateral SCR., Temerature (K) HBM test for LVTSCR -1,E-7,E+ 1,E-7 2,E-7 3,E-7 4,E-7 5,E-7 Tme (s) Maxmum temerature (K) Average temerature (K) Fg. 7: The smulated HBM test at the LVTSCR structure., Temerature (K) HBM test for lateral SCR -1,E-7,E+ 1,E-7 2,E-7 3,E-7 4,E-7 5,E-7 Tme (s) Maxmum temerature (K) Average temerature (K) Fg. 8: The smulated HBM test at the covetoal lateral SCR structure. It s evdet that the LVTSCR structure s more effectve tha LSCR esecally whe usg advaced CMOS rocesses. However, due to ts hgher voltage lmtato ad trgger voltage adjustablty lmtato the ew structure called Varable lateral Slco Cotrolled Rectfer was develoed to mrove these features. 3 Varable lateral Slco Cotrolled Rectfer The Varable lateral Slco Cotrolled Rectfer s a structure that eables tug of ts erformace accordg to the requremets. Frst of all focusg o the semcoductor hyscs s eeded. The coductvty of a semcoductor σ s gve by: σ = q µ + qµ (2) where µ ad µ are the electro ad hole mobltes ad ad are the electro ad hole cocetratos, resectvely. q = 1,62 x 1-19, C s the electroc charge, ad are gve by the equatos: = = ( ψ φ) q ex kt (3) ( φ ψ ) q ex kt (4) ψ ad Ф are the otetals corresodg to the Ferm eergy, E F ad the Ferm eergy for the trsc semcoductor, E, resectvely. ISSN: Issue 8, Volume 5, August 28

4 Hece, Φ=-E F /q ad ψ=-e /q s the trsc carrer cocetrato gve by: = N C N V Eg ex (5) 2kT where N C ad N V are the effectve desty of states the coducto ad valece bads, resectvely. For slco we get: = 1, T Eg ex 2kT (6) I N-tye resstors at low jecto curret levels, the curret desty s gve by: J = J = N qµ E = N qv (7) B As the hole curret s eglgble, N B s the backgroud dog cocetrato ad E s the electrc feld, v d = µe s the drft velocty of carrers. As the voltage s creased E creases ad so does J ad the resstor s ohmc, that s, t shows a lear deedece betwee curret ad voltage. As the voltage s rased further the feld creases ad so does J accordace wth Equato (7) utl at E = 1 4 Vcm -1 the electro drft velocty saturates at v s =1 7 cm s -1. Further creasg the voltage serves oly to crease the electrc feld wth o crease J ad sat J = J = N qv (8) J sat s a fucto of the dog cocetrato ad wll ot be observed for ether low N B (<1 14 /cm 3 ) or very hgh dog levels whe N B ~1 2 /cm 3. N-well resstors wth N B ~1 17 / cm 3 wll have J sat ~1 5 Acm - 2, whch traslates to a curret of about 1 ma a 2 µm wde resstor. B s B d Fg. 9: The hgh curret I-V curve for a -tye dffused resstor showg the ohmc ad saturated regos [2]. The hgh curret I-V curve for a 2 µm wde N-well resstor s show Fg.9. As the voltage s creased eve further the saturato rego the E-feld evetually reaches the mact ozato threshold ad holes are geerated. Whe the geerated hole curret becomes large eough to cotrbute to the total curret the voltage decreases ad a egatve resstace or saback characterstc s observed as show Fg.9. A rough calculato of the maxmum voltage across the resstor may be doe by assumg that mact ozato begs at ~15 kv cm -1. The the maxmum voltage for a legth of 2 µm s 3 V. The amout of mact ozato requred to cause saback deeds o N B, whch would fluece the maxmum voltage across the resstor before saback occurs. Saback the resstor could also occur due to the heatg the saturato rego. For more hghly doed resstors, self-heatg s more lkely to result saback tha avalache breakdow. Aalytcal studes ad smulatos have also show that curret costrctos the resstor may occur the egatve resstace rego. It s obvous that the more cocetrated s N or P rego the faster saback occurs. The feature s mortat for desgg structures based o SCR. Cosder the reverse-based PN jucto. The curret through the jucto ca be calculated: I R qadnc N = L N d B V E ex kt g qw + τ e N C N V E g ex 2kT (9) ISSN: Issue 8, Volume 5, August 28

5 B α = A ex (13) E where B =E g /qλ ad λ s the mea free ath of the carrer. E r λ = λ tah (14) 2kT Fg. 1: Curret a reverse-based jucto I R, as a fucto of temerature. The dffuso domated rego where l(i R ) s roortoal to 1/kT s observed at hgher temeratures, ad the geeratodomated rego where l(i R ) s roortoal to 1/2kT s observed at lower temeratures [2]. Fg.1 shows a lot of l(i R ) as a fucto of 1/kT. At low temeratures I R wll domated by the thermal geerato ad shows a sloe of ½. At hgher temeratures, the dffuso curret domates ad I R has a sloe of 1. As the reverse voltage s creased ad the electrc feld across the jucto aroaches 1 5 Vcm -1, the carrers the deleto rego ca mart eough eergy a collso wth the lattce to geerate electro-hole ars, whch become free carrers. These ew carrers tur are accelerated, collde wth the lattce ad create more carrers. The rocess s kow as avalache multlcato. The hole ad electro currets, I ad I, flowg to a hgh feld rego are multled so that the currets extg the rego are: I I = I + α I + α I (1) = I + α I + α I (11) α are the electro ad hole mact ozato coeffcets ad are temerature deedet. Emrc equato for the mact ozato coeffcets for electros ad holes ca be wrtte as follows: α, = A 4 [ 1+ C 1 ( T 3) ] B E ex 2 2 [ 1+ D ( T 3) ] 2 E (12) A =,426 /V, A =,243 /V, B = 4,81x1 5 Vcm -1, B = 6,53x1 5 Vcm -1, C = 3,5x1-4, C = 5,35x1-4, D = 6,86x1-4 ad D = 5,87x1-5 are the coeffcets for electro ad holes: E s Vcm -1. The above equatos ca be smlfed to obta: λ =5A ad E r =5meV are λ ad the otcal hoo eergy, E r, at T = K. A reasoable ft to exermetal results has bee obtaed by usg: ( T ) B α = A ex (15) E Where the coeffcet A remas costat as a fucto of temerature ad the major varato wth temerature s assumed to occur the exoet B (T). The multlcato factor for holes ad electros, M, s a mortat arameter alyg mact ozato models to devce behavor. ( out) ( ) I M = (16) I I (out) ad I () defe the currets at the edges of the deleto rego. For α ~α ~α, M ca be wrtte as 1, = (17) ω 1 αdx M Avalache breakdow occurs at the voltage whe M aroaches fty, that s: ω α = 1 (18) Emrcally, the relatosh betwee M ad the voltage across the jucto V j has bee descrbed the form: 1 M = V 1 j V av (19) ISSN: Issue 8, Volume 5, August 28

6 where V av s the avalache breakdow voltage ad s a fttg arameter ragg from 2 to 6 deedg o the tye of jucto beg cosdered. The crease M wth aled voltage s very shar as V j aroaches V av. Aother aroach s to substtute for α from Equato (15) Equato (17), to gve: M = 1 A 1 B j ex V j (2) The Cross secto of VLSCR s descrbed by the dmesos X, Y ad L, where L reresets the aode-to-cathode sacg ad t affects the base legth of PNP trasstor. The sze Y s the P+ rego exteso ad t chages the base legth of NPN trasstor. Fally, X s the sze of N++ dffuso to chage the trgger voltage. The rcal crcut scheme of ths structure s reseted Fg. 12. The dmesos of the dffuso regos also fluece a value of the P- rego ad the N-rego resstaces whch are llustrated the scheme. The fttg arameters A ~Ax d ad B ~Bx d rovde better emrcal matchg over a rage of V j comared to Equato (19), esecally whe comarg graded ad abrut juctos. As V j aroaches V av, M aroaches, ad Equato (2) ca be wrtte as: V av B = (21) l ( A ) Ths equato ca be used to A ad B f V av s already kow. The oly lmtg factor s the resstace of the eutral regos outsde the deleto rego. The temerature deedece of α s such that as T creases, the mact ozato decreases ad M goes dow whch meas that the avalache breakdow voltage creases wth temerature. To acheve a better holdg ad also trgger voltage adjustablty a varable lateral SCR (VLSCR) was formed N-well. Ths structure utlzes N++ dffuso betwee aode ad cathode to chage the N-rego cocetrato for the trgger voltage tug as was dscussed at the begg the MLSCR [2]. To chage the holdg voltage we must maulate wth the P-rego ad the aode-tocathode sacg as t s show Fg. 11. Fg. 12: Crcut scheme of SCR-based structure termed as VLSCR Maulatg wth the szes X,Y the curret gas of the NPN ad PNP trasstor are chaged the way that was dscussed earler ad t corresods wth the avalache codtos accordg to the equato (21). The Fg 13 resets the smulated I-V characterstcs of the structure. Curret [A],35,3,25,2,15,1,5 Smulato results, VLSCR [P+ aode], L=13,X=1um, Voltage [V] Y=1um Y=6um Y=2um Y=11um Y=3um Y=2,5um Fg.13: Smulated I-V characterstcs.5µm CMOS rocess (TCAD devce smulato). Fg.11: Cross secto of VLSCR Accordg to the grah, the holdg voltage adjustablty s 17 V-31 V ad the trgger voltage ISSN: Issue 8, Volume 5, August 28

7 adjustablty s 25 V - 57 V. Ths behavour s alcable for the hgh voltage suly clams. But the behavour deeds o the P+ aode resstace. If we use a dfferet P+ aode cocetrato we get dfferet I-V characterstcs. The same VLSCR structure but wth a dfferet P+ aode cocetrato s llustrated Fg. 14. Curret [A],1,5 VLSCR, BCMOS 1,5um X=22um, L=26um Y= 4um Y=2um Y=1um Voltage [V] Fg.16: Measuremet results of VLSCR maufactured BCMOS 1.5 µm rocess. Fg. 14: Cross secto of VLSCR wth P++ aode Ths structure settg yelds dfferet voltage levels I-V characterstcs as see Fg.15. I ths case, the used voltage at VLSCR or LVTSCR structures s smlar. Therefore, the coveet P+ aode cocetrato has to be chose. Curret (A),29,24,19,14,9,4 Smulato results, VLSCR, P++ aode -, Y=1um,L=13um,X=1um Y=3,5um, X=1um,L=13um Y=um,L=13um,X=1um Y=um,L=18um,X=1um Y=um,X=1um,L=23um Fg.15: Smulated I-V characterstcs.5µm CMOS rocess (TCAD devce smulato). Fg.16 shows measuremet results of a VLSCR structure whch was maufactured 1.5µm BCMOS techology. It s show that the holdg voltage adjustablty s aroxmately from 2 V to 42 V. Trgger voltage chages from 4 V to 6 V. Fg.17: Cross secto of VLSCR structure maufactured BCMOS A cross secto of a VLSCR structure maufactured BCMOS s show Fg.17. To mrove adjustablty of the holdg ad trgger voltage, t would be coveet ot to use costat X ad L settg. BCMOS techology rovdes a low doed etaxal layer ad therefore the voltage levels of I- V characterstcs are relatvely hgh. I a commo CMOS rocess, the voltage levels are relatvely low ad the ON resstace s better. Fg.18 llustrates a voltage varablty of the VLSCR the.5µm CMOS rocess from the TCAD devce smulator. Curret (A) 1 1,1,1,1 Comarso of dfferet P+ aode cocetratos, TCAD smulato results P++ aode, P+ aode Fg.18: Comarso of dfferet P+ aode cocetrato TCAD devce smulato. ISSN: Issue 8, Volume 5, August 28

8 Also the thermal-voltage deedece was smulated ad the results are show Fg.19. We ca see the smulated erformace s smlar lke at the LVTSCR structure. Ths meas the erformace s qute effectve. The thermal breakdow starts at 85 K deedg o the voltage level. The lower s voltage the hgher temeratures ca VLSCR wthstad. Temerature [K] 11, 7, 3, Thermal-voltage deedece for the (P+) VLSCR, L =13,X=1um, 2, 4, 6, Voltage [V] Nwell_modf1,Y=1um Nwell_modf2,Y=6um Nwell_modf3,Y=2um Nwell_modf4,Y=11um Nwell_modf5,Y=3um Nwell_modf6,Y=2,5um Fg. 19: The smulated thermal-voltage deedece at the low doed VLSCR structure. The same deedece but for the structure wth more cocetrated VLSCR aode s show Fg.2. Here, we ca see aga very smlar results lke at LVTSCR structure, but the VLSCR results have better erformace. Heatg of ths structure s ot as rogressve as at the LVTSCR structure. Temerature (K) 11, 7, 3, Thermal- voltage deedece for the (P++) VLSCR L=13,X=1um, 5, 1, 15, 2, _cotact1,y=1um,l=13um,x=1um _cotact2,y=3,5um, X=1um,L=13um _cotact,y=um,l=13um,x=1um _cotact,y=um,l=18um,x=1um.cotact,y=um,x=1um,l=23um Fg. 2: The smulated thermal-voltage deedece at the hgh doed VLSCR structure. Very mortat are the results from HBM test. (Fg.21, Fg.22, Fg.23) Here, we have comarso of the both VLSCR structures wth the covetoal lateral SCR. The sgfcat advatage of the VLSCR s that the temerature durg HBM test does ot reach as hgh as at the LSCR structure. Also the fallg rogress of the maxmum temerature at the VLSCR s reasoable. The covetoal lateral SCR embodes worse maxmum temerature fallg rogress., Temerature (K) HBM test for lateral SCR -1,E-7,E+ 1,E-7 2,E-7 3,E-7 4,E-7 5,E-7 Tme (s) Maxmum temerature (K) Average temerature (K) Fg. 21: The smulato results of the HBM test for covetoal lateral SCR structure., Temerature (K) HBM test for P+ VLSCR -1,E-7,E+ 1,E-7 2,E-7 3,E-7 4,E-7 5,E-7 Tme (s) Maxmum temerature (K) Average temerature (K) Fg. 22: The smulato results of the HBM test for the low doed VLSCR structure., Temerature (K) HBM test for P++ VLSCR -1,E-7,E+ 1,E-7 2,E-7 3,E-7 4,E-7 5,E-7 Tme (s) Maxmum temerature (K) Average temerature (K) Fg. 23: The smulato results of the HBM test for the hgh doed VLSCR structure. ISSN: Issue 8, Volume 5, August 28

9 4 Cocluso The Varable lateral Slco Cotrolled Rectfer seems to be useful the hgh voltage tegrated crcuts but eve low voltage alcatos. The sgfcat advatages of ths structure are holdg voltage adjustablty ad trgger voltage adjustablty. That meas the desger ca set the layout dmesos exactly accordg to the requred ESD rotecto erformace. The ew VLSCR structure ca be formed CMOS rocess as was smulated or eve BCMOS rocesses as was maufactured ad measured. We ca see the erformaces are very smlar eve we used dfferet techology. Also other verfcatos were doe ad are commeted above the text. The thermal-voltage deedece embodes suffcet behavour. Ad the results from the smulated HBM tests roclam good robustess ad effcecy of the ew VLSCR structure. The VLSCR structure s coveet for low voltage alcatos CMOS rocess but eve for hgher holdg voltages BCMOS rocess. I the ESD rotecto desg the VLSCR ca form a suly clam or a rmary ESD rotecto. The layout examle of the VLSCR Smulato results, VLSCR [P+ aode], L=13,X=1um Curret [A],35,3,25,2,15,1,5, Voltage [V] Y=1um Y=6um Y=2um Y=11um Y=3um Y=2,5um Fg. 24: Smulated I-V characterstcs.5µm CMOS rocess (TCAD devce smulato). The Fg. 24 shows adjustablty of the holdg ad trgger voltages smulated CMOS rocess. The Fg. 25 shows the adjustablty of the same structure maufactured BCMOS.,1 VLSCR, BCMOS 1,5um X=22um, L=26um Curret [A], Voltage [V] Y= 4um Y=2um Y=1um Fg. 25: Measuremet results of VLSCR maufactured BCMOS 1.5 µm rocess. Fg. 26: Layout examle of the VLSCR structure CMOS rocess. structure CMOS rocess s show Fg.26. Postve features ad good erformace of the VLSCR structure eable to use ths kd of ESD rotecto commercally. ISSN: Issue 8, Volume 5, August 28

10 Ackowledgemet: The authors would lke to thak Deartmet of Mcroelectrocs at Bro Uversty of Techology for the research suort realzed by research la MIKROSYN. Refereces: [1] A.Chatterjee,T. Polgree, A low-voltage trggerg SCR for o-ch rotecto at outut ad ut ads Elec.Dev.Lett., EDL-12, 21-22, [2] A.Amerasekera,Ch. Duvvury,ESD Slco Itegrated Crcuts. New York: Joh Wley ad Sos, 22 [3] Steve H. Voldma,ESD Crcuts ad Devces. New York: Joh Wley ad Sos, 26 [4] P. Betak, V. Musl, Sa-back characterstcs tug of SCR-based semcoductor structures.i WSEAS Trasactos o Electrocs 27(Secal Issue: Itegrated Crcut Desg), 4(9) ISSN ISSN: Issue 8, Volume 5, August 28