ISSN (Print), ISSN (Online) Volume 5, Issue 1, January (2014), IAEME AND TECHNOLOGY (IJARET)

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1 Iteratoal INTERNATIONAL Joural JOURNAL of Advaced OF Research ADANED Egeerg RESEARH ad Techology IN ENGINEERING (IJARET), ISSN (Prt), ISSN (Ole) olume 5, Issue, Jauary (4), IAEME AND TEHNOLOGY (IJARET) ISSN (Prt) ISSN (Ole) olume 5, Issue, Jauary (4), pp IAEME: Joural Impact Factor (3): (alculated by GISI) IJARET I A E M E MULTI-INPUT QUASI-FLOATING GATE MOSFETS WITH ANALOG INERTER USED IN IRUITS S.K Bso, G. Dev ABSTRAT The multple-put floatg gate trasstors were used to smplfy the desg of multple valued logc. The Quas-floatg gate ode have a well defed D operatg pot. The mult-put quas-floatg gate s used for low voltage applcatos because ts effectve threshold voltage wll be cotrollered to a low value. Keywords: Quas-floatg gate, mult-put quas-floatg gate, aalog verter.. INTRODUTION The floatg gate MOS trasstor s geerated by formg a addtoal coductve layer betwee cotrol termal ad chael solated from evromet called floatg gate []. Multple-put floatg gate MOS trasstor s a floatg gate trasstor wth multple cotrol gate. The put cotrol gates are capactvely coupled to the floatg gate [8,9]. Floatg gate s cotactg wth the chael through the capacty of oxde layer ad wth source, dra ad bulk. The values of these capactes deped o the area of put gate, floatg gate ad cheel as well as o thckess of oxde layer [5,6]. The whole MIFGMOS trasstor made o semcoductor. The ma goals are to release the tradtoal sem-floatg desgs from recharge mode ad to mplemet cotuous mode. Quas floatg gate ca compute multple valued sgals ad obta hgher frequeces [,,3,4]. The aalog verter s a key elemet multple valued logc. The trasfer characterstc of the aalog verter s determed by capactor dvso factor K = ad out = dd Total where ad out are the voltages o the put ad output termal ad dd s supply voltage. 38

2 ISSN (Prt), ISSN (Ole) olume 5, Issue, Jauary (4), IAEME II. MULTI INPUT QUASI FLOATING GATE Sce Quas floatg gate ode have a well defed D operatg pot ad ths techque s used for low voltage applcatos, so that mult put QFG ca compute multple valued sgals ad obta hgher frequeces. To operate the fucto of MOS trasstors at the output of verter, the gate termals of verter must be based through the D supply voltage ad that wll be provded through the couplg capactors gb ad gb' ad hece, Quas floatg MOS gates are proposed to provde a D shft to the combed A sgal. The quas floatg MOS gates are operatg at +5v or -5v depedg o -type ad p-type MOS gates. Ths supply voltage or some porto of supply voltage may pass through the chael from source to dra or dra to source depedg o -type ad p-type MOS gate. The age resstors ad the parallel capactors are operate such a maer that the combed A sgals ca pass through the capactors ad D sgals ca block through the capactors the Quas floatg MOS gates so that the D shftg o postve sde or egatve sde of the combed A sgal ca be doe depedg o types of MOS gates. The shftg of A sgals are requred to oly provde the debasg to the gate termals of MOS verter ad that s ot drectly provded at gate termal, but through the couplg capactors whch ca store the D voltage due to hgh mpedace ad pass the A sgal wthout shft due to low mpedace. The couplg capactors are D block capactors.e. D sgals, f=hz. X c = = = Ω (Ope crcut path) ωc πfc ad A sgal, f = very hgh = Hz X c = = = Ω (Short crcut path) ωc πfc that s the couplg capactors are short crcut paths. At put sde termals the capactors are provded to pass the hgh frequecy sgals oly ad f ay D sgal or low frequecy sgals accommodate wth the orgal sgals that ca be ullfy ad pure form of hgh frequecy sgals ca easly pass through the capactors. The combatos of sgals are geerated at the ode pot whch the passes through the quas floatg MOS gates ad the MOS verter operato obta. 39

3 ISSN (Prt), ISSN (Ole) olume 5, Issue, Jauary (4), IAEME =,, 4, 5 3,, 6 ds, ' =,,,, ( wth R ds ( wth R qfg qfg R L mos ), gb p mos ), ' ( at the verter ) gb sd ( at the verter ) ( at the output ) Load Re ss ta ce at Output III. SIMULATION AND MODEL where QFG total = = = + + GS Total + Total + GB + ' ad = ( + GSS + D + GBB ) QFG QFG total = = + total + Total GSS + D + GBB = Total ' = ' ' + GSS + D + GBB ' total + ' = Total where, ' " total = = GS GB GS th ' ' ad = ( ' ' + GSS + D + GBB ) ' total = It s Ohmc mode or trod rego that s > ad < ( ) I ω = µ ox L ( ) QFGS th Total QFGS th.5 st base bad sgal.4 d base bad sgal Fg. Fg. 4

4 ISSN (Prt), ISSN (Ole) olume 5, Issue, Jauary (4), IAEME.3 3rd base bad sgal x -7 omposed base bad sgals wth capactors,"" Fg. 3 Fg Net output due to,,3,"" -4.4 qfg sgal s s Fg. 5 Fg. 6. 4th base bad sgal. 5th base bad sgal Fg. 7 Fg. 8 4

5 ISSN (Prt), ISSN (Ole) olume 5, Issue, Jauary (4), IAEME.3 6th base bad sgal 4 x -7 omposed base bad sgals wth capactors,"3". 3. a m plt ud e v o lt Fg. 9 Fg. 6 qfg sgal Fg. Fg. 8.6 x -3 Dra to source saturato curret,ids" -.8 Dra to source saturato curret,ids" urret ma urret ma oltage x- axs,qfg -.9 oltage x- axs,qfg Fg. 3 Fg. 4 4

6 ISSN (Prt), ISSN (Ole) olume 5, Issue, Jauary (4), IAEME.86 oltage across load,out -.8 oltage across load,out urret ma urret ma oltage x- axs,qfg oltage x- axs,qfg Fg. 5 Fg. 6 I. ONLUSION I ths paper we have preseted a ew mult-put Quas floatg gate wth aalog verter used crcut. It offers better frequecy respose wth larger bad wdth ad large age resstace eeds less chp area as compared to ts multple put floatg gate techque. REFERENE [] J. Ramrez Agulo,.A. Urqud, R.G. arvajal ad F.M. havero, ery low-voltage aalog sgal processg based o quas-floatg gate trasstor, IEEE, J. Sold State rcuts, 4, 39, [] I. Seo ad R.M. Fox, omparso of quas/pseudo floatg gate techques ad low voltage applcato Aalog Iteger crcuts sgal process, 6, 47, [3] A. Torralba, J. Gala,. Luja Martez, R.G. arvajal, omparso of Programmable lear resstors based o quas floatg gate MOSFETs Proceedgs of IEEE. Iteratoal symposum o crcuts ad systems, 8, Washgto, USA, pp [4] R. Gupta, S. Sharma, oltage cotrolled resster usg quas-floatg gate MOSFET 3, 7(), 6-5. [5] K. Ramesh, S.K. Dash, G. Dev, omparso of floatg gate ad pseudo floatg gate techques IJAIEM, ol., Issue, Nov. 3. [6] H. Guderse, Y. Berg, Max ad M fuctos usg mult-valued recharged sem-floatg gate crcuts.: IEEE, ISAS 4, ol. II, [7] A. Suadat, T. Thogleam,. Kasemsuwa, Quas-floatg-gate Iverter-based class-ab Lear Tras coductor for low voltage Applcatos, Iteratoal coferece o crcuts, sytems ad smulato, Sgapore, ol-7 (), -6. [8] L. Topor Kamsk, P. Holaj, Multple put floatg gate MOS trasstor Aalogue electroc crcut. Bullet of polsh Academy of Scece, ol. 5, No. 3, 4. [9] S.K. Bso, G. Dev, Mult-put Mult Pseudo Floatg Gates used crcuts, IJEAT, ol.3, Issue-, Oct-3. [] D. Kahg, S.M. Sze, A floatg-gate ad ts applcato to memory devces, The Bell System Techcal Joural, 46(4): 88-95, 967, IEEE stadard deftos ad characterzato of usg floatg gate semcoductor arrays, Feb

ISSN 976 648(Prt), ISSN 976 6499(Ole) olume 5, Issue, Jauary (4), IAEME AUTHOR S INFORMATION Sul Bso s studyg for hs Ph.

He s a Assocate Professor of ENT departmet Orssa Egeerg ollege, Odsha. Dr. Gayatr Dev heads the PG departmet of computer scece ad egeerg at Ajay Bay Isttute of Techology of Odsha.

7 ISSN (Prt), ISSN (Ole) olume 5, Issue, Jauary (4), IAEME AUTHOR S INFORMATION Sul Bso s studyg for hs Ph.D the feld of Neural etworks Utkal Uversty, Hs research actvtes ad terest clude LSI realzato of Neural etworks ad aalogue tegrated crcuts ad systems. Bso receved the Egeerg degree from Utkal Uversty. He s a Assocate Professor of ENT departmet Orssa Egeerg ollege, Odsha. Dr. Gayatr Dev heads the PG departmet of computer scece ad egeerg at Ajay Bay Isttute of Techology of Odsha. Her curret feld of terest MOS tegrated crcuts ad systems ad applcato of Neural Networks. Dev receved PG degree Math from Utkal Uversty ad egeerg degree (B.Tech ET ad M.Tech S) from Rastha Deemed Uversty ad Ph.d & D.Sc degree from Utkal Uversty of Odsha. She s a member of IEEE, Odsha Iformato techology of socety ad Odsha Mathematcal Socety. 44

Research on System-level Calibration of Automated Test Equipment based. Least Square Method

Research on System-level Calibration of Automated Test Equipment based. Least Square Method Research o System-level Calbrato of Automated Test Equpmet based Least Square Method Wag Yog*,,, Zhag Juwe,, Qu Laku,, Zhag Lwe, ad Su Shbao 3 College of Electrcal Egeerg, Hea Uversty of Scece ad Techology,