Long Number Bit-Serial Squarers

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1 Log Number Bt-Seral Squarers E. Chaotaks, P. Kalvas ad K. Z. Pekmestz are th the Natoal Techcal Uversty of Athes, 7 73 Zographou, Athes, Greece. E-mal: lchaot, paraskevas, pekmes@mcrolab.tua.gr Abstract Ne bt seral squarers for log umbers LSB frst form, are preseted ths paper. The frst preseted scheme s a % operatoal effcet squarer tha has the half umber of cells compared to the tradtoal squarers. The secod scheme s a % operatoal effcet squarer. I ths scheme, the umber of the cells rema uchaged compared to other proposed schemes but the umber of the requred regsters s reduced sgfcatly. Both schemes are preseted o-systolc ad systolc form ad are compared agast other squarers preseted the bblography from the aspect of hardare complety.. Itroducto Bt-seral arthmetc s ofte used applcatos lke cryptography, here log umbers computatos are requred, to reduce the rg do to a reasoable level. Squarg s a commo computato cryptography algorthms. The despread use of cryptography today combed th the demad for lo poer devces justfes desg efforts for more hardare effcet mplemetato of ths operato. A bt-seral squarer for usged umbers has bee preseted []. Aother scheme preseted [] has the same hardare complety as that [] but has the addtoal advatage of mmedate respose. A dsadvatage of the above schemes s the lack of systolcty. Systolcty s a very mportat property of bt-seral crcuts operatg o log umbers because the same data put s broadcasted to may cells. Thus, more hardare s requred for drvg the broadcasted les resultg creased combatoal delay. Aother squarer scheme based o a e squarg algorthm s preseted [3]. It s of mmedate respose ad ts hardare complety s comparable to the squarer preseted [] but the applcato of a techque that merges eghborg cells [][] yelds systolc archtectures. I ths paper, a e squarer s proposed based o the scheme preseted [3]. A techque, preseted [6] for usged seral-seral multpler, s appled order to reduce by half the umber of cells. Ths techque uses the same cells to compute both the lo ad hgh order part of the result. The most sgfcat part of the put ord s stored to a eteral shft regster ad he the least sgfcat part of the result has bee computed the crcut s fed th these stored data to compute the most sgfcat part. The proposed squarer s also preseted systolc form. A sgfcat draback of the schemes [] ad [] s that they operates th % effcecy, amely, a umber of zero bts equal to the operad legth must be serted betee successve put ords to obta the full product. Tofold effcecy ad throughput ca be acheved by combg to squarers to operate parallel. A more hardare effcet techque s preseted [3] ad [8]. Accordg to t, at the mddle of the multplcato cycle the most sgfcat part of the result s doloaded carry-save form to a double shft regster. The multpler s free to proceed to the et multplcato hle the most sgfcat part s shfted through a bt-seral adder ad s obtaed bary form. I [3], the above techque s appled to a squarer to acheve % operatoal effcecy. The orgazato of the papers s the follog: I Secto, the squarg algorthm ad the squarer of [3] are preseted. The proposed % effcet scheme s preseted the same secto hle the proposed % effcet scheme s preseted Secto 3.. The proposed % operatoal effcet squarer Cosder a postve teger : = = ()

2 Fgure. The crcut mplemetato of the squarg algorthm for 6-bt data ord legth. Accordg to the squarg algorthm preseted [3] the square s gve by the follog equato: = { + } () = The quatty the above equato s the umber obtaed by trucatg the most sgfcat bts of, amely, j = ad j j= = (3) A crcut mplemetato of the above algorthm for 6- bt data ord legth s sho Fgure. The umber of cells s equal to the data ord btlegth. The quatty s stored progressvely to the ro of delay elemets th eable put R. At the -th Table. Correspodece betee the partal results ad the squarer cells. Cell Clock Result

3 Table. Correspodece betee the partal results ad the squarer cells he the half umber of cells s used. clock cycle the quatty s added alog th the term the cell-. The term s added through the carry put of the Full-Adder cluded the cell. The rght most cell s reduced to a -put multpleer sce t adds oly bt. The cotrol sgal R s a trav- elg oe that eters the crcut at the frst clock cycle of each square operato. Table shos the correspodece betee the partal results ad the cells of the crcut Fgure that adds these results. I ths table e ca see that the cells are uderutlzed because a zero ord s serted be- (a) (b) Fgure. (a) The proposed % operatoal effcet squarer for 8-bt data ord legth osystolc form. (b) The tmg of the cotrol sgals. 3

4 Fgure 3. Applyg the mergg techque to the crcut Fgure. tee successve data ords to obta the most sgfcat part of the result. Table shos that the half umber of the cells ca be used for computg both the lo ad hgh order part of the square by rearragg the partal results. Accordg to ths table, oly the most sgfcat bts of the operad are / volved the computato of the hgh order part of the result. Thus, these bts must be stored order to be reused for the computato of the hgh order part. The proposed scheme that mplemets the above + cells ad dea s sho Fgure a. It has oly the rghtmost of them s reduced to a -put multpleer sce t adds oly the term. Durg a computatoal cycle the crcut performs to depedet computatos. Durg the frst half of ths cycle all the bts of eter the crcut ad the lo order part of the result s computed. After that, the most sgfcat bts of are stored to a shft regster ad reeter the crcut durg the computato of the hgh order part. The delay elemets th the eable put must be reset at the begg ad the mddle of the computato cycle. The tmg of the cotrol sgals s sho Fgure b. The cotrol sgal R s a travelg oe that eters the crcut at the begg ad the mddle of the computato cycle. The sgal R allos the reetrace of the H most sgfcat part of the put data ord. I the crcut of Fgure the term s added through the carry put of the Full-Adder each cell. I the crcut of Fgure ths s ot feasble because the carry from the computato of lo order part of the result must be added durg the computato of the hgh order part. The soluto to ths problem adopted here s the term to be added the eghborg cell the left a clock cycle earler. For eample, accordg to Table, the term must be added cell at clock cycle 9. I the crcut of Fgure, t s added cell at clock cycle 8. At clock cycle 8 the cell- has ot yet start partcpatg the computato of the hgh order part ad therefore the term ca be added. I Table terms are crcles to sho hch cell ad at hch clock cycle each of them s added. I the leftmost cell, cell Fg., here there s o eghborg cell at the left the term s added through the free Full-Adder put. The above soluto requres that both ad + are avalable every cell. The proposed crcut ca be trasformed to systolc form by applyg the mergg techque. Accordg to ths techque to cells are merged to oe cell by drag a vertcal retmg cut betee them ad rearragg the to Full-Adders. Fgure 3 shos the frst step of mergg here the retmg cuts (sho th dashed les) result removg delay (sho th dashed boes) ad sertg e oes to the les of, + ad R. Fgure shos the fal crcut here each merged cell s terally ppeled to avod creasg the combatoal delay.

5 Fgure. The proposed % operatoal effcet squarer systolc form. (a) (b) Fgure. (a) The tmg dagram of a % operatoal effcet squarer (b) The block dagram of the % operatoal effcet square preseted [3]. 3. The proposed % operatoal effcet squarer The tmg dagram Fgure a clarfes the operato of a % effcet squarer. The least ad most sgfcat parts LSB, ad MSB, of the -th square computato are obtaed from dfferet outputs. The computatos of LSP, ad are overlapped ad cosequetly o zero bts are requred betee successve put ords. The squarer preseted ths paper s based o a % operatoal effcet squarer preseted [3] hch operato s clarfed by the block dagram Fgure b The hgh ad lo order parts of the result are receved from the outputs ad H L respectvely. Durg the frst clock cycles of the operato the least sgfcat part of s obtaed bary LSP, form from the output L. At the ed of the -th clock cycle sum ad carry outputs of all the Full-Adders that costtute hgh order part of the result are doloaded to to shft regsters ad the squarer s free to start the computato of LSP, +. After doloadg, the shft regsters cota the most sgfcat part carry-save form. Durg the et cycles, s receved from the output LSP, + L of the squarer ad shfts through the bt-seral adder sho the fgure ad s beg obtaed from the output. H

6 The rght part outputs the loer order bts of LSP, + at L. The left part produces the hgher Fgure 6. The block dagram of the proposed % effcet squarer. Table shos that he a e squarg starts the cells from to are volved the computato of the square after cycles. These dle cycles ca be eploted to empty the left half part of the crcut by sertg zero bts. Cosequetly the left half part of the crcut does ot requre the to shft regsters. The block dagram Fgure 6 shos the structure of the proposed % operatoal effcet squarer. The squarer cossts of to parts. At the frst clock cycles of the multplcato the quatty LSP, s ob- taed from the output. At -th cycle the carry ad L sums of the Full-Adder the rght part are doloaded to the to shft regsters. Durg the et clock cycles the multpler operates as follog: order bts of MSP, ad pass them to the sum shft regster. The cotet of both shft regsters s shfted through the bt-seral adder producg the loer order bts of at H. Durg those clock cycles the cotrol sgal R solates the left part from the e values of that eter the squarer. Durg the last clock cycles the most sgfcat bts of ad the LSP, + ad are produced. A crcut mplemetato of the above scheme s sho Fgure 7. The cotrol sgal Q s actvated at the -th clock cycle of the squarg operato ad doloads the carres ad sums of the rght stage ad sets the JK flpflop hch tur actvates the sgal R. The sgal R s deactvated after clocks. Applyg the mergg techque as the proposed squarer Fgure e obtaed the proposed % operatoal effcet squarer systolc form sho Fgure 8. The retmg serts delay elemets to the le of the cotrol sgal R that s used for doloadg the hgh order part of the result. Thus, Q s a travelg oe that eters the squarer at the frst clock of each (a) (b) Fgure 7. (a) The crcut mplemetato of the proposed % effcet squarer for 6-bt data ord legth. (b) The crcut of the cell. 6

7 (a) (b) (c) Fgure 8. (a) The crcut mplemetato of the proposed % effcet squarer systolc form for -bt data ord legth (b) The crcut of the cell (c) The crcut of the rghtmost cell (cell ). operato ad the sums ad carres each cell are doloaded progressvely. I the merged cell, e have to doload to sums ad to carres from the to Full- Adders. Due to the fact that the cell s terally ppeled to addtoal clock cycles are requred for doloadg. These cycles are created by sertg to zero bts betee successve put data ords. The detaled descrpto of the cotrol sgals s gve [3] takg to accout that the rght part of the crcut s the same as the crcut preseted [3].. Comparso of the proposed squarers th other schemes I order to evaluate the effcecy of the proposed schemes e compare them th the squarer preseted [] ad [3]. The results are preseted Table 3. All the schemes compared ths table have the same combatoal delay. Therefore, oly the hardare complety s cluded the table. As far the % operatoal effcecy s cocered, Table 3 reveals that the proposed systolc ad osystolc squarers requres about % ad 3% less 7

8 Table 3. Comparso betee the proposed scheme ad the squarers preseted [] ad [3]. Multpler Total hardare Complety for put data ord legth equal to Hardare complety trasstors for =6 Squarer preseted []. ( ) D* + ( ) FA+ ( ) S + AND 3 Squarer preseted [3] (Fgure). D* + ( ) D+ ( ) DE+ ( ) FA+ S+ ( ) AND 8 Proposed % effcet osystolc squarer (Fgure a). 3 7 D* + D+ DE + FA S + ( + ) AND Proposed % effcet systolc D* ( ) squarer (Fgure ). + D+ DE FA S + AND % effcet o-systolc ( ) D* + ( 3) D+ ( ) DE+ FA+ ( 3 ) S+ ( 63 ) AND squarer preseted [3] Proposed % effcet osystolc squarer (Fgure 7). ( + ) D* + ( 3+ ) D+ ( ) DE+ FA+ ( ) S+ ( 8 ) AND + JK % operatoal effcet systolc D* + ( ) D+ ( ) DE+ FA+ ( ) S+ ( 3) AND squarer preseted [3] Proposed % effcet systolc D * D ( ) DE FA S ( 3) AND JK square (Fg. 8). D:-bt regster (8 trasstors) D*:-bt regster th sychroous reset put ( trasstors), DE:-bt regster th eable put ( trasstors), S: put stch (6 trasstors) FA: Full-Adder (6 trasstors) AND :-put AND gate ( trasstors) (6 trasstors) JK:JK flp-flop ( trasstors) [9] hardare tha the correspodg squarers [] ad [3] respectvely. As far the % operatoal effcecy s cocered the proposed systolc ad osystolc scheme requres % less hardare tha the correspodg schemes [3].. Cocluso Ne bt-seral squarers for usged umbers are preseted ths paper. For ther mplemetato to techques are used hch lead to hardare reducto. Accordg to the frst of them oly the half umber of squarer cells s requred because they are reused for the computato of the lo ad the hgh order part of the result. Ths techque leads to very hardare effcet crcuts. The secod techque s appled to % operatoal effcet squares ad reduces by half the legth of the double shft regster that s used for doloadg the most sgfcat part of the result. Ths techque ca lead to sgfcat hardare reducto case of log umber squarers. 6. Refereces [] L. Dadda Squares for Bary Numbers Seral Form 7th IEEE Symposum o Computer Arthmetc Proceedgs, Jue 98, pp [] Paolo Iee ad Marc A. Vredaz Bt-Seral Multplers ad Squarers IEEE Trasactos o Computers, v.3., December 99, pp.-. [3] K.Z. Pekmestz, P. Kalvas ad N. Moshopoulos, Log usged umber systolc seral multplers ad squarers, IEEE Crcuts ad Systems II:, vol. 8, o 3, Mar., pp [] A.S. Ashur, M.K Ibrahm, ad A. Aggou, Systolc dgt-seral multpler, IEE Proc.- Crcuts Devces & Systems, vol. 3, Feb 996, pp. -. [] C. Carascos, K. Z. Pekmestz, A class of systolc btseral multplers, Iteratoal Joural of Electrocs, vol. 76, 99, o 3, pp [6] A. Aggou, A. Ashur ad M.K. Ibrahm, Area-tme effcet seral-seral multplers, ISCAS -IEEE Iteratoal Symposum o Crcuts ad Systems, May 8-3,, Geeva, Stzerlad. pp [7] G. Eve, To s complemet ppele multplers, Itegrato, the VLSI joural, o, 997, pp [8] K.Z. Pekmestz ad P. Kalvas, Costat Number Seral Ppele Multplers The Joural of VLSI Sgal Processg- Systems for Sgal, Image, ad Vdeo Techology, Kluer Academc Publshers, o. 6, November, pp [9] N. Waste, K. Eshragha, Prcples of CMOS VLSI desg, Readg, MA: Addso- Wesley, 99. 8

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