Implementation and Applications of CORDIC Algorithm in Satellite Communication

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1 NCC 9, Jauary 16-18, IIT Guwahat 118 Implemetato ad Applcatos o Algorthm Satellte Commucato Satsh Sharma 1, Sul Kulkar ad P.Lakshmarsmaha 3 Dgtal Systems Group, ISRO Satellte Cetre, Arport Road, Baagalore-5617, Ida 1 Dgtal Systems Group, ISRO Satellte Cetre, Arport Road, Baagalore-5617, Ida Dgtal Systems Group, ISRO Satellte Cetre, Arport Road, Baagalore-5617, Ida 3 Emal: {satsh@sac.gov. 1, kulkar@sac.gov., vharam@sac.gov. 3 } Abstract stads or COrdate Rotato DIgtal Computer, s a versatle algorthm, wdely used or VLSI mplemetato o dgtal sgal processg (DSP) based commucato systems. Ths paper presets the use o satellte commucato systems. Speccally, Dgtal Dow Coverter (DDC), Drect Dgtal Frequecy Sytheszer (), ad use o dgtal modulator ad demodulator has bee explaed. The algorthm ad ts applcatos are rst realzed o System Vue sotware tool ad the desgs are coded VHDL. Apart rom the mplemetato aspects, paper presets ew results regardg the umber o braches requred or computato. The paper also aalyzes the perormace o based DDC ad o the bass o hardware requremet. The system s mplemeted o XILINX FPGA platorm ad tested real tme or ts perormace Idex Terms Dgtal dow covertor, Frequecy sytheszer, Sgal processg, Satellte commucato. S I. INTRODUCTION atellte commucato systems, ow days gog through a seres o rapd chages terms o modulato techques ad mplemetato. More & more DSP algorthms are used to crease the perormace o the system. Thus, there s a creasg eed or the ecet mplemetatos o complex arthmetc operato requre to, realze these algorthms. Amog the hardware-ecet algorthms, s a class o teratve solutos or trgoometrc ad trascedetal uctos that use oly shts ad adds to perorm. Ths algorthm s called, was rst troduced by Jack E Volder s a arthmetc algorthm wdely used the computato o elemetary uctos ad dgtal sgal processg applcatos, partcularly where large amout o rotato operatos are ecessary. It calculates the trgoometrc uctos o se, cose, arctaget, magtude ad phase, to ay desred precso. It ca also calculate hyperbolc uctos. Apart rom these basc realzato ca be used to mplemet varous trasorm lke Dscrete Cose Trasorm (DCT), Hlbert trasorm ad Dscrete Fourer trasorm (DFT). works o the bass o teratve rotato o a twodmesoal vector usg oly add ad sht operatos. The DSP based commucato system mplemetato usg s more hardware ecet tha covetoal as does t requre ay multpler ad accumulator. Wth the dgtal realzato o the system, we ca optmze the commucato system at algorthm level plus at mplemetato level. The basc theory o s explaed secto II. Secto III deals wth the error aalyss ad data wdth requremets mplemetato ollowed by depth aalyss o based. I secto V, ssues related to FPGA mplemetato o based ad results o real tme testg are descrbed. The use o based other system s dealt secto VI. Secto VII explas about based DDC, ts mplemetato ad real tme spectrum ollowed by cocluso at the ed. II. THEORY I ts most geeral orm [1], the teratve equatos ca be descrbed as X + 1 = X m. Y. d. (1) Y 1 = Y X. d. () where d = Z = Z dα (3) +1 α = ta -1 ( - ) Z <, +1 otherwse ad 1 or crcular co-ordate system m = or lear co-ordate system -1 or hyperbolc co-ordate system Varables X ad Y represet the vectors ad Z s the agle accumulator varable, whch keeps track o the agle that already

2 NCC 9, Jauary 16-18, IIT Guwahat 119 bee rotated. Varable d, decdes the drecto o ext rotato ad the m speces the workg co-ordate system. α s the agle that the vector wll be rotated by durg the th terato. X Y Z Cell # α A. Modes o operato operates two mode vectorg mode ad rotato mode. I vectorg mode the tal vector s rotated to alg t alog X-axs. Ths mode s used or calculato o Arc ta. Iput s X ad Y varable ad output comes o Z. I rotato mode, the agle accumulator s talzed wth the desred rotato agle. The rotato decso at, each terato s made to dmsh the magtude o the resdual agle the agle accumulator. The decso s thereore based o the sg o the resdual agle ater each step. The equato (1), (), ad (3) provde ths result x y [ x cos z y z ] = A (5) s [ + z = A y cos z x s ] (6) z = (7) A = Π 1+ (8) Where A s ga. B. Archtecture Based o the mplemetato o equatos (1), (),(3), there are two archtectures [], seral ad parallel. I our desg we have chose parallel mplemetato, because o the requremet o hgher speed whch s supported by the parallel archtecture wth pealty o more hardware. Seral archtecture has a advatage terms o hardware ececy but t caot work at hgher speed. I parallel archtecture each, terato has oe ut. Oe ut structure s show g.1. III. ERROR ANALYSIS, CHOOSING NUMBER OF ITERATIONS AND DATA PATH WIDTH I applyg crcular-mode to ay applcato, t s crucal to uderstad how seemgly depedet parameters ca aect each other. Frst, t s ecessary to determe how much teratos are ecessary to properly resolve a rada agle b ractoal bts. Assumg that MSB bt s or sg. The ut the least precso (ulp) -b the agle represetato s meagul oly whe t ca be resolved by the terato. That s, at the al terato where = -1, ad s umber o teratos. α -1 should be less tha or equal to -b. Ths esures that the al error agle s less tha -b. The value α = arcta ca be Clock Cell # X 1 Y 1 α 1 Latch or ppelg data x y z q. y. - q = sg(z ) - q. x. - x +1 y +1 z +1 Latch or ppelg data Fg. 1. Parallel archtecture. approxmated as - or large values o. Thereore, -(-1) should be less tha or equal to -b. So, the mmum s b+1, whch s the mmum umber o teratos to correctly resolve the gve agle. I most applcatos, however, the agle s gve a ormalzed ormat such that π π, s scaled to 1 1, because agle accumulator overlow s awkward to deal wth the rada ormat. Whe the ormalzed ormat s used, the agle table should also cota ormalzed etres. Suppose the agle s gve by b ractoal bts. The, the ormalzed agle s ulp s -b ad t should be resolved by -1. b α 1 But, 1) 1) arcta( ) α 1 = π π 1) Thereore, b π Ths meas that the mmum s b. Fally, teratos are to be made, the data path wdth w should be at least 1 (ractoal). Ths s because, or teratos, the largest sht s 1, ad oly whe w 1, ca the largest sht cotrbute to the terato. IV. BASED I satellte commucato systems, requecy sytheszer ds applcato demodulator, PLL loop ad modulator or geeratg se & cose carrer wave. Covetoally Dgtal cotrolled oscllator () ollowed by the ROM look up table are used to geerate the se / cose wave orm. The major dculty wth ths approach s that the sze o the ROM table α

3 NCC 9, Jauary 16-18, IIT Guwahat 1 creases expoetally wth the wdth (.e., the resoluto) o the output. Eve though there have bee several techques proposed to mtgate ths problem, whch bascally partto the ROM table to reduce the sze, the expoetal relatoshp stll perssts ad a resoluto hgher tha 1 bts s curretly cosdered mpractcal. Usg a arthmetc ut, s a alteratve approach that has bee gettg atteto recetly. Especally the algorthm whch has bee domat ths approach because t oly requres sht-ad-add operato whle other approaches based o uctoal approxmatos geerally volve more complcated arthmetc operato such as multplcato. The geeral archtecture o wth /ROM look up table s show g.. The requecy output, system clock SYS, requecy cotrol word K, ad umber o phase accumulator bts N, are related as [3] SYS * K = (9) N The algorthm s used rotato mode or calculato o s ad cose agle. The put to the equato s the agle or whch se ad cose has to be calculated. Settg y compoet o the put vector to zero equato (5) ad (6) reduces the rotato mode to x y = = A. x. cos z A. x. s z caot be accommodated bts. Thereore, maxmum umber o teratos whch t ca go up to wll be (-) ot. We have desg ad smulated the or (-) teratos ad teratos but we dd t d ay sgcat mprovemet the output. Beyod (-) teratos the value o ta -1 ( - ) wll be sged teger ormat. Agle Mappg s doe to map each degree to ts correspodg value accordg to the umber o bts take. Thereore 18 represets = -1, The 1 wll be equal to ( -1 / 18 ). Hece the agle must be multpled by ( -1 / 18 ). We also used tal ±π/ rotato to crease the rage o the algorthm. The system vue output or 1 KHZ requecy s show g.3 Ater adjustg the parameters, the desg s coded the VHDL ad smulated Model sm sotware. Fally or real tme testg the desg s targeted to the XILINX (xcv3-4g676) FPGA. Table-1 shows the comparso o hardware requremets or ROM look up table. Fg. 4 shows the real tme captured wave orm o osclloscope By settg x equal to 1 / A, the al value o x ad y gves the s ad cose agle o the put agle. V. FPGA IMPLEMENTATION OF BASED Beore mplemetato the desg s smulated system vue sotware. We have desg the system or 14 bt, so al error ( agle) -b ; For bts o Phase accumulator Maxmum multplcad wll be - or ampltude because the multplcad value s more tha ths the ta -1 ( - ) = 45 whch the hghest agle to be represeted Fg. 3. Smulated phase accumulator output wth Se & Cose waveorm o 1 KHz requecy. Clock Phase Se look-up table / D/A covertor Frequecy word Se Fg.. archtecture. lter Fg. 4. Real tme S & Cose waveorm at 1 KHz requecy

4 NCC 9, Jauary 16-18, IIT Guwahat 11. TABLE -I HARDWARE REQUIREMENT COMPARISON OF BASED AND ROM LOOK UP TABLE BASED 1 3 Seral No. From Table-I, t s clear that wth based we ca get more phase resoluto less hardware. The hardware requremet or look up table based crease expoetally. Up to 1 bt phase resoluto lookup table approach s better but beyod that outscore terms o hardware requremet. The mportat perormace parameter or s spurous ree dyamc rage (SFDR). The SFDR s rato o ampltude o the desred requecy compoet to that o the largest udesred requecy compoet the output o. It s expressed as Ap SFDR = log 1 As Where A s the ampltude o the desred requecy compoet p Phase Bts & Phase Resoluto Bts: 1 Phase Resoluto : Bts: 14 Phase Resoluto :.197 Bts: 4 Phase Resoluto :.1 Implemetato Xlx (XCV1-4bg676) Slces used or based 3/14336 (1%) 54/14336 (3%) 841/14336 (5%) Slces used or ROM based 179/14336 (1%) 13/14336 (7%) Not possble ad As s that o the udesred compoet. The SFDR ca be calculated approxmately by exame the spectrum o geerated waveorm. The g. 5 shows the real tme spectrum o 1 MHz se wave. It s clear that SFDR s approxmately 8 db. VI. APPLICATIONS OF IN SATELLITE SUB SYSTEMS The s oe o the requremets dgtal modem desg. Partcular to our satellte system, we are usg BPSK modulato techque, so at trasmtter ed ca be used BPSK modulator as show g.6. Iput data s used to select the phase ad that s added wth the phase o the carrer. Fally phase ormato s coverted to ampltude by. D/A s used to get the aalog output. The system ca be upgraded to M- PSK by sutable selecto o phases. At recever the based ds applcato Costas loop demodulator & Bt sychrozer as show g. 7 & 8. π/ -π/ Modulated put Iput M U X Fg. 6 Dgtal BPSK modulator Based lter Loop lter lter Fg. 7 Costas loop demodulator I Phase Tmg Crcut Carrer S _clock Regster Based BPSK modulated output Hard Decso Loop Flter D/A Smoothg ter Demodulated Md Phase Cos _clock Regster Delay Fg. 5. Real tme spectrum o 1 MHz se wave geerated usg based Fg. 8 I phase / Md phase bt sychrozer

5 NCC 9, Jauary 16-18, IIT Guwahat 1 VII. BASED DDC FOR SATELLITE RECEIVER DDC s oe o the mportat modules o the ay recever system. There are varous algorthm to dow covert the RF put to ay low IF requecy. Oe o the smple methods s the use o multpler. For I-Q demodulato we requre two multpler ad a as show g.9. Istead o usg two multpler & look-up table based, ca be used drectly to dow covert [4] ad geerate I ad Q compoet o the receved put as show g.1. A proto DDC usg, havg 14 terato ad 1 bt ampltude resoluto, s realzed XILINX FPGA. X put o s xed at zero ad at Y, sgal to be dow coverted s gve [5]. RF or hgh IF put s(k) Fg. 9 Multpler based dow coverso X Y Z φ ( k) = (π k) s Q( k) A. s( k).s(π k I( k) A. s( k).cos( π k) Fg. 1 based dow coverso s operated o 1 MHz wth samplg clock o MHz the desg s smulated, systheszed ad real tme tested o the XILINX platorm by gvg a 3 MHz se wave put ad observg output spectrum aalyzer. The SFDR acheved ths desg s apprmately 7 db. The desg ca go up to 15 MHz. Fg.11 shows the spectrum o dow coverted sgal at & 4 MHz. VIII. CONCLUSION I- Compoet at low IF Frequecy Q-Compoet at low IF Frequecy s very versatle algorthm ad just by chagg ew parameters we ca realze may useul ucto. Speccally ths paper, applcatos o algorthm satellte commucato system are aalyzed. The based s s ) Fg.11 Dow coverted output at MHz & 4 MHz. s dealt depth rom cocept to FPGA realzato. The s realzed o XILINX platorm ad tested real tme. Spectrum o output shows a SFDR o 8dB. It was oud that over 1 bt phase resoluto based has advatage terms o hardware o ROM based. We have oud out that case o - teratos are eough stead o. Paper also explaed about based DDC. SFDR case o DDC s 7 db. Apart rom these, applcatos o dgtal modulator, demodulator ad bt sychrozer are also preseted. We have chose parallel archtecture or algorthm mplemetato or all applcato as t provdes advatage terms o speed o operato. The varous applcatos o are smulated, coded VHDL ad real tme tested o XILINX platorm. ACKNOWLEDGMENT Authors would lke to thaks Madur Rao, Shruth H.A, Vashr R ad Vdhya T.P or carryg out the smulatos at varous level o desg & helpg real tme testg o desg. REFERENCES [1] R. Adraka A Survey o Algorthm or FPGA Based Computers Proc. o ACM/SIGDA Sxth Iteratoal Symposum o FPGAs, pp 191-, Feb.1998, Moterrey, CA. [] Herbert Dawd ad Herch Meyr, Chapter 4,Dgtal Sgal Processg or Multmeda Systems, Meyr Syopsys Ic. [3] Bar-Gora Goldberg,Dgtal Frequecy Sythess Demysted : DDS ad Fractoal-N-PLLS, Eagle Rock,VA, LLH Techology,1999 [4] Javer valls, Tr Sasalo, ad A.P.Pascual The Use o Sotware Deed Rados: A tutoral IEEE Commucatos Magaze, pp 46-5, Sept.6. [5] M. Loehg, T. Hetschel, ad G. Fettwes, Dgtal Dow Coverso Sotware Rado Termals, 1 th Europea Sgal Processg Coerece, vol.3,sept Tampere, Flad.

Module 6. Channel Coding. Version 2 ECE IIT, Kharagpur

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