A Parallel-Layered Belief-Propagation Decoder for Non-layered LDPC Codes

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1 400 JOURNAL OF COMMUNICATIONS, VOL. 5, NO. 5, MAY 2010 A Parallel-Layered Belef-Proagato Decoder for No-layered LDPC Codes Ku Guo Yog He ad Shusha Qao Asc ad System Deartmet, Isttute of Mcroelectrocs of Chese Academy of Sceces, Bejg, Cha Emal: {guoku, heyog, qaoshusha}@me.ac.c Abstract I ths aer, we roosed a Parallel-Layered Belef-Proagato (PLBP) algorthm frst, whch makes a breakthrough utlzg the layered decodg algorthm o the o-layered quas-cyclc (QC) LDPC codes, whose colum weghts are hgher tha oe wth layers. Our roosed PLBP algorthm ot oly acheves a better error erformace, but also requres almost 50% less teratos, comared wth the orgal floodg algorthm. The we roose a low-ower artal arallel decoder archtecture based o the PLBP algorthm. The PLBP decoder archtecture requres less area ad eergy effcecy tha other exstg decoders. As a case study, a mult-rate 9216-bt LDPC decoder s mlemeted SMIC 0.13m 1P6M CMOS techology. The decoder dssates a average ower of 87mW wth 10 teratos at a clock frequecy of 83.3 MHz. The ch core sze s 7.59 mm 2,ad the de area occues mm 2. Idex Terms Low-desty arty-check codes, quas-cyclc codes, layered decodg, arallel archtecture, o-layered codes, VLSI I. INTRODUCTION Low-desty arty-check (LDPC) codes, are a kd of lear block codes, whch were frst troduced by Gallager 1962[1], ad were redscovered by MacKay[2] Wth the mrovg techology, LDPC codes ad ther effcet mlemetatos have bee recevg a lot of atteto due to ther excellet error-correctg erformace closg to the Shao lmt. Hece, LDPC codes have bee wdely emloyed most wreless commucato systems, such as IEEE [3], e[4], DVB-S2[5] ad Chese Moble Multmeda Broadcastg(CMMB) [3] stadard. Wth the heret arallelsm the decodg rocess, varous decoder archtectures (fully arallel [7], artally arallel [8], ad comletely sequetally [9]) have bee roosed. Takg both throughut ad hardware cost to cosderato, the artally arallel method s the best choce for most alcatos. Recetly, a growg atteto has bee gve to dfferet schedules of the elaboratos of the Belef Proagato (BP) algorthm to seed u the decoder covergece wth a smaller umber of teratos. So far, there are two ma decodg algorthms for the LDPC codes. The orgal floodg (or TPMP[10]) algorthm udates all the check-to-varable (CTV) messages frst, the all the varable-to-check Mauscrt receved August 27, 2009; revsed December 20, 2009; acceted Jauary 15, (VTC) messages ay terato. Therefore, the estmato of all the varable odes are udated oly oce wth all the eghborg check-to-varable oe terato. O the other had, the layered algorthm [11] breaks u oe terato to several sub-teratos, called layers. The CTV ad VTC messages wll be udated frst oe layer, the the latest messages are used the ext layer, ad so o, layer by layer. Wth more udated estmates, the layered schedule acheves faster coverget rate, ad better error erformace. However, the rows of arty check matrx ca be groued as a layer should have the feature that the layer colum weght s oe at most. So we ca refer to the codes lke these as layered codes, oosto to o-layered codes, whose colum weghts are hgher tha oe wth layers. As the orgal layered decodg algorthm ca cause coflcts whe used o the o-layered LDPC codes straghtforwardly, two dfferet strateges are roosed [12]. But both the strateges are the aroxmatos of the orgal layered algorthm ad oly work well wth a small umber of the overlaed blocks. Whe the umber creases, the error erformace ca get worse ad more teratos are requred for covergece. Aother soluto based o the comutato of a extra varato s reseted [13]. Such comutato allows cocurret udates but requres more memory access or faster clock frequecy. Istead of mrovg the message udatg formulas, [14] roosed a reorderg mechasm for the arty check matrx to reduce the umber of coflcts. However, ths aroach lowers the level of arallelsm ad stll ca ot acheve the same error erformaces as the orgal layered algorthm. I ths aer, we roosed a arallel-layered belef-roagato (PLBP) algorthm. The algorthm avods the coflcts carefully by buldg drect aths amog dfferet layers for every code bt, whe all the layers are rocessed a arallel way. Wth such aths, every varable s able to be udated layer by layer. As a result, the PLBP algorthm ca get the same error erformace ad the same coverget rate as the orgal layered algorthm, o matter how may coflcts aears. Moreover, a low-ower PLBP archtecture s roosed ad mlemeted for 9216-bt LDPC codes CMMB system as a examle usg 0.13m CMOS techology. The remader of ths aer s orgazed as follow. I Secto II, we troduce the two oular decodg algorthms, ad the o-layered QC-LDPC codes. The roosed PLBP algorthm ad ts archtecture are do: /jcm

2 JOURNAL OF COMMUNICATIONS, VOL. 5, NO. 5, MAY demostrated Secto III ad Secto IV, resectvely. The ch mlemetato s show Secto V ad the coclusos are reseted Secto VI. II. LOW-DENSITY PARITY-CHECK (LDPC) CODES The decodg of the LDPC codes s a teratg rocess to refe the Log-Lkelhood Rato (LLR) of the receved bts the codeword, defed as (1), wth x ad y are the orgal codeword ad ts observato resectvely. Whe decodg, the LLRs are roagated ad udated betwee the varable odes ad the check odes the Taer grah [13], utl all the check equatos are satsfed. ( x y 0) LLR x log (1) ( x y 1) A. Floodg decodg schedule Floodg decodg algorthm s the most commo message-roagatg algorthm. I each terato, the udatg floods from oe sde of the Taer grah (check odes) to the other sde (varable odes). As a result, each varable ode s udated oly oce, based o the message from all the check odes coected to t. At the k-th terato, let r m (k) ad q m (k) deote the message from check ode m to varable ode ad the message from varable ode to check ode m, resectvely. Assume N(m) s the set of varable odes coectg to the check ode m ad M() s the set of check odes coectg to the varable ode the Taer grah. Oe terato s comosed of two successve stes as follow. Check ode udatg s the rocess to udate r m (k) searately o sgs ad magtudes: sg r m k sgq m k 1 (2) N m\ r m where k q k N m \ N m \ m x x loge 1 e 1 1 (3) x. (4) There are several low-comlexty aroxmatos of (4). I ths aer, we use the Normalzed M-Sum algorthm wth a ormalzed factor of 0.8 [16]. r k m m m N m (5) \ Varable ode udatg s to geerate (k) by q k 1 q m summg the check message r m (k) from ts eghborg check odes ad the ror message from the chael. qm k rm k (6) mm \ m At the same tme, a refed estmato o the trasmtted bt k s comuted, whch s also referred to as the soft outut: mm k k r (7) B. Layered decodg schedule Oe dsadvatage of the Floodg schedule s ther slow covergece. To mrove the covergece, the layered ad shuffled decodg schedules are troduced, whch slts arty check matrx horzotally or vertcally to several sub matrces, called layers. Therefore, oe terato s broke u to the sequetally sub-teratos of these layers. Wth more tha oce udatg of the varable odes, both the layered ad shuffled decodg schedules requre u to 50% fewer teratos to coverge ad acheve better error erformace tha the orgal floodg schedule. As the horzotal layered decodg s more sutable for the mlemetato of the check odes ut, t s more oular for ractcal mlemetatos. ( ) Let k deote soft outut of varable ode at the -th sub-terato of the k-th terato. As the check odes udatg s followed by the varable odes ( ) udatg every sub-terato, k s udated every ste by (8) ad the value at the last ste (the max-th ste) reresets the soft outut of the k-th terato. k rm k 1 rm k (8) mm \ m Ad the hard decso X k 0, 1, X k m ca be made as follow: k k. (9) max C. No-layered LDPC codes max 0 0 No-layered LDPC codes are a secal kd of QC LDPC codes, whose elemets the base arty check matrces ca be exaded as several cyclc-shfted detty matrces overlaed wth each other. Ths s the case of the codes used CMMB system, as show Fg.1 (a) ad (b), ad all the overlaed blocks are marked wth crcles. Such overlag ca gve rse to the decodg coflcts, whe the layered algorthm ad the artal arallel archtecture are both emloyed. To fgure out the coflct, let C1 ad C2 deote the overlaed blocks. As metoed secto II, the essetal reaso that the layered algorthm has a faster covergece s that the latest message s used by the ext layer whe decodg layer by layer a sgle terato. As the artal arallel archtecture udates all the check odes ad varable odes wth a layer a arallel way, C1 ad C2 have to be rocessed at the same tme ad ether of them s able to beeft from the latest udated messages of each other. So such LDPC codes whch do ot allow the straghtforward mlemetato of the orgal layered decodg, are referred to as o-layered codes. The most oular o-layered LDPC codes are the oes used DVB-S2 system ad CMMB system.

3 402 JOURNAL OF COMMUNICATIONS, VOL. 5, NO. 5, MAY 2010 (a) (b) Fgure 1. Party check matrces of LDPC codes CMMB system: (a) 3/4-rate matrx, (b) 1/2-rate matrx III. THE PROPOSED PLBP ALGORITHM I ths secto, we roose a arallel-layered belef-roagato (PLBP) algorthm for the o-layered LDPC codes. The decodg of ths algorthm s qute dfferet from the orgal layered algorthm, for t uses arallel udatg amog all the layers ad seral udatg wth each layer. Wth such a decodg schedule, a varable ode dfferet layers s udated at dfferet tme, whch meas that the message s able to be udated layer by layer. As a result, the PLBP algorthm ca be emloyed by the o-layered LDPC codes, so as to mrove ther error erformace ad covergece seed just lke the orgal layered decodg algorthm. A. The PLBP algorthm Let us take the LDPC codes for CMMB systems as a examle to exla the detal of the PLBP algorthm. Fg. 2 llustrates message assg routes the PLBP algorthm usg the 33rd colum of the arty check matrx Fg. 1 (a). We deote the overlaed sub-matrces as Layer 4a ad Layer 4b resectvely. As the udatg s rocessed sequetally wth a layer, oe terato s broke u to 256 stes. The oerato sequece of these three layers s descrbed as followg: 1) At ste 0, all the layers udate from the frst row (Row 0). Colum 0 Layer 4a, Colum 138 Layer 4b ad Colum 216 Layer 7 rocess the udatg at the same tme, accordg to (5),(6) ad (8), as show Fg. 2(a). 2) At ste 40, all the three layers are rocessed at Row 40, corresodg to Colum 40 ( Layer 4a), Colum 178 ( Layer 4b), Colum 0 ( Layer 7). As Colum 0 has already bee udated Layer 4a at the ste 0, Layer 7 ca use the latest message from Layer 4a, as show Fg. 2(b). 3) At ste 78, all the three layers are rocessed at Row 78, Colum 78 ( Layer 4a), Colum 216 ( Layer 4b) ad Colum 38 ( Layer 7). Layer 4b ca use the latest message of Colum 216 from Layer 7 whch has already bee udated at ste 0, as show Fg. 2(c). 4) At ste 118, all the three layers are rocessed at Row 118, corresodg to Colum 118 ( Layer 4a), Colum 0 ( Layer 4b), Colum 78 ( Layer 7). As Colum 0 has already bee udated Layer 4a the Layer 7, Layer 4b ca get the latest message from Layer 7. So far, Colum 0 has comleted ts terato wth three udatg (Layer 4a Layer 7 Layer 4b), ad stored the hard decsos Layer 4b, as show Fg. 2(d). 5) As the stes go o, Colum 216 ad Colum 138 also are able to get ther latest messages from other layers, whch have bee udated at the earler stes, as show Fg. 2(e)~(g). 6) At ste 255, all the colums have fshed ther three layered-udatg, but the udatg sequeces are dfferet. Sce the latest messages of all the colums are dfferet layers, as show Fg.2(h), the hard decsos of these colums ths terato are dstrbuted dfferet layers. Such dstrbuto of the 33 rd block colum s show s Table I. The key ot the PLBP algorthm s that each varable ode s udated dfferet layers at dfferet tme. Such dffereces make t ossble to exchage the messages amog dfferet layers. However, there are several sub-matrces the same block colums wth the same shftg factors, whch mles that all the three layers of oe varable ode are udated at the same tme. To solve the roblem, we ca start the terato wth dfferet rows for dfferet layers, whch s equvalet to

4 JOURNAL OF COMMUNICATIONS, VOL. 5, NO. 5, MAY Check odes (a) (b) (c) (d) (e) (f) (g) (h) Fgure 2. The decodg schedule of the 33th block colum addg a offset to the shftg factor of each layer, as show Fg. 3(a) ad (b). The offset values are carefully selected, so that the dfferece of the modfed shftg factors betwee ay two layers s at least four. B. Smulato result Both the floodg ad PLBP algorthms are smulated usg the codes Fg. 1, wth 6-bt quatzed LLRs BPSK modulato mode over AWGN chael. The check odes udatg algorthm s the Normalzed M-Sum for both algorthms. The BER erformace comarso s lotted Fg. 4 (a) ad (c) for 3/4-rate code ad 1/2-rate code, resectvely. The maxmum terato umber s set to 5, TABLE I. UPDATING SEQUENCE AND HARD DECISION DISTRIBUTION OF THE 33 TH BLOCK COLUMN Col.0~137 Col.138~215 Col.216~255 Sequece L4a-L7-L4b L4b-L4a-L7 L7-L4b-L4a Hard Decso L4b L7 L4a

5 404 JOURNAL OF COMMUNICATIONS, VOL. 5, NO. 5, MAY 2010 (a) Fgure 3. (b) The arty check matrces wth offset for the CMMB system: (a) 3/4-rate matrx, (b) 1/2-rate matrx 30 BER Floodg(ter=5) PLBP(ter=5) Floodg(ter=10) PLBP(ter=10) Floodg(ter=20) PLBP(ter=20) Floodg(ter=30) PLBP(ter=30) SNR(dB) (a) 10 0 Average terato umber Floodg PLBP SNR(dB) (b) 30 BER Floodg (ter=5) PLBP(ter=5) Floodg (ter=10) PLBP(ter=10) Floodg (ter=20) PLBP(ter=20) Floodg (ter=30) PLBP(ter=30) SNR(dB) (c) Fgure 4. Average terato umber Floodg PLBP SNR(dB) (d) Error erformace ad covergece seed of PLBP algorthm vs. Floodg algorthm: (a) ad (b) for /-rate codes of CMMB system, (c) ad (d) for /-rate codes of CMMB system.

6 JOURNAL OF COMMUNICATIONS, VOL. 5, NO. 5, MAY Fgure 5. The archtecture of the PLBP decoder 10, 20 ad 30. The fgure demostrates that the roosed the PLBP algorthm acheves much better BER at the same SNR for the same umber of teratos. I artcular, wth 10 teratos, 1/2-rate code at -1.2dB (Eb/No = 1.8dB) ad 3/4-rate code at 1.5dB (Eb/No = 2.75dB), the PLBP algorthm rovdes a order of magtude mrovemet BER. The average umbers of teratos requred to coverge usg both algorthms are lotted Fg. 4(b) ad (d). As show, the PLBP algorthm requres sgfcatly less teratos to coverge. Where some cases t requres close to half the umber of teratos to coverge comared wth the floodg algorthm. Hece, the decoder ower cosumto ca be reduced whe the PLBP algorthm acheves the same erformace as the floodg algorthm. IV. THE PROPOSED ARCHITECTURE The overall archtecture of the PLBP decoder for the LDPC codes CMMB system s show Fg. 5. It maly cotas two edge ode rocessor clusters. The frst oe s the varable ode uts (VNUs), whch geerate the sum of extrsc messages for the eghborg check odes, ad the secod oe s check ode uts (CNUs) whch check the hard decso ad geerate the check message for the VNUs. There are 36 VNUs ad 18 CNUs total. I each VNU, there are oe block of Imem memory ad 3 blocks of Exmem memory. The sgle-ort Imem block s used to store the trsc message from the chael, whle the dual-ort Exmem blocks are used to store the extrsc message from the CNUs. Each memory block assocated wth a address geerator (AG) to rovde readg ad wrtg address. I artcular, the code bts of the CMMB system are ot trasmtted ts atural order as ecoded [3], therefore, a ROM to reorder the outut bts s eeded at the recever, as show Fg. 5. A. The VNU block The VNU archtecture s show Fg. 6(a). Each Exmem blocks storage the extrsc messages for oe of the three layers the same block colum. I ths archtecture, t takes two clock cycles to comlete oe ste metoed Secto III. At each ste, every Exmem block reads out two extrsc messages for the other two layers, ad wrtes oe ew udated message for ts ow layer from the corresodg check odes, o the other had, the Imem block comosed of two sgle-ort memory, rocesses three readg oeratos rovdg a trsc messages for each layer. The three AG geerate three dfferet addresses for the three layers ad cotrol the readg/wrtg oeratos for the memory blocks, as show Fg. 6(b). The address for the memores at ste ca be calculated as addr ( s ) mod 256 ( 1,2,3) (10) s where reresets the shftg factor of the -th cyclc-shfted detty matrx from the to of the block colum. Let v (=1, 2, 3; =0, 1,, 255) deote the varable ode whch s gog to be udated the -th layer at the -th ste ad deote ts corresodg trsc message. Let r j (,j=1,2,3, j) rereset v the extrsc message of the from the j-th Exmem. The message of to the CNUs s deoted as q,whch

7 406 JOURNAL OF COMMUNICATIONS, VOL. 5, NO. 5, MAY 2010 r 11 r 11 r 22 r 12 r 13 r 23 r r 22 X 2 q 22 q 33 X 1 q 11 r 33 r 31 r 32 r 33 X 3 Fgure 6. (a) The archtecture of VNU block: (a) the data ath of the VNU memory blocks, (b) the address geerator for the memory block (b) (a) (b) (c) Fgure 7. The comarso art of the CNU block: (a) 3-ut, (b) 6-ut, (c) 12-ut ca be comuted by (6), ad the ewly udated message of v from the CNUs s deoted as r, whch ca be comuted by (5). Four or three clock cycles (for dfferet code rates) after geerated, s avalable for the q X comutato of usg (9), so s delayed for four or three clock cycles as show Fg. 6(a). B. The CNU block To erform the check ode udatg M-Sum Algorthm, we should search for the mmum ad secod mmum amog the receve data. As demostrated Fg. 7(a), the 3-ut comarso ut (Com3) ca be bult by the 2-ut comarso ut (Com2). Base o the costructo of Com3 ad Com2, the desg of 6-ut comarso ut (Com6) ad 12-ut comarso ut (Com12) ca be realzed herarchal method[17], as show Fg. 7(b) ad Fg. 7(c). It takes 3 clock cycles for 1/2-rate codes ad 4 clock cycles for 3/4-rate codes to comlete the CNU comutato. As show Fg. 3, the dfferece of the shftg factor amog dfferet layers a same block r q colum s more tha 4, so that the messages for the ext layer have already bee reared the Exmem block. V. IMPLEMENTATION RESULTS I order to evaluate the erformace of the roosed PLBP archtecture, we mlemet the mult-rate LDPC decoder for CMMB system SMIC 0.13m 1P6M CMOS techology. The storage elemets are mlemeted by 144 memory baks, whch cosst of 36 sgle-ort ad 108 dual-ort rams. Each of the memory bak has 256 etres, whch oe etry cossts of 6-bt data. To reduce the routg comlexty, we use the checkboard [17] layout scheme to as show Fg. 8, where + reresets the dual-ort memory, - reresets the sgle-ort memory ad O reresets the ROM, whch s used to storage the reorderg dex lst as metoed Secto IV. I order to comare wth other state of art, the ormalzed area ad ower are derved as follows: Area (11) Normalze Area 2 2 code_legth (1 code_rate) techology Power (12) Normalze Power 2 (core_ower_suly)

8 JOURNAL OF COMMUNICATIONS, VOL. 5, NO. 5, MAY TABLE II. OVERALL COMPARISON BETWEEN THE PROPOSED CMMB LDPC DECODER AND THE EXISTING LDPC DECODERS JSSC 06 [18] JSSC 08 [19] JSSC 02 [20] LDPC decoder IP [21] Ths work Code Legth ~ ~ Gates 220(logc) k NA 900k Parallelsm Partal Partal Fully Partal Partal Frequecy(MHz) Iteratos Throughut (Mbs) Area (mm 2 ) (wth dex Rom) Normalzed Area10-3 mm Power (mw) NA 87 Eergy Effcecy (J/Bt/Iter) NA 118 Normalzed Power NA 60 Techology 0.18 m,1.8 V 90m,1.0V 0.16m, 1.5V 0.18 m,1.8v 0.13m,1.2V Rate 8/16:1/16:14/16 1/2,2/3,3/4,5/6 1/2 1/2,2/3,3/4,5/6 1/2, 3/4 Table II shows the decoder mlemetato results comared wth other exstg QC-LDPC decoders. Note that the roosed LDPC decoder s much smaller tha the other research works ormalzed area. Moreover, the ormalzed ower ad Eergy Effcecy are also smaller tha other artal arallel decoder chs. I other words, the roose decoder wth sueror characterstcs of low area cost ad low ower dssato s qute sutable for the wreless commucato systems, esecally CMMB ad DVB system. VI. CONCLUSION As layered algorthm caot be used the decodg of the o-layered LDPC codes, we roosed a arallel-layered belef-roagato (PLBP) algorthm ad ts artal arallel archtecture ths aer. The PLBP algorthm establshes a ath for messages roagatg amog dfferet layers, whch makes every code bt udated layer by layer wthout ay loss error erformace ad covergece seed, comared wth the orgal layered algorthm. Addtoally, the roosed PLBP archtecture s mlemeted for the codes CMMB system as a study case, usg SMIC 0.13m 1P6M CMOS techology. The de area s oly 10.82mm 2 ad the ower cosumto s 87mW at 83.3MHz, whch are both smaller tha the other desgs the ormalzed way. I summary, the roosed PLBP algorthm ad the corresodg archtecture are very sutable for low-ower commucato systems emloyg the o-layered QC LDPC codes. Fgure 8. The layout hoto of the roosed decoder REFERENCES [1] R. Gallager, Low-desty arty-check codes, IRE Tras. If. Theory, vol. 7, , Ja [2] D. J. C. MacKay, Good error-correctog codes based o very sarse matrces, IEEE Tras. If. Theory, vol. 45, o. 3, , Ja [3] IEEE P802.11/D1.05 October 2006, Wreless LAN Medum Access Cotrol (MAC) ad Physcal Layer (PHY) secfcatos Ehacemets for Hgher Throughut (Draft). [4] IEEE e: Ar Iterface for Fxed ad Moble Broadbad Wreless Access Systems, IEEE, [5] Euroea Telecommucatos Stadards Isttute (ETSI). Dgtal Vdeo Broadcastg (DVB) Secod geerato, framg structure for broadbad satellte alcatos; EN V

9 408 JOURNAL OF COMMUNICATIONS, VOL. 5, NO. 5, MAY 2010 [6] GY-T , Moble Multmeda Broadcastg Part 1: Framg Structure Chael Codg ad Modulato for Broadcastg Chael, [7] A. J. Blaksby ad C. J. Howlad, A 690-mW 1-Gb/s 1024-b, rate-1/2 low-desty arty-check code decoder, IEEE J. Sold-State Crcuts, vol. 37, , Mar [8] C. J. Howlad ad A. J. Blaksby, Parallel decodg archtectures for low desty arty check codes, Proc. IEEE ISCAS, vol. 4, , May [9] Z. Cu ad Z. Wag, Area-effcet arallel decoder archtecture for hgh rate QC-LDPC codes, Proc. IEEE ISCAS, , May [10] M. M. Masour ad N. R. Shabhag, hgh-throughut LDPC decoders, IEEE Tras.Very Large Scale Itegrato Systems, vol.11, o.6, Dec.2003 [11] M. M. Masour ad N. R. Shabhag, A 640-Mb/s 2048-bt rogrammable LDPC decoder ch, IEEE J. Sold-State Crcuts, vol. 41, , Mar [12] Massmo Rov, Fracesco Ross, Pasqale Cao, Ncola L Islata, Luca Faucc. Layered Decodg of No-Layered LDPC codes Proc.the 9th Euromcro comferece o Dgtal System Desg, , Se, [13] E. Boutllo ad F. Gulloud, LDPC decoder, corresodg method, system ad comuter rogram, US atet 7,174,495 B2, Feb [14] C. Marchad, J.-B. Dor e, L. Code-Caeca, ad E. Boutllo, Coflct resoluto by matrx reorderg for DVB-T2 LDPC decoders, Global Telecommucatos Coferece. Hoolulu, USA, Oct [15].M.Taer, A recursve arroach to low comlexty codes, IEEE Tras. Iform. Theory, IT-27, , Setember [16] J. Che, A. Dholaka, E. Eleftherou, M. Fossorer, ad X.-Y. Hu, Reduced-Comlexty Decodg of LDPC Codes, IEEE Tras. Commu., vol. 53, o. 8, , Aug [17] X-Yu Shh,Cheg-Zhou Zha, Cheg-Hug L, ad AN-Yeu(Ady) Wu, A 8.29mm 2 52mW Mult-Mode LDPC Decoder Desg for Moble WMAX System 0.13m CMOS Process, IEEE J. Sold-State Crcuts, vol43, No.3, , March [18] M. M. Masour ad N. R. Shabhag, A 640-Mb/s 2048-bt rogrammable LDPC decoder ch, IEEE J. Sold-State Crcuts, vol. 41, o. 3, , Mar [19] Chh-Hao Lu, Shau-We Che, Chl-Lug Che,Hse-Cha Chag, Che-Y Lee ad et al. A LDPC decoder ch based o self-routg etwork for IEEE e alcato, IEEE J. Sold-State Crcuts, vol.43, o.3, , Mar [20] A. J. Blaksby ad C. J. Howlad, A 690-mW 1-Gb/s 1024-b, rate-1/2 low-desty arty-check code decoder, IEEE J. Sold-State Crcuts, vol. 37, , Mar [21] T. Brack, M. Alles, F. Kele, ad N. Whe, A sytheszable IP core for WIMAX E LDPC code decodg, Proc. IEEE 17th It. Sym. Persoal, Idoor ad Moble Rado Commucatos,. 1 5, Se Yog He was bor 1974 Hebe, Cha. He receved B.S. ad M.S. degrees from Bejg Broadcastg Isttute, Bejg, Cha, 1996 ad 1999, resectvely. He receved Ph.D. degree 2002 ad s a rofessor the Isttute of Mcroelectrocs Chese Academy of Sceces. Presetly, he s seor vstg scholar Uversty of Calfora, Los Ageles. Hs research terestg cludes DSP ad VLSI alcato, recofgurable rocessor, wreless commucato ad low ower desg methodology. He has ublshed over 40 techcal aers referred coferece ad jourals. Shusha Qao was bor 1981 Shax, Cha. He receved B.S. degree Automato from Hua Uversty, Chagsha, Cha He receved the Ph.D. degree IMECAS, At reset, he s a assstat rofessor of IMECAS. Hs scoe of actvty comrses wreless commucato, DSP ad VLSI alcato. He has ublshed over 10 techcal aers refereed coferece ad jourals. Ku Guo was bor 1982 Dala, Cha. She receved the B.S. degrees Electrcal ad Electroc Egeerg from Taj Uversty, Taj, Cha, She s curretly ursug the Ph.D. degree the Isttute of Mcroelectrocs Chese Academy of Sceces (IMECAS), Bejg, Cha. Her research terests clude wreless commucato ad low ower desg.