EMI Modeling and Characterization for Ultra-Fast Switching Power Circuit Based on SiC and GaN Devices

Transcription

1 EMI Modeling and Characterization for Ultra-Fast Switching Power Circuit Based on SiC and GaN Devices DISSERTATION Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy in the Graduate School of The Ohio State University By Kaichien Tsai Graduate Program in Electrical and Computer Science The Ohio State University 2013 Dissertation Committee: Dr. Longya Xu, Advisor Dr. Jin Wang Dr. Mahesh S. Illindala

2 Copyright by Kaichien Tsai 2013

3 Abstract Electromagnetic interference (EMI) has been a well known problem ever since the introduction of Silicon (Si) based BJT, MOSFET, and IGBT. EMI noise is unavoidable due to breaks in the current and voltage generated by the switching actions of semiconductor devices. The noise is transmitted in the form of conducted and radiated emission through conductors and radiation. The advancement of Wide Band-gap (WBG) devices such as Gallium Nitride (GaN) transistors and Silicon Carbide (SiC) BJT and MOSFET have allowed designers to achieve higher power density and efficiency of circuits by utilizing the ultra-fast switching frequency, speed, and the ability to operate at a larger range of temperatures. As the result of the more compact design, EMI control in electronic circuits has become more challenging with regard to functional issues, operational robustness, increased cost, thermal, and space constraints. Due to the superior switching abilities of WBG devices, inductor-less circuit topologies, such as switched-capacitor circuits are drawing quite a bit of attention. The Common Mode (CM) noise inherent in these types of circuits is severe due to the rapid change of node voltages. The CM noise current is created by combining the parasitic impedance between the node and the common reference plane. The CM choke in EMI filters is used to suppress CM noise while preserving the differential signals. The PSPICE model is proposed to evaluate and predict the performance of the CM choke the ii

4 accuracy of which is verified up to 100MHz. In addition, we analyzed the grounding of the Y-capacitor's ability to effectively muffle CM noise. Many researchers have identified the fast transients of dv/dt and di/dt with various parasitic components which contribute to major conducted noise in pulse width modulation (PWM) controlled converters and inverters. To predict the conducted noise emission level, it is essential to identify the electronic circuit at the initial design stage. A circuit modeling procedure and transient analysis in PSPICE are demonstrated using a GaN based switched-capacitor circuit to predict and identify the noise generated by the CM and transmission paths. We proposed improvements to reduce the CM noise based on the derived CM noise equivalent circuits, which were verified in both the computer simulation and experimental testing. In addition to the conducted noise emission in the power line, we also investigated the noise problem due to electromagnetic field coupling within the SiC BJT based three phase inverter system. We also identified the known and potential problems in power circuits, gate drive, and control board during high power operation in the experiment. Some practical noise mitigation techniques for each sub-system are proposed and verified in both computer simulation and experimental testing. iii

5 Dedication This document is dedicated to my family and all the people that I love. iv

6 Acknowledgments I would like to express my deepest gratitude to my PhD advisor, Dr. Longya Xu, who has consistently provided academic guidance and funding support throughout my graduate study career. His immense knowledge, insightful research, and great patience have inspired and helped me to develop independent and creative thinking skills, which will benefit me throughout my entire life. I also want to thank my advisor for providing me with many wonderful projects and opportunities to explore the area of motor drive control, power electronic applications, and EMI. Without his unwavering guidance, encouragement, and precision, this dissertation would not have been possible. I also want to thank Dr. Jin Wang, Dr. Donald Kasten, Dr. Steven Sebo, Dr. Vadim Utkin, and Dr. Mahesh S. Illindala for their numerous useful discussions, advice, and ideas, which were all very beneficial to my graduate career over the past few years. I would like to give my special thanks to Dr. Chingchi Chen from Ford for his guidance and suggestions for my EMI study. In addition, I would like to thank Dr. Minghua Fu, Dr. Xiaolin Lu, and Smart Grid team from Texas Instruments for providing thought provoking and challenging research projects and the opportunity to gain industry experience while working as an intern. I want to thank Dr. Julia Zhang, who is currently an Assistant Professor at Oregon State University as well as a senior fellow student, Mr. Bo Guan, for their help to my v

7 course work, research, and numerous discussions. I will always remember the days and nights we spend together in the lab. I also want to thank my junior group members Mr. Mark Scott, Mr. Zhendong Zhang, Mr. Yu Liu, Mr. Haiwei Cai, Mr. Dakai Hu, Mr. Feng Qi, Mr. Ernest Davidson, Dr. Ke Zou, Mr. Feng Guo, Mr. Cong Li, Mr. Lixing Fu, Mr. Jinzhu Li, Ms. Xiu Yao, Mr. Luis Herrera, Mr. Xuan Zhang, Mr. Chengcheng Yao, Mr. Da Jiao, and Ms. Pu Xu for their friendship, help and support during the happy and challenging days over the past six years. vi

8 Vita July B.S Electrical and Computer Engineering, The Ohio State University Sept to present...ph.d student, The Ohio State University Publications [1] Kaichien Tsai; Longya Xu; Feng Qi; Ernest Davidson;, "Common Mode EMI Noise Characterization and Improvement of a Gallium-Nitride Switched- Capacitor Circuit," Energy Conversion Congress and Exposition (ECCE), 2013 IEEE [2] Longya Xu; Bo Guan; Huijuan Liu; Le Gao; Kaichien Tsai;, "Design and control of a high-efficiency Doubly-Fed Brushless machine for wind power generator application," Energy Conversion Congress and Exposition (ECCE), 2010 IEEE, vol., no., pp , Sept Fields of Study Major Field: Electrical and Computer Engineering vii

9 Table of Contents Abstract... ii Acknowledgments... v Vita... vii Publications... vii List of Tables... xi List of Figures... xii Chapter 1: Introduction Introduction to EMC and EMI Literature Review Motivation of The Work Chapter Preview Chapter 2: Passive Device High Frequency Modeling Introduction Methods of Impedance Measurement and Limitations CM Choke Modeling CM Inductance L CM Extraction Leakage Inductance L leakage Extraction Impedance Z 1 Determination CM Choke PSPICE Implementation and Verification Capacitor and DM Inductor Modeling Study of the EMI Filter Grounding Effectiveness for CM Noise viii

10 2.6.1 Effects of a Common Grounding Path Effects of Mutual Coupling Between Two Grounding Paths Computer Simulation and Experimental Testing Simulation Result Experimental Results Summary Chapter 3: Active Device High Frequency Circuit Modeling Introduction CM Noise Circuit Modeling of Voltage Doubler Converter Operating Principle High Frequency CM Noise Circuit Modeling Circuit Model Verification Common Mode Noise Analysis Equivalent Circuits The Concept of Circuit Balance Computer Simulation and Experimental Testing Simulation Results Experimental Results Summary Chapter 4: Electromagnetic Interference in Power Electronics Introduction Power Circuits Power Device Test Setup PCB Layout Considerations ix

11 4.3 Gate Drive Circuits Control Circuits Summary Chapter 5: Conclusion and Future Work Conclusion Future Work Appendices Appendix A: Impedance of Capacitors Appendix B: Transmission Line Effect Appendix C: Capacitive Coupling Mechanism Appendix D: Magnetic Coupling Mechanism Appendix E: Selecting Dielectric Material for IMS Appendix F: List of Principle Symbols References x

12 List of Tables TABLE 1.1 PROPERTIES OF SI, GAN, AND SIC DEVICE... 9 TABLE 2.1 FIVE CASES FOR EMI FILTER GROUNDING ANALYSIS TABLE 3.1 Q3D SIMULATION OF EACH TRACE TABLE 3.2 STRAY INDUCTANCE IN THE VOLTAGE DOUBLER CIRCUIT TABLE 4.1 EXTRACTED SELF AND MUTUAL INDUCTANCE OF TEST SETUP IN FIGURE xi

13 List of Figures FIGURE 1.1 BLOCK DIAGRAM OF NOISE PROPAGATION PATH... 2 FIGURE 1.2 TEST SETUP FOR CONDUCTIVE NOISE MEASUREMENT... 3 FIGURE 1.3 IMPEDANCE BETWEEN EUT PORT AND REFERENCE GROUND... 4 FIGURE 1.4 SIMPLIFIED HIGH FREQUENCY MODEL OF CONDUCTIVE NOISE MEASUREMENT.. 4 FIGURE 1.5 COMPLETE CONDUCTED NOISE TEST SETUP... 5 FIGURE 2.1 ONE STAGE EMI FILTER FIGURE 2.2 (A) STRUCTURE OF CM CHOKE, (B) HIGH FREQUENCY CIRCUIT MODEL OF CM CHOKE FIGURE 2.3 EQUIVALENT CIRCUIT OF Z CM MEASUREMENT FIGURE 2.4 IMPEDANCE FOR L CM, EPC, AND EPR EXTRACTION FIGURE 2.6 EQUIVALENT CIRCUIT FOR L LEAKAGE EXTRACTION FIGURE 2.7 IMPEDANCE FOR L LEAKAGE EXTRACTION FIGURE 2.8 EQUIVALENT CIRCUIT FOR Z 1 MEASUREMENT FIGURE 2.9 IMPEDANCE FOR Z 1 EXTRACTION FIGURE 2.10 EQUIVALENT CIRCUIT FOR Z 1 EXTRACTION WITH SHORTED CM CHOKE FIGURE 2.11 IMPEDANCE OF Z 1 WITH SHORTED CM CHOKE FIGURE 2.12 LUMPED CIRCUIT MODEL FOR Z 1 / FIGURE 2.13 CM CHOKE SPICE IMPLEMENTATION FIGURE 2.14 CM CHOKE SIMULATION RESULT IN SPICE (A) Z CM, (B) Z DM, (C) Z 1, (D) Z 1 WITH WINDINGS SHORTED FIGURE 2.15 INSERTION LOSS OF CM CHOKE WITH (A) FIXED 3.9MH CM CHOKE AND VARIOUS SHUNT CAPACITANCES, (B) FIXED SHUNT CAPACITANCE AND VARIOUS INDUCTANCES xii

14 FIGURE 2.16 CIRCUIT MODELS FOR (A) L DM =47µH, (B) C Y2 =100NF, (C) C Y1 =56NF, (D) C X1 =10µF FIGURE 2.17 CIRCUIT CONFIGURATION FOR CM NOISE GROUNDING ANALYSIS FIGURE 2.18 EQUIVALENT CIRCUIT OF ONE STAGE EMI FILTER FOR CM NOISE ANALYSIS. 32 FIGURE 2.19 EQUIVALENT CIRCUIT WITH A WIRE CONNECTING TO A REFERENCE FRAME FIGURE 2.21 SIMULATION RESULT OF GROUNDING FOR (A) ORIGINAL EMISSION, (B) CASE 1, (C) CASE 3, (D) CASE 2, (E) CASE 4, AND (F) CASE FIGURE 2.22 DIAGRAM OF THE TEST SETUP FOR CM NOISE GROUNDING INVESTIGATION.. 41 FIGURE 2.23 CONDUCTIVE CM NOISE EMISSION (A) WITHOUT EMI FILTER, (B) COMMON GROUND WITH A SINGLE WIRE CONNECTION TO REFERENCE PLANE, (C) SEPARATE GROUNDING PATHS WITH TWISTED WIRES, (D) ONLY C Y2 IS APPLIED IN THE FILTER, (E) SEPARATE GROUNDING WITH LONG WIRES, (F) SEPARATE GROUNDING WITH SHORT WIRE FIGURE 3.4 MODEL OF THE CERAMIC CAPACITOR FOR C IN, C 1, AND C FIGURE 3.5 COPPER TRACES OF THE VOLTAGE DOUBLER CONVERTER FIGURE 3.6 GAN SOFT-SWITCHING VOLTAGE AND CURRENT WAVEFORMS FROM (A) SIMULATION AND (B) EXPERIMENT FIGURE 3.7 NOISE MODEL OF THE VOLTAGE DOUBLER FIGURE 3.8 EQUIVALENT CIRCUIT OF NOISE V FIGURE 3.9 EQUIVALENT CIRCUIT OF NOISE V FIGURE 3.10 EQUIVALENT CIRCUIT OF NOISE V FIGURE 3.11 EQUIVALENT CIRCUIT OF NOISE V FIGURE 3.12 EQUIVALENT CIRCUIT OF NOISE V FIGURE 3.13 WHEATSTONE BRIDGE CIRCUIT FIGURE 3.14 TOTAL CM NOISE IN TIME DOMAIN FOR (A) ORIGINAL CIRCUITRY, (B) 200PF ADDED AT C A AND C N, (C) 10NF ADDED AT C L AND C E FIGURE 3.15 TOTAL CM NOISE IN FREQUENCY DOMAIN FOR (A) ORIGINAL CIRCUITRY, (B) 200PF ADDED AT C A AND C N, (C) 10NF ADDED AT C L AND C E xiii

15 FIGURE 3.16 EXPERIMENTAL RESULT OF CM NOISE FOR (A) ORIGINAL CIRCUITRY, (B) 200PF ADDED AT C A AND C N, (C) 10NF ADDED AT C L AND C E FIGURE 3.17 ORIGINAL CM NOISE FROM 100KHZ TO 30MHZ FIGURE 3.18 CM NOISE WHEN 200PF IS ADDED TO C A AND C N FIGURE 3.19 CM NOISE WHEN 10NF IS ADDED TO C L AND C E FIGURE 4.1 BLOCK DIAGRAM OF A TYPICAL THREE PHASE INVERTER IN MOTOR DRIVE APPLICATION FIGURE 4.3 T-CLAD CIRCUIT BOARD FIGURE 4.4 AN EXAMPLE OF LAMINATED DC BUS BAR FIGURE 4.5 RELATIONSHIP OF MAGNETIC FLUX IN LAMINATED BUS BAR FIGURE 4.7 REDUCING LOOP INDUCTANCE IN POWER CIRCUITS FIGURE 4.9 SIC BJT AND JBS DIODE BASED THREE PHASE INVERTER DESIGN FIGURE 4.10 EXPERIMENTAL RESULT OF I BASE (PINK, 2A/DIV) VS. I BJT (GREEN, 10A/DIV) VS. V CE (BLUE, 100V/DIV) FIGURE 4.11 BUCK CIRCUIT SCHEMATIC FIGURE 4.12 BOOST CIRCUIT SCHEMATIC FIGURE 4.13 CIRCUIT CONFIGURATION FOR DC BUS SHORT CIRCUIT INVESTIGATION FIGURE 4.14 EXPERIMENTAL WAVEFORM OF CURRENT MEASURED AT DC BUS DURING SWITCHING TRANSIENTS. CH1: DC BUS VOLTAGE 25V/DIV, CH2: I BASE_TOP 2A/DIV, CH4: V RLIM1=5Ω 25V/DIV FIGURE 4.15 SIMPLIFIED CIRCUIT SCHEMATIC FOR ABNORMAL BUS CURRENT INVESTIGATION FIGURE 4.16 SIMULATION RESULT OF SWITCHING TRANSIENT AT (A) 50V DC BUS, (B) 300V DC BUS FIGURE 4.17 CIRCUIT SCHEMATIC OF TOP SWITCH WITH CURRENT FLOW DIRECTION WHEN BOTTOM SWITCH TURNS ON FIGURE 4.18 BLOCK DIAGRAM OF THE ENHANCED GATE DRIVE BOARD FIGURE 4.19 SIMULATION RESULT OF SWITCHING TRANSIENT AT 300V DC BUS WITH THE PROPOSED GATE DRIVE xiv

16 FIGURE 4.20 SWITCHING TRANSIENT OF THE TOP BJT GATE DRIVE. CH1: DC BUS VOLTAGE 100V/DIV, CH2: I LIM1 5A/DIV, CH3: V RLIM1=5Ω 25V/DIV, CH4: I BASE_TOP 2A/DIV FIGURE 4.21 EXPERIMENTAL RESULT OF V BE AT 100V DC BUS WHEN (A) BOTTOM BJT TURNS ON, (B) TOP BJT TURNS ON FIGURE 4.22 CIRCUIT SCHEMATIC OF SHORT CIRCUIT PROTECTION FIGURE 4.23 EXPERIMENTAL RESULT OF DESATURATION PROTECTION CIRCUITRY. CH1: V BE 10V/DIV, CH2: V CE 5V/DIV, CH3: V DESAT 5V/DIV FIGURE 4.24 LOGIC DIAGRAM OF HEX INVERTING SCHMITT TRIGGER FIGURE 4.25 CHARACTERISTIC OF HYSTERESIS LOOP FIGURE 4.26 HEX SCHMITT TRIGGER INPUT AND OUTPUT WAVEFORMS FIGURE 4.27 A SIMPLE CIRCUIT TO MINIMIZE FIGURE 4.28 TRANSIENT CURRENTS OF DIGITAL IC FIGURE 4.29 MEASURED IMPEDANCE FOR 2.2µF, 0.1µF, 10NF, AND 1NF FIGURE 4.30 IMPEDANCE OF MULTIPLE CAPACITORS CONNECTED IN PARALLEL (A) 0.1µF // 0.1µF // 0.1µF, (B) 0.1µF // 10NF // 1NF, (C) 2.2µF // 2.2µF // 2.2µF, (D) 0.1µF // 10NF // 2.2µF FIGURE 4.31 EQUIVALENT CIRCUIT OF (A) 0.1µF, 10NF, AND 1NF CONNECTED IN PARALLEL, (B) RESONANT AT P4, (C) RESONANT AT P FIGURE 4.32 AD CONDITIONING CIRCUIT WITH CM AND DM NOISE CONSIDERATION AT SIGNAL INPUT FIGURE 4.33 OUTPUT VOLTAGE SIMULATION RESULT OF (A) UNBALANCED, (B) BALANCED INPUT IMPEDANCE. (C) FFT RESULT OF UNBALANCED INPUT IMPEDANCE FIGURE 4.34 ELECTROMAGNETIC EFFECTS OF SHIELDED CABLE FIGURE 4.35 EQUIVALENT CIRCUIT OF SHIELDED CONDUCTORS TABLE 4.1 EXTRACTED SELF AND MUTUAL INDUCTANCE OF TEST SETUP IN FIGURE FIGURE 4.36 EQUIVALENT CIRCUIT OF THE SHIELDED CABLE FIGURE 4.37 SIMULATION RESULT OF MAGNETIC COUPLING WITH SHIELD (A) UN- GROUNDED, (B) SINGLE END GROUNDED, (C) BOTH END GROUNDED xv

17 FIGURE 4.38 EXPERIMENTAL RESULT OF MAGNETIC COUPLING WITH SHIELD (A) UN- GROUNDED, (B) SINGLE END GROUNDED, (C) BOTH END GROUNDED FIGURE A.1 1µF CERAMIC CAPACITOR USED FOR C IN, C 1, AND C FIGURE A.2 IMPEDANCE OF A 2000UF ELECTROLYTIC CAPACITOR FIGURE A.3 IMPEDANCE OF A 200UF FILM CAPACITOR FIGURE B.1 SCHEMATIC OF A VOLTAGE MEASUREMENT SETUP FIGURE B.2 CHARACTERISTIC IMPEDANCE, Z 0 OF THE 12 INCH RG-58 CABLE FIGURE B.3 TIME DELAY, T D OF THE 12 INCH RG-58 CABLE FIGURE C.1 (A) CAPACITIVE COUPLING CIRCUIT; (B) NOISE COUPLED ON CONDUCTOR FIGURE D.1 (A) INDUCTIVE COUPLING CIRCUIT; (B) NOISE COUPLED ON CONDUCTOR FIGURE E.1 LIFESPAN PREDICTION AT DIFFERENT OPERATING TEMPERATURE xvi

18 Chapter 1: Introduction 1.1 Introduction to EMC and EMI Electronic equipment is said to have electromagnetic compatibility (EMC) if it does not cause interference with other systems, interfere with its own processes, and is not susceptible to noise generated from other systems. The electromagnetic environment includes both conducted and radiated energy; therefore, EMC requires both emission and susceptibility [1]. On the other hand, electromagnetic interference (EMI) stands for the level of interference generated from electronic equipments. In power electronic applications, the major EMI issues are coming from the high rated dv/dt and di/dt of the switching devices such as IGBT, MOSFET. The dv/dt and di/dt are caused by the pulse-width modulation technique which is often found in modern controls to meet the design requirements in dynamic response, size, and weight. As a result, high slew rates of dv/dt and di/dt containing noise in a wide frequency spectrum are generated. The typical noise propagation path is illustrated in Figure 1.1. In general, the major noise sources within electronics are generated from dv/dt and di/dt of the switching devices. In lower voltage items, high speed digital circuits, such as DSP, communication circuits, and various clock sources would also contribute substantial amounts of noise to 1

19 the power supply ground. The receptor is defined as the circuits that are susceptible to the noise, which normally are the low voltage control circuits, such as pulse width modulation (PWM) signals, digital signals from position sensors, and analog signals. The coupling paths provide the channel to transmit noise from source to receptor. Noise sources Coupling paths Receptor Figure 1.1 Block diagram of noise propagation path Methods of noise coupling can be categorized into two types: conductive and radiative. Conductive noise coupling is defined as the noise that is transmitted through wires from the noise source to another circuit. The typical bandwidth of conductive noise falls below 30MHz. Noise above 30MHz contains both conductive and radioactive noises. Radiatively coupled noise includes electric (capacitive) field coupling, magnetic (inductive) field coupling, and a combination of both, known as electromagnetic field coupling. When the receiver is close to the source (near field), the two types of coupling are considered separately. When the receiver is far from the source (far field), the radiation is considered to be a combination of electric and magnetic field [2]. The total emission for conductive noise is measured across AC or DC power lines. The noise can be separated into two types: Differential Mode (DM) and Common Mode (CM) noise. For a single phase AC and DC power supply, two identical Line Impedance Stabilization Networks (LISN) were connected at the input sides to reduce the DM and CM noise, as shown in Figure 1.2. LISN is used to ensure that the noise can be measured consistently. The parameters in LISN can vary depending on the current 2

20 ratings. The LISN, shown in Figure 1.2, was employed to measure the conducted noise in the present study. The 5µH inductor in the LISN was used to block noise generated from the converter returning to the power supply. It also prevents external disturbances from entering the converter. Two capacitors, 0.22µF and 4µF with a 5Ω current limiting resistor were used to divert the external noise to a ground. The 0.1µF capacitor provided a low impedance path to measure high frequency noise across the 1kΩ resistor. The 1kΩ discharges 0.1µF capacitor when it is removed from a power line. Spectrum Analyzer Attenuator Power splitter or combiner LISN1 5µH 0.22µF 4µF 0.1µF AC or DC 0.22µF 5Ω 5Ω 4µF 1kΩ 1kΩ 0.1µF DC or AC bus input Electronic equipment LISN2 5µH Figure 1.2 Test setup for conductive noise measurement The outputs of two LISNs are usually connected through an attenuator before being connecting to a Spectrum Analyzer (SA). Because the terminal impedance of the spectrum analyzer (SA) is 50Ω, the input impedance is limited under test conditions (EUT) to slightly less than 50Ω, as shown in Figure

21 Figure 1.3 Impedance between EUT port and reference ground The equivalent circuit for high frequency noise is illustrated in Figure 1.4 where the impedance of LISN on the EUT side is modeled as a 50Ω resistor. i CM Z S Converter 50Ω 50Ω V 1 V 2 i DM Z S V S1 i CM 2i CM Z C Figure 1.4 Simplified high frequency model of conductive noise measurement In Figure 1.4, the DM and CM noise currents are represented by the blue and red lines, respectively. CM noise current is generated if there is an equivalent coupling impedance, Z C, between the ground and the converter. The total noise level is measured by connecting one of the LISNs to the SA while terminating the other with 50Ω impedance. However, total noise can be separated into DM and CM noise based on the 4

22 voltage drop across the two LISN, V 1 and V 2 using the paths shown in Figures (1.1) and (1.2). (1.1) (1.2) In the experiment, V 1 and V 2 were connected through a power splitter or a combiner to obtain a phase shift of 180 or 0 for DM and CM noise extraction. The time domain noise was converted to frequency spectrum by using an SA. The final conducted noise test setup is explained in Figure 1.5. Combiner / Splitter LISN Bulk capacitor Power circuit, gate drive, heatsink Ground plane DSP controller Wall Computer Spectrum Analyzer Resistive load box Power supply Figure 1.5 Complete conducted noise test setup Conductive noise emission is defined as the level of total noise transmitted through conductors back to the power sources. However, it does not explain how the noise source is coupled into the system. Therefore, it is crucial to be able to identify the 5

23 hidden coupling paths in order to effectively reduce the conducted noise emission. Based on this information, the optimal solution can be provided to effectively reduce the total noise emission. Ultimately, the electronic equipment must be able to pass the EMC regulations in order to be sold around the world. 1.2 Literature Review The EMI problem was first identified in radio receivers as early as the 1900's; however, at this time the problems were easily fixed by reassigning the transmitting frequencies onto a less crowded spectrum or repositioning the cable further away from the noise source. [1]. However, the invention of the Integrated Circuit (IC) and semiconductor devices brought more severe interference which was widely spread over the frequency spectrum. Due to this phenomenon, the Federal Communications Commission (FCC) in the United States published various EMC regulations to control the levels of noise emissions for various applications. In addition to emission control, the FCC also requires that the electronic equipment be able to resist a certain level of noise generated from surrounding equipment or from electrical surges to ensure greater reliability. Ever since the introduction of the Bipolar Junction Transistor (BJT) in the 1950's [3], power converters have become much more popular due to their high efficiency, power density, and dynamic performance. As the switching frequency and speed increases, conducted noise begins to get louder due to the impulse current generated from switching devices, such as rectifier and DC to AC inverters [4]-[7]. The distorted input 6

24 current waveform mainly contributes to DM noise, which would increase the chances of power converter malfunction during high torque and speed operation if no proper steps are taken to avoid this problem. In addition to the high levels of DM noise, other serious problems, such as premature winding failures, shaft voltage, and bearing currents due to dv/dt and parasitic impedance between EUT and the ground were also discovered [13]- [14]. Proper design and placement of the LC filters on the AC input or output or the common reference plane or any combinations of the above for a three phase rectifier and inverter were implemented to suppress total noise emission and improve system stability [12]-[16]. However, not all the coupling paths and levels of the parasitic capacitance have been identified. In order to effectively bypass and suppress conductive noise emission, it is necessary to identify the major parasitic coupling paths. One approach is to insert switching transients into key spots and monitor the noise on various locations [17]. The method does not require EUT to be functional or the system to be powered up; therefore, this test can be conducted in the early stages of development. Another approach is to identify the equivalent noise source and use the dominant distribution paths to estimate the location of the conductive noise emission [18]. Although there are many other ways to identify the coupling paths for various applications, most methods only focus on a specific operation mode to predict total noise emission. The coupling mechanism due to high frequency components, such as voltage and current oscillations across power devices during normal operation, remains unclear. Another limiting factor for direct noise measurement is the small amount of space between traces. 7

25 To further understand and be able to reproduce EMI issues, a high frequency circuit model of EUT is necessary. We attempted to study the conducted EMI emission on a three phase inverter [19]-[20]. The power devices were created using a physicsbased modeling technique. Only the major parasitic components of the device modules, passive components, cables, leads, and interconnections were constructed using Time Domain Reflectometry (TDR). The high frequency circuit model with extracted inductances and capacitances were simulated in the PSPICE program. It provided well matched result from 10kHz to 30MHz. Furthermore, EMI emission was lower if zero voltage soft (ZVS) switching was implemented compared to hard switching [19]. The circuit model was very helpful for component layout optimization and noise estimation. However, it was difficult to determine the coupling effects between traces within a complex structure using the TDR method. This could limit the effect of parasitic components as well as the accuracy of noise prediction with increased frequency. Upon completion of the PCB layout of the initial design, it will be possible to extract parasitic components, including the stray inductance, parasitic capacitance, and the mutual coupling effects between wires, using Finite Element Analysis (FEA) tools, such as an Ansys Q3D extractor. Ideally, when all the boundary conditions, material properties, and excitation sources have been identified, the electric and magnetic field distribution within the boundaries can be determined. The accuracy of the simulation was determined by the quality of mesh, which is a tradeoff between quality and performance. Ref. [21]-[23] found that the conducted EMI simulation using the extracted 8

26 parameter from FEA was relatively accurate as long as the noise source and propagation paths were properly modeled. The EMI issues discussed above focus on Si based power electronic applications, such as IGBT and MOSFET. The noise problem became more severe when wide bandgap devices (WBG), such as Gallium Nitride (GaN) and Silicon Carbide (SiC) began to be widely used for power converters for greater efficiency [24]-[28]. One reason for their popularity was their ability to switch at higher speeds (smaller dt) due to higher saturation velocities [29]. Another reason was that WBG devices have lower onresistance (larger di) compared to Si devices with similar voltage ratings and higher breakdown voltage (larger dv) with similar drift region spacing (gate-to-drain spacing) due to higher critical electric fields [29]-[30]. The actual parameters are summarized in Table 1.1. Another advantage of the WBD devices are the high bandgaps (E g ) which allow the device to operate at higher temperatures compared to Si devices [30]. Si GaN SiC Saturation velocity (cm/s) Critical electric fields (MV/cm) Bandgaps (ev) Table 1.1 Properties of Si, GaN, and SiC device In sum, WBG devices allow for designs with higher efficiency and power density. Ref [31] and [32] demonstrate that a 760W boost converter and a 900W three phase inverter has 99% efficiency. A 5kW SiC photovoltaic inverter with four times greater power density than a Si inverter and peak efficiency of 99% is illustrated in reference [33]. 9

27 Another important aspect of EMC is the EMI filter which is used to effectively reduce noise emission at the input and/or output of electrical equipment. With the trend toward higher switching frequencies, it is essential that the EMI filter perform well at high frequencies. EMI filters using scattering parameters (S-parameters) were proposed to extract the parasitic components which affect performance at high frequencies [34]. The Equivalent Parallel Capacitance (EPC) has been shown to be one of the limiting factors for excellent performance at high frequencies [35]. Based on the equivalent circuit, two small capacitors were added at the end of each winding to cancel out the EPC effect. Another solution is to insert and ground an embedded conductive layer into the CM winding to establish a parasitic cancellation [36]-[37]. Many previous EMI studies have focused on simply reducing the total noise emission. However, EMI not only transmits through conductors but also interferes with nearby circuits. 1.3 Motivation of The Work Because WBG semiconductor devices, such as GaN transistor and SiC MOSFET, allow for much higher switching speeds (GaN dt<3ns at 480V, SiC dt<24ns at 800V) and frequencies at the same voltage range as traditional IGBT or MOSFET, they will benefit from smaller circuit footprints and higher efficiency. However, their more compact design also means more vulnerable control signals due to stronger noise sources and larger parasitic components. Since PWM is often applied to turn the switches on and off, the induced dv/dt and di/dt act as excitation sources and provide high frequency voltage 10

28 and current oscillation across switching devices. This would further boost CM and DM conducted noise emission levels, especially in high frequency ranges. In order to fully utilize the superior switching capabilities of the GaN and SiC power devices, identifying noise sources and their propagation paths is extremely important. A PSPICE circuit modeling procedure for active devices was proposed and demonstrated using a GaN based switched-capacitor circuit. Conducted CM noise generated by the circuit was analyzed, which verified the proposed improvement in both computer simulation and experimental testing. An EMI filter is often added to the input or output of power converters. We proposed a circuit model of CM choke to suppress CM currents, which is applicable up to 100MHz. By combining both the active circuit and the EMI filter circuit model, the total noise emission of the system can be predicted. 1.4 Chapter Preview Chapter 2 presents a four step circuit modeling procedure for measuring CM choke based on impedance measurements. The PSPICE implementation method simulation results correlate well with the low frequency test results up to 100MHz. We were able to systematically evaluate grounding effectiveness by building an EMI filter using the capacitor model. Chapter 3 explains the circuit modeling procedures for GaN switched-capacitor circuit in detail. Specifically, this chapter examines critical parameters such as the GaN model, stray inductances of traces, mutual coupling inductances, and main bus capacitors. The concept of circuit balance, based on the Wheatstone Bridge, is proposed to minimize 11

29 the conducted noise emission. Significant improvement is verified in both the computer simulation and experimental testing. Chapter 4 discusses the known and potential EMI issues within a SiC based three phase inverter system. The noise source is generated from the power circuit and forced into the low voltage circuits through parasitic capacitances and mutual coupling inductances. Some layout improvements and circuit design considerations are proposed to increase the noise immunity. The effectiveness of detail shielding is investigated in this chapter as well. Chapter 5 summarizes the research presented in this dissertation and suggests topics for future research. 12

30 Chapter 2: Passive Device High Frequency Modeling 2.1 Introduction The EMI filter has been widely used to suppress conducted EMI noise emission in various electronic systems. A typical one stage EMI filter includes inductors and capacitors to filter DM and CM noise, as shown in Figure 2.1 [42]. The DM (C X1, C X2 ) and CM capacitors (C Y1, C Y2 ) provide a low impedance path to bypass the noise currents. Both C X1 and C X2 are only effective against DM noise, while C Y1 and C Y2 reduce the DM noise by half. On the other hand, DM (L DM ) and CM inductors (L CM ) create a high impedance path to block EMI noise currents. The total effective DM inductor includes the leakage inductance of CM choke and 2X L DM. To control CM noise, the effective inductance should include L CM and half of L DM. Depending on the size requirements, more stages can be added by connecting multiple one stage filters in series. For a typical two stage EMI filter, one stage would normally focus on filtering low frequency noise, while the other would filter the high frequency noise. Due to the trend of increasing switching speeds and frequencies, the effectiveness of an EMI filter at high frequencies has become even more crucial. Therefore, modeling the components of an EMI filter is critical to understanding how the parasitic components affect it. The derived model can also be implemented in computer simulations to evaluate the filter performance and 13

31 predict noise distribution of a system by including the power converter or the noise sources. 1 CM choke 3 L DM C Y1 C Y2 C X1 C X2 C Y1 C Y2 2 4 L DM Figure 2.1 One stage EMI filter This chapter will first present the proposed modeling procedure for CM choke based on the impedance. Then, the steps to construct the CM choke SPICE model using the extracted parameters will be presented. Based on the model, the key parameter affecting the performance of CM choke will be identified. In order to maximize the EMI filter performance, a systematic analysis approach on the various grounding configurations was studied. The grounding analysis was verified in both the computer simulation and via experimental testing. 2.2 Methods of Impedance Measurement and Limitations An impedance analyzer, Agilent 42941A and a test fixture, 16047E were used to obtain the impedance of the CM choke and capacitors. Since the frequency range of interest was from 10kHz to 100MHz, open and short calibrations were needed to compensate for the transmission characteristics due to stray inductance and parasitic capacitance of the test fixture leads. The induced errors were dependent upon test 14

32 frequencies, test fixtures, test leads, devices under test (DUT) connection configurations, and surrounding conditions [38]. Hence, the key to obtaining accurate impedance measurement is to compensate for the actual measurement setup. If an impedance analyzer is not applicable, a function generator (10kHz to 100MHz) and oscilloscope for current measurement can be used to obtain impedance versus frequency curve. A BNC cable with 50Ω characteristic impedance is recommended for measurement of the current because the transmission line effect can only be removed by matching the impedance between the cable and the oscilloscope terminal impedance (generally 50Ω). matching is provided in Appendix B. A more detailed explanation of impedance One limitation of using this method is the possibility of a distorted current waveform near resonance frequencies which could degrade the accuracy of the measurements. When an impedance analyzer is used, the data is averaged over a large number of sampling points to improve measurement precision and consistency [38]. In addition to being highly accurate, both methods provide intuitive understanding of the impedance curve at various frequencies. 2.3 CM Choke Modeling CM choke is extensively used to suppress CM noise current, which is generated by power circuits that are coupled to the ground. Figure 2.2 (a) shows the typical structure of a CM choke in which the flux linkage, λ CM (solid line) is doubled for CM noise currents, and λ DM (dashed line) is cancelled out for DM noise currents. Figure 2.2 (b) shows the proposed high frequency CM choke circuit model. 15

33 EPR Winding 1 EPC 1 I CM λ CM λ DM I DM L line R DC L R DC L line 3 2 I CM I DM 4 2 L line Z 1 /2 R DC L 2 EPC Z 1 /2 R DC L line 4 EPR Winding 2 (a) (b) Figure 2.2 (a) Structure of CM choke, (b) high frequency circuit model of CM choke where L 1 and L 2 are the self inductance of windings 1 and 2. EPC represents the equivalent parallel capacitance of one set of windings. Since the wires are wound across the magnetic core and stacked on top of each other, it makes sense that the winding capacitance would dominate the impedance at high frequencies. Therefore, EPC is connected across L 1 and L 2. EPR is the equivalent parallel resistance to identify core loss. L line represents stray inductance due to wire connections, which is generally very small. R DC is the DC resistance of the winding, which is in the milliohm range for power line filters. Z 1 represents the coupling impedance between two sets of windings, which is dominated by the capacitance. The impedance is divided in half and connected diagonally across pins 1 and 4 and pins 2 and 3 so the impedance from pins 1and 2 is the same as from pins 3 and 4. Z 1 is essential because it will interact with leakage inductance and change impedance behavior at high frequencies. 16

34 2.3.1 CM Inductance L CM Extraction The induced voltage in windings 1 and 2 due to CM noise current is given in Eqs. (2.1) and (2.2). Since the flux linkage is enhanced in this configuration, the CM impedance, L CM is equal to the combination of self and mutual inductance. Because the CM choke is generally symmetrical, windings 1 and 2 can be assumed to have identical L CM for both windings, found in Eq. (2.3). (2.1) (2.2) (2.3) L CM was extracted by measuring the impedance between the shorted pins 1 and 2 and pins 3 and 4. The effects of the winding impedance Z 1 was not taken in this case. As a result, the equivalent circuit would be equal to two sets of parallel windings, as shown in Figure 2.3. The measured (solid blue line) and estimated (red dashed line) impedance are depicted in Figure

35 Impedance (ohm) EPR/2 Impedance Analyzer 2EPC 1,2 L line /2 L CM /2 R DC /2 3,4 V S1 Figure 2.3 Equivalent circuit of Z CM measurement 10 5 Z CM Z CM measured Z CM estimated Frequency (Hz) Figure 2.4 Impedance for L CM, EPC, and EPR extraction A seen in Figure 2.4, the inductance is expected to dominate at low frequencies; therefore, L CM can be calculated based on Eq. (2.4). (2.4) 18

36 where Z CM is the CM impedance at low frequency f CM. For the choke under test, the measured Z CM at 80.5kHz was equal to 2036Ω and the calculated L CM was approximately 8mH. Other parameters, such as stray inductance of wires, L line were estimated proportionate to the length of wire, which was less than 10nH. This set R DC at less than 168mΩ. Both results would not affect the accuracy of the model because they are only effective at extremely high or low frequencies. EPC was calculated at the resonance point, according to Eq. (2.5). (2.5) where Z CM_OSC is the impedance at the resonance frequency f CM_OSC. Based on the measured Z CM_OSC, which was equal to 15.8kΩ at the resonance frequency of 1.127MHz, an EPC was calculated as 2.5pF. The round shape at the resonance point suggested that the core had a high loss. EPR was used to represent the core loss, while this parameter was obtained by trial-and-error to match the peak magnitude at the resonance point. Since the permeability of magnetic material is highly nonlinear at high frequencies, the estimated EPR was adjusted slightly in order to obtain more accurate results. The final extracted circuit parameters will be presented in Section Leakage Inductance L leakage Extraction CM choke, explained in Figure 2.2 (a), is like a transformer if pins 2 and 4 are considered the primary windings and pins 1 and 3 are the secondary windings or vise versa. If pins 3 and 4 are connected, as shown in Figure 2.5 (a), then the terminal 19

37 voltages across pins 2 and 4 (winding 2) and pin 1 and 3 (winding 1) would satisfy Eqs. (2.6) and (2.7). And the leakage inductance, L leakage would be equal to the difference of self and mutual inductance, as given in Eq. (2.8). The equivalent circuit of a transformer is depicted in Figure 2.5 (b). (2.6) (2.7) (2.8) CM choke L 1 3 L leakage = L 2 - M L leakage = L 1 - M 2 M 4 4 M 3 L 2 (a) (b) Figure 2.5 (a) CM choke circuit schematic and (b) equivalent circuit for L leakage extraction where M is the mutual inductance. To obtain the leakage inductance, L leakage for windings 1 and 2, pins 1, 3 and 4 were shorted. Because L leakage is much less than M, the impedance measured between pin 2 and pins 1,3 and 4 was dominated by the 2X leakage inductances. With the assumption that the value of L leakage for windings 1 and 2 are the same, the final equivalent circuit for L leakage extraction is revealed in Figure 2.6. The measured (blue solid line) and estimated (red dashed line) impedance are given in Figure

38 Impedance (ohm) EPR Impedance Analyzer L line EPC 2L leakage R DC 2 1,3,4 V S1 Figure 2.6 Equivalent circuit for L leakage extraction Z leakage 10 5 Z leak measured Z leak estimated (no winding parasitics) Frequency (Hz) Figure 2.7 Impedance for L leakage extraction At low frequencies, the impedance is dominated by the 2L leakage ; therefore L leakage is calculated according to Eq. (2.9). (3.9) 21

39 where Z leakage is the impedance at low frequencies (f leakage ). At 10kHz, the Z leakage is equal to 2.836Ω and the calculated L leakage is equal to 22.57µH. With the EPC and EPR, obtained from Section 2.3.1, the estimated L leakage (red dashed curve) shows a good correlation with the measured impedance in Figure 2.7. The two extra resonance points between 50 and 70MHz were due to winding parasitic effects, which will be discussed in Section Impedance Z 1 Determination Z 1 can be determined based on the measured impedance across pins 1and 2 when pins 3 and 4 are open. Since the applied current was DM, only the leakage inductance was involved. The equivalent circuit for Z 1 extraction is given in Figure 2.8 and the measured impedance (solid blue line) is shown in Figure 2.9. EPR Impedance Analyzer 1 L line R DC EPC L leakage V S1 2 L line Z 1 /2 R DC L leakage EPC Z 1 /2 EPR Figure 2.8 Equivalent circuit for Z 1 measurement 22

40 Impedance (ohm) 10 7 Z Z 1 measured Z 1 estimated (C 1 only) Frequency (Hz) Figure 2.9 Impedance for Z 1 extraction We expected Z 1 to be dominated by a capacitive load due to the physical layout of the windings. This suggests that the value of the capacitor, C 1 could be obtained in the low frequency range, according to Eq. (2.10). (2.10) At very low frequencies, such as 10kHz, the measured impedance was 6.52MΩ, which was too large to measure accurately. As a result, the equipment measurement range was taken into account to approximate an accurate reading. At 40.85kHz, Z C1 was equal to165.8kω, and the calculated C 1 was 1.175pF. Using the same parameters discussed in previous sections, the estimated Z 1 curve (red dashed line), where C 1 was the only parameter used to plot Figure 2.9. In the figure, the two resonance points at

41 and 20.83MHz correlate very well, but the equivalent circuit failed to show resonance at and 55.4MHz. To calculate these resonance points, the effects of CM choke were minimized by shorting the first and second windings. A simplified version of the equivalent circuit is shown in Figure 2.10 where L line1 and L line2 represent the stray inductances of wire connections for the short circuits and CM choke windings impedance measurement. Impedance Analyzer L line1 1 L line2 0 3 V S1 Z 1 /2 Z 1 /2 L line1 2 L line2 0 4 Figure 2.10 Equivalent circuit for Z 1 extraction with shorted CM choke The measured impedance (solid green line), represented in Figure 2.11, showed that there was no resonance at and 20.83MHz. This is because L leakage was minimized by L line2. In the figure, the impedance at low frequency remains dominated by C 1. Since the stray inductance of L line1 and L line2 were only several nano henries, resonance with C 1 would not occur below 100MHz. Therefore, the resonance is likely caused when C 1 interacts with the distributed parasitic inductance and capacitance. The lumped circuit model in Figure 2.12 was applied to describe the resonance points at (f R1 ) and 55.4MHz (f R2 ). 24

42 Impedance (ohm) 10 7 Z 1 windings shorted 10 6 Z 1s measured Z 1s estimated Frequency (Hz) Figure 2.11 Impedance of Z 1 with shorted CM choke C 1 L 2 C 2 R 2 Figure 2.12 Lumped circuit model for Z 1 /2 According to the lumped circuit model, f R1 and f R2 will satisfy Eq. (2.11) and (2.12). The final fitted curve result is represented as the black dotted line in Figure (2.11) (2.12) 25

43 Insertion of the derived Z 1 into the equivalent CM choke model in Figure 2.2 (b) caused glitches to occur between 50 and 70MHz, as illustrated in Figure 2.7 and Figure 2.9, which can be accurately reproduced. The final CM choke model is shown in the next section. 2.4 CM Choke PSPICE Implementation and Verification One simple way to model CM choke in PSPICE is to use two mutually coupled inductors. Each inductor represents the self-inductance, L 1 or L 2 of the winding, which can be derived based on Eqs. (2.3) and (2.8). The mutual inductance between two windings, M, can also be obtained by utilizing these two equations. The coefficient of coupling, k, will represent the mutual coupling effects. Eq. (2.13), (2.14), and (2.15) are the derived equations used to determine L 1, M, and k. (2.13) (2.14) (2.15) Since L CM and L leakage were equal to 7.7mH and 22.57µH, the corresponding L 1 and M were calculated to be 3.861mH and 3.839mH. Based on L 1 and M, the k of this choke was equal to In some cases, L leakage is purposely designed to be larger (with a lower k value) in order to provide sufficient filtering against DM noises without additional DM inductors. 26

44 The circuit parameters and schematic are given in Figure By connecting the choke to the four configurations, as discussed in previous sections, the impedances for Z CM, Z DM, Z 1, and Z 1 with shorted windings are shown in Figure Figure 2.13 CM choke SPICE implementation 27

45 Impedance (Ω) Impedance (Ω) (a) (b) (c) (d) Frequency (Hz) Figure 2.14 CM choke simulation result in SPICE (a) Z CM, (b) Z DM, (c) Z 1, (d) Z 1 with windings shorted Compared to the measured impedances in Figure 2.4, Figure 2.7, Figure 2.9, andfigure 2.11, the proposed circuit model with calculated parameters was able to accurately reproduce the characteristics of CM choke from 10kHz to 100MHz. Since the magnetic core model was linear in this simulation, the mismatch of resonance could be slightly higher than the measurement. Despite this limitation, the proposed parameter extraction method and PSPICE implementation are useful when evaluating CM choke performance via a computer simulation. 28

46 Insertion loss (IL) is one way to measure the performance of CM choke [1]. It is defined as the ratio of CM current without the choke compared to the CM noise current with the choke, as shown in Eq. (2.16). Based on this definition, larger IL is desirable in a wide frequency range. (2.16) Figure 2.15 (a) and (b) depict the insertion loss of the CM choke in two scenarios: 1) fixed CM inductance with various shunt capacitances, 2) fixed shunt capacitance with various CM inductances. It is clear from the figure that filter performance at high frequencies (1 to 100MHz) is not benefited by increased inductances; instead it is reduced considerably as a function of EPC. Therefore, the most important parameter that determines the high frequency performance of CM choke is the parasitic capacitance, EPC. 29

47 EPC x1 Insertion loss (db) EPC x10 EPC x5 EPC x20 (a) L 1 x20 Insertion loss (db) L 1 x1 L 1 x5 L 1 x10 (b) Frequency (Hz) Figure 2.15 Insertion loss of CM choke with (a) fixed 3.9mH CM choke and various shunt capacitances, (b) fixed shunt capacitance and various inductances 2.5 Capacitor and DM Inductor Modeling In addition to CM choke, the EMI filter also includes X and Y-capacitors and a DM inductor [1], [2], [42]. The modeling procedures for capacitors 56nF, 100nF and 10µF of the one stage EMI filter in Figure 2.1 are explained in Section The two additional 47µH DM inductors, L DM, were modeled following similar procedures for L CM, discussed in Section Since two of the L DM were not mutually coupled, the effectiveness of CM inductance from the two DM inductors was reduced to 1/2L DM ; 30

48 however, the effectiveness of DM inductance was actually doubled. Circuit parameters for the capacitors and DM inductors are given in Figure pF 13.6nF 13.4nF 28.3nF 42mΩ 65mΩ 60mΩ 48.7µF 38kΩ 100.5n 55.7n 9.95µF (a) (b) (c) (d) Figure 2.16 Circuit models for (a) L DM =47µH, (b) C Y2 =100nF, (c) C Y1 =56nF, (d) C X1 =10µF 2.6 Study of the EMI Filter Grounding Effectiveness for CM Noise The one stage EMI filter, shown in Figure 2.1, with focus on major parasitic components as shown in Figure Based on the Thevenin theorem, the equivalent CM noise source and coupling impedance of the reference plane are represented by V CM and Z CM. Since the positive and negative DC bus were connected for more efficient CM noise analysis, the circuit can be further simplified, as shown in Figure 2.18, by combining the two sets of windings. The total CM noise current measured on LISN was equal to Eq. (2.17). This study was conducted based on reference [43] where the author investigated the EMI filter s performance in a motor drive system. 31

49 L line EPR 1 EPC 1 EPR 2 EPC 2 C LISN 50Ω 50Ω C LISN ESL 1 C Y1 C Y1 ESL 1 C L 1 L 1 L DM L DM ESL 2 C Y2 C Y2 ESL 2 V CM L line EPC 1 EPR 1 EPC2 EPR 2 Z CM I CM3 I CM1 I CM2 I CM Figure 2.17 Circuit configuration for CM noise grounding analysis EPR 1 /2 EPR 2 /2 2EPC 1 2EPC 2 LISN L line /2 L CM /2 L DM /2 2C LISN ESL 1 /2 M1 ESL 2 /2 M2 V CM 25Ω ESR 1 /2 ESR 2 /2 Z CM 2C Y1 2C Y2 I CM3 I CM1 C I CM2 I CM Figure 2.18 Equivalent circuit of one stage EMI filter for CM noise analysis (2.17) In Figure 2.18, the voltage drop across LISN is approximately equal to V CM1 if the stray inductance of the line is very small or negligible within the range of the frequency of interest. As a result, to minimize noise detected by LISN, V CM1 must be kept small. Based on the definition of V CM1, given in Eq. (2.18), ESL 1 would dominate at high frequencies since the C Y1 will be close to zero. Therefore, ESL 1 would become the key 32

50 factor for maintaining a low voltage drop across V CM1 in order to reduce noise detected by LISN. (2.18) Effects of a Common Grounding Path In many power electronic circuit designs, there is usually a large piece of copper which is grounded underneath the EMI filter to provide a low impedance return path. The mid-point of the Y-capacitors, C Y1 and C Y2, shown in Figure 2.17, was connected to this grounding plane to bypass the CM noise current. A short wire was used to connect the grounded board to a common reference frame, such as the metal case of electronic equipment. The equivalent circuit of this configuration is illustrated in Figure 2.19 where C and B represent the ground layer and common reference plane, respectively. The additional wire connecting C and B is represented by a stray inductance, L wire. 33

51 EPR 1 /2 EPR 2 /2 2EPC 1 2EPC 2 LISN L line /2 L CM /2 L DM /2 2C LISN ESL 1 /2 M1 ESL 2 /2 M2 V CM 25Ω ESR 1 /2 ESR 2 /2 Z CM 2C Y1 2C Y2 I CM3 I CM1 C I CM2 I CM L wire B Figure 2.19 Equivalent circuit with a wire connecting to a reference frame Since the added wire carried both I CM1 and I CM2, there was an additional voltage drop on L wire. The total voltage between point B and M1 is given in Eq. (2.19). (2.19) At low frequencies, I CM1 and I CM2 are lessened due to the large impedance of C Y1 and C Y2. The total CM noise current was determined by inductance of the CM choke and DM inductor. As frequency increases, I CM2 would increase and would be expected to be much higher than I CM1 because I CM1 is limited by the CM inductance on the return path. CM noise measured on LISN would be much higher since V BM1 would be added across V LISN. The number of noise increases can be calculated by placing Eq. (2.19) over Eq. (2.18). If I CM2 = n 1 I CM1, L wire = n 2 ESL 1, and C Y1 would be negligible at high frequencies, then the ratio of noise increment, m 1 could be found by using Eq. (2.20). 34

52 (2.20) If n 1 = 10 and n 2 = 2, then the CM noise would increase by 44X or be degraded by 33dB compared to the scenario without additional wire connections. One way to minimize the noise increment is by using a shorter wire or copper strips to reduce the stray inductance of L wire. Another way is to reduce the variance in current between I CM1 and I CM2 by adding more Y-capacitors across C Y1. Unless n 2 is equal to zero, there will always be degradation in this configuration. Therefore, the most effective way to reduce CM noise in a one stage EMI filter is to ground C Y1 and C Y2 separately. If this is not possible, then C Y1 should be removed in order to maintain the high output impedance for CM noise at high frequencies Effects of Mutual Coupling Between Two Grounding Paths With separate grounding, the additional voltage drop on a single wire due to the large difference in current between I CM1 and I CM2 was removed. However, at high frequencies filter performance could still be limited by the mutual coupling effect between the two wires. The equivalent circuit of separate grounding with mutual coupling effect is given in Figure Since the two wires, L wire1 and L wire2 were connected to the same reference plane, T-equivalent circuit could be used for circuit analysis. 35

53 EPR 1/2 EPR 2/2 EPR 1/2 EPR 2/2 2EPC 1 2EPC 2 2EPC 1 2EPC 2 LISN L line /2 L CM /2 L DM /2 LISN L line /2 L CM /2 L DM /2 2C LISN ESL 1 /2 M1 ESL 2 /2 M2 V CM 2C LISN ESL 1 /2 M1 ESL 2 /2 M2 V CM 25Ω ESR 1 /2 ESR 2 /2 Z CM 25Ω ESR 1 /2 ESR 2 /2 Z CM 2C Y1 2C Y2 2C Y1 2C Y2 I CM3 I CM1 L wire1 M C I CM2 L wire2 I CM3 I CM1 I CM2 L wire1 -M L wire2 -M M C Figure 2.20 Equivalent circuit of mutual coupling effect between two separate grounding The new voltage drop between C and M1 is equal to Eq. (2.21). Although the effective inductance in the C Y1 branch was reduced, additional voltage drop due to I CM2 M was added. (2.21) The ratio of increased noise can be analyzed by following a similar analysis procedure, given in section If I CM2 = n 1 I CM1, L wire1 = n 2 ESL 1, and M = k L wire1 = n 2 k ESL 1, then the noise ratio, m 2 can be determined from Eq. (2.22). (2.22) Eq. (2.22) is quite similar to m 1 with the difference of k multiplied by n 1. Since k is the coefficient of coupling, its value varies from 0 to 1. If n 1 = 10, n 2 = 2, and k = 0.1 (M is 10% of L wire1 ), then there would be an 18dB noise degradation. Compared to m 1, m 2 is likely to be lower since the coupling coefficient between the two wires is normally less than 1. As the frequency increases, the differences between I CM1 and I CM2 or n 1 36

54 should increase and become the major limiting factor to the filter s high frequency performance. If the length of the wire is fixed, according to Eq. (2.22), k must be reduced in order to minimize m 2. One simple way to reduce k is by further separating the two grounding paths. Another way is to place the two wires perpendicularly in order to reduce the magnetic flux coupling effect. This section provides a systematic approach for analyzing the grounding in a one stage EMI filter. Based on the analysis, the grounding of the Y-capacitor for each stage should be separated and kept far away from the other. The wires connecting to the reference plane and ESL of the Y-capacitors need to be small in order to maximize the effectiveness of the filter. The contact resistance between wire and reference plane must be minimized as well to reduce the voltage drop. The grounding analysis is also applicable to EMI filter with multiple stages. 2.7 Computer Simulation and Experimental Testing Simulation Result The purpose of the computer simulation was to verify the one stage EMI filter performance based on different grounding configurations, as discussed in Section 2.6. The simulation is setup according to Figure CM noise was generated via a square wave which mimics the V DS waveform across switching devices. The switching frequency was 500kHz with raising and falling speed of 10ns. Since the CM noise current was formed mainly through capacitive coupling between power device and the 37

55 reference plane, 300pF capacitor and a small equivalent series resistor of 10mΩ was used to represent the CM coupling impedance, Z CM. The models for CM choke and capacitors, C X1, C Y1, and C Y2 in the EMI filter were built based on the actual components derived in Sections 2.4 and 2.5. Two LISNs were connected at the positive and negative rail for CM noise extraction. The stray inductance of the wire was L wire = 30nH. We created five scenarios, listed in Table 2, that were based on the grounding analysis. The simulation results, including the five scenarios and original noise emission levels, are given in Figure (1) C Y1 and C Y2 are connected to a common ground and a single wire is used to connect to the reference plane (2) Only C Y2 are connected to reference plane (3) Separate grounding with k = 0.1 (simulate two wires close to each other) (4) Separate grounding with k = 0.01 (simulate two wires far from each other) (5) Ideal grounding Table 2.1 Five cases for EMI filter grounding analysis 38

56 (a) (b) (c) (d) (e) (f) Frequency (Hz) Figure 2.21 Simulation result of grounding for (a) original emission, (b) case 1, (c) case 3, (d) case 2, (e) case 4, and (f) case 5 The frequency spectrum of the original noise emission is shown in Figure 2.21 (a). Compared to Scenario 1, which is given in Figure 2.21 (b), CM noise had only 5dBµV or approximately 5% improvement from 1 to 10MHz. The filter became more effective as frequency increased from 10 to 100MHz due to the Y-capacitors. If C Y1 and C Y2 were connected to a reference plane separately with two twisted wires (coupled, k=0.1), as shown in Figure 2.21 (c), CM noise would be reduced by another 10 to 39

57 20dBµV compared to Scenario 1. If the two wires were significantly separated (k = 0.01), as shown in Figure 2.21 (e), then another 20 to 40dBµV improvement would be observed compared to Scenario 3. If separate grounding is not possible, then only a C Y2 would be used. The simulation result for this scenario is given in Figure 2.21 (d) in which the noise level was 10dBµV lower compared to Scenario 3. The performance of the ideal filter with zero stray inductance is depicted in Figure 2.21 (e). CM noise can be further reduced by an additional 10 to 20dBµV from Scenario 4 if the stray inductance of the wire could be reduced. This simulation verified the grounding analysis in Section 2.6. Furthermore, it showed that the performance of the EMI filter can be greatly affected by different grounding configurations Experimental Results This experiment was performed to verify that different configurations of grounding have a real impact on filter effectiveness. The test setup is given in Figure 2.22 in which the voltage source was generated from the voltage doubler circuit switching at 304kHz. The EMI filter was connected in series to the DC bus, while the Y- capacitors were connected to a common reference plane. Two LISNs and a combiner were used to reduce the conductive CM noise. 40

58 LISN1 5µH Source 0.22µF 0.22µF 4µF 5Ω 5Ω 4µF 0.1µF 1kΩ 1kΩ 0.1µF C X1 1 C Y1 C Y1 2 CM choke 3 4 L DM C Y2 C Y2 L DM DC+ DC- Voltage doubler circuit LISN2 5µH Reference plane Z CM Figure 2.22 Diagram of the test setup for CM noise grounding investigation The original conductive CM noise emission, ranged from 100kHz to 50MHz, without EMI filter is shown in Figure 2.23 (a). The measured high emission was due to the high switching speed and frequencies of the six GaN devices in the voltage doubler. The peaks of 30 and 45MHz were caused by the voltage ringing across V DS during turnoff transients. Therefore, an EMI filter was applied to reduce conductive noise emissions. Figure 2.23 (b) shows the experimental result when two Y-capacitors were first connected to a common ground on PCB and to a reference plane with a single wire. This resulted in most of the CM noise being reduced from 90 to 80dBµV or lower. By separately grounding to the reference plane with twisted wires, the test results, illustrated in Figure 2.23 (c), show that the improvement compared to Figure 2.23 (b) was less than 5dBµV. In the scenario with only a C Y2 attached, shown in Figure 2.23 (d), the noise at 1, 10, 30 and 45MHz was still higher than 60dBµV, which was better than separate grounding paths using a high coupling coefficient. However, if the two grounding paths were placed far away from each other, even with a 2X wire length, the noise would be reduced by 12 to 25%, as shown in Figure 2.23 (e). Another 8 to 12% improvement in 41

59 the high frequency range was achieved by reducing the length of the wire, as illustrated in Figure 2.23 (f). (a) (b) 80dBµV 60dBµV (c) (d) 80dBµV 60dBµV (e) (f) 80dBµV 60dBµV Figure 2.23 Conductive CM noise emission (a) without EMI filter, (b) common ground with a single wire connection to reference plane, (c) separate grounding paths with twisted wires, (d) only C Y2 is applied in the filter, (e) separate grounding with long wires, (f) separate grounding with short wire 42

60 2.8 Summary We studied the parasitic effects of the key components, CM choke, DM inductor, and capacitors on a one stage passive EMI filter. Open and short compensation was performed in order to remove the parasitic effects due to the leads in the test fixture. If an impedance analyzer is not applicable, an oscilloscope and function generator may be used to obtain the impedance measurement. However, the typical impedance of the cable must correlate well with the terminal impedance in the scope in order to prevent the transmission line effect at high frequencies. We proposed procedures for measuring the impedance and calculating the parameters for CM choke. The corresponding PSPICE model was built based on the proposed circuit model. The simulation results of CM choke had good agreement with measurements from 10kHz to 100MHz. The winding capacitance was identified as the major limit to high frequency filtering performance. Other components including the DM inductor and capacitors were also extracted for EMI filter grounding analysis. The analysis showed that CM noise performance of EMI filter can be greatly affected due to improper grounding configurations. Due to the large current difference between the two Y-capacitors at high frequencies, the Y-capacitor near LISN should be grounded separately in order to reduce the additional voltage drop caused by the other Y-capacitor. Even with separate grounding, mutual coupling still occurs between the two wires which must be minimized by keeping both wires far away from each other. To further improve the high frequency performance, the length of the wire should be kept as short as possible. Both computer simulation and experimental testing have confirmed the results of the grounding analysis. 43

61 Chapter 3: Active Device High Frequency Circuit Modeling 3.1 Introduction Converters based on switched-capacitor circuits utilizing WBG devices, such as GaN, benefit from the high switching speed (<10ns) and operating temperature capabilities. However, the sharp rising and falling edge of the drain-to-source voltage acts as an excitation source to the parasitic inductance and capacitance, which results in EMI and over voltage due to voltage oscillation. Because of the parasitic capacitance between GaN and the heatsink, hidden paths are formed for dv/dt to flow into the ground and generate CM noise. This kind of parasitic capacitance is normally inherit in the circuit structure and is difficult to minimize. To fully utilize the high switching speed of the GaN transistors in the switchedcapacitor circuit based converter, characterizing EMI, especially the CM noise, becomes critical. We built a PSPICE circuit model focusing on the major parasitic components to try to eliminate CM noise. Parameter extractions for the critical components were implemented using Q3D FEA and an impedance analyzer. We were able to verify the accuracy of the circuit model through experimental testing. Based on the balance concept theory, this paper also proposes the third way to reduce the CM noise emission. One common way to reduce the noise emission is to 44

62 suppress and/or bypass CM noise by using a CM choke and Y-capacitors. Another way is to increase dt by reducing the switching speed, changing the control strategy or altering the circuit structure at the expense of higher switching rates and system complexity. Improvement and minimization of CM noise by the proposed way is presented. As a counter example, a case which could lead to higher CM noise based on this analysis is also discussed. All cases were verified by both computer simulation and experimental testing. 3.2 CM Noise Circuit Modeling of Voltage Doubler Converter Operating Principle Figure 3.1 shows the switch capacitor circuit we studied for CM noise investigation. The circuit has two modes of operation, as shown in Figure 3.2. During the first mode, Figure 3.2 (a), C 2 was connected in series with C IN through S 6 to form the output voltage. At the same time, C 1 was being recharged by the DC bus C IN through S 1 and S 2. In the second mode, in Figure 3.2 (b), the output voltage was established by connecting C 1 and C IN through S 3 while C 2 was being recharged through S 4 and S 5. At this time all the switches were operating at 50% duty cycle. The total output voltage of the circuit was doubled without the use of any magnetic components. In this paper, this switched-capacitor circuit will henceforth be referred to as the voltage doubler converter. In Figure 3.1, each GaN device, S 1, S 2, S 3, S 4, S 5 and S 6 was attached to a heatsink with a thin layer of insulation material in between. If the heatsink was connected to 45

63 ground, this creates parasitic capacitances. The proposed high frequency voltage doubler circuit model including the major parasitic capacitance and stray inductance is shown in Figure 3.3. S 1 L 11 S 4 Z LISN Z LISN S 3 C IN C 1 C 2 S 6 S 2 L 22 S 5 R L Figure 3.1 Dc-dc voltage doubler circuit S 1 L 1 S 4 + I C1 + DC + + C 1 I C IN C1 C C S S 3 S R L 2 I R I R DC I R I C2 C IN S 5 I C2 + C 2 - R L I R (a) (b) L 2 I R Figure 3.2 The equivalent circuit (a) when C 1 is charging (b) C 2 is charging C b C a C c C d C e C f C g L 21 L 13 L 11 L 23 ESR 1 L 15 S 1 ESR IN L 25 S 4 ESR 2 ESL 1 ESL IN ESL 2 S 3 S 6 C1 L 16 C IN L 26 C 2 L 14 S 2 L 12 L 22 S 5 L 24 C n C m C l C k C j C i C h Figure 3.3 The equivalent circuit with the stray inductances 46

64 3.2.2 High Frequency CM Noise Circuit Modeling To study and predict the high frequency CM noise caused in the voltage doubler converter, a CM noise equivalent circuit model was derived to investigate and reproduce the switching characteristic of the circuit. The components modeled included the EPC GaN device, the passive components, such as capacitor, stray inductance of the PCB traces, LISN, the cables for power supply, the resistive loads, and the LISN connections. The PSPICE model for EPC-1010 was obtained from the device supplier, EPC. The model is a hybrid of physics-based and phenomenological functions to create a compact PSPICE model with acceptable simulation and convergence characteristics. The accuracy of the model has been extensively studied in the literature [24]. The model of the 1µF ceramic capacitor used in C IN, C 1 and C 2 is relatively simple but proved to be essential to our study. Both the impedance of the capacitor and stray inductance of the PCB traces affected the resonance frequency and switching behavior. The capacitor impedance was measured with Agilent 42941A from 10kHz to 30MHz. Low frequency range capacitance was obtained by using Eq. (3.1) in the low frequencies. The Equivalent Series Inductance (ESL) was then calculated at the resonance point via Eq. (3.2). The Equivalent Series Resistor (ESR) was obtained by trial-and-error to match the magnitude of the resonance point. The model of the 1µF capacitor is shown in Figure 3.4. Other capacitors, including the electrolytic and film 47

65 capacitor used to stabilize and filter at the DC bus side, were measured and curve fitted in the similar way. The measured and curve fitted results are given in Appendix A. (3.1) (3.2) C=1µF ESL=4nH ESR=7mΩ Figure 3.4 Model of the ceramic capacitor for C IN, C 1, and C 2 The stray inductances, shown in Figure 3.3, are the other critical components which were extracted from the field analysis results using a Maxwell Q3D Extractor. Figure 3.5 shows the Printed Circuit Board (PCB) of the voltage doubler converter imported to the Q3D for parameter extraction. Stray inductance L 11 was found to be equal to the sum of inductance in traces 1, 2 and the externally added 67mm wire in between traces 1 and 2. Stray inductance L 12, L 13 and L 14 were equal to the inductance in traces 3, 4, and 5. Since the circuit was symmetrical at the DC bus, inductance for traces 6, 7, 8, 9, and 10 were equal to traces 1, 2, 3, 4, and 5. In Q3D, the source and sink nodes for each conductor were defined according to the actual current flow, given in Figure 3.2. The current path for each of the two charging loops, I C1 and I C2 is highlighted by black and green dotted lines in Figure

66 2 1 I C C 1 5 C IN 8 C 2 I C1 6 7 Figure 3.5 Copper traces of the voltage doubler converter Table 3.1 contains the simulation results for each trace. The highlighted values in Table 3.1 are the self-inductance, and the other values represent the mutual inductance. The final values for L 11, L 12, L 13, and L 14 were obtained by adding each column, as shown in Table 3.2. For L 11, an additional 43nH was added to compensate for the extra wire inserted in between traces 1 and 2. units: nh Trace 1&2 Trace 3 Trace 4 Trace 5 Trace 1& Trace Trace Trace Table 3.1 Q3D simulation of each trace units: nh L 11 L 12 L 13 L 14 Inductance Table 3.2 Stray inductance in the voltage doubler circuit 49

67 3.2.3 Circuit Model Verification To validate the CM noise circuit model, the simulation results of the circuit model was compared with the experiment, as shown in Figure 3.6 (a) and (b). The simulation results correlated very well with those from the experiment, including details such as the small dip of the output voltage during dead time. The initial current dip and high frequency oscillation components or a charging current I C1 were also accurately reproduced in the circuit model simulation. The oscillation patterns of the simulated V DS waveforms S 1 and S 3 were also very close to those in the experiment. The turn-on and - off time from 10% to 90% or approximately 10ns which was also verified by the experiment. The slight V DS1 decrease and V DS3 increase, observed during experimental testing, were also replicated in the simulation. Since only the major parasitic capacitances were considered in the simulation, the mismatches were expected to increase at higher frequencies. 50

68 25V/div V OUT V DS_S3 V DS_S1 2A/div TIME 1µs/div I D_S1 (a) TIME 400ns/div V DS_S3 10V/div V OUT 20V/div V DS_S1 10V/div I D_S1 2A/div (b) Figure 3.6 GaN soft-switching voltage and current waveforms from (a) simulation and (b) experiment 51

69 3.3 Common Mode Noise Analysis Equivalent Circuits According to the substitution theorem, the switching waveform of a branch can be replaced by a voltage source with the same pattern and the circuit operation will remain the same. So, the voltage waveforms across S 1, S 2, S 3, S 4, S 5, S 6, C 1, C 2, and C IN were replaced with the voltage sources V 1, V 2, V 3, V 4, V 5, V 6, V 7, V 8 and V 9. Superposition was applied to decouple the noise propagation path of each source. The circuit model used for noise analysis is shown in Figure 3.7. Since the circuit was symmetrical in terms of the DC bus, the analysis of V 1, V 2, V 3, and V 7 would also be valid for V 5, V 4, V 6, and V 8. C a C b C c C d C e C f C g L 13 V 1 L 11 L 21 V 4 L 23 V 7 L 15 V 3 V 9 50Ω L 25 V 6 V 8 L 14 V 2 L 16 L 12 50Ω L 22 L 26 V 5 L 24 C n C m C l C k C j C i C h Figure 3.7 Noise model of the voltage doubler To analyze V 1, all other voltage sources can be shorted, and the equivalent circuit obtained is shown in Figure 3.8. Since C d and C k were connected in parallel with LISN, these parasitic capacitances helped to bypass some of the CM noise. Similarly, the equivalent circuits for noise V 2, V 3, V 7, and V 9 are also found in Figure The 52

70 total CM noise measured on LISN was equal to the sum of all the CM currents generated by each source. L 13 I CM1 L 12 L 11 ½ Z LISN C V k C d 1 L 16 L 15 Z L 14 O X Y C n C a C m C l C b GND C c Figure 3.8 Equivalent circuit of noise V 1 L 11 L 12 ½ Z LISN C k C d O L 13 I CM2 L 15 L 16 V 2 X Y L 14 C b C c C l C m C n C a Figure 3.9 Equivalent circuit of noise V 2 I CM3 L 13 L 11 V 3 L 12 L 15 L 16 ½ Z LISN L 14 C k C d C n C a C b C c C l C m Figure 3.10 Equivalent circuit of noise V 3 53

71 L 11 I CM7 L 12 L 15 L 16 ½ Z LISN L 13 V 7 L 14 C k C d C b C c C a C n C l C m Figure 3.11 Equivalent circuit of noise V 7 L L 23 L L 15 L 16 L 14 L 11 L 25 L 26 L 21 L 22 V 9 L 12 C g C f Z LISN Z LISN C a C b C c C d C k C l C m C n I CM9 C e C i C j C h Figure 3.12 Equivalent circuit of noise V The Concept of Circuit Balance The equivalent circuits derived above, except for the noise generated by V 2, have a Wheatstone Bridge type of structure, as shown in Figure The relationship among voltage measurements on LISN, V O and noise source V S can be calculated via Eq. (3.3). Ideally, the noise can be eliminated if Eq. (3.4) is satisfied. Eq. (3.5) shows the impedance relationship of a balanced circuit. 54

72 V O Z 1 Z 2 Z LISN V S V 1 V 2 Z 3 Z 4 Figure 3.13 Wheatstone bridge circuit (3.3) (3.4) (3.5) In Figure 3.8, the equivalent circuit due to V 1 is balanced if Eq. (3.6) is satisfied. (3.6) where, Z XO and Z YO represent the total impedance between X, O and Y, O. Z XGND and Z YGND are the impedance between X, GND and Y, GND. Since the physical trace length between S 1 and S 3 was short, L 15 and L 16 were negligible compared to the other stray inductance. L 13 was connected in parallel with L 14 and the equivalent inductance was approximately 5nH. Because C a and C n were in the pico farad range, these capacitances dominated the impedance between Z and GND. The final impedance of Z XO, Z YO, Z YGND, and Z XGND are given in Eqs. (3.7) - (3.10). (3.7) (3.8) 55

73 (3.9) (3.10) As seen in Table 3.2, L 11 was approximately 10 times larger than L 12. Since C c, C b, C l, C m, C a, and C n are approximately the same, adding the additional capacitor, C X1 at Z XGND was necessary to achieve a balanced condition. After simplification, equivalent circuit V 1 was balanced when Eq. (3.11) was satisfied. (3.11) Similar assumptions to L 13, L 14, L 15, and L 16 were applied to noise V 3. CM noise generated by V 3 was minimized by adding C X3 to the denominator in Eq. (3.12). (3.12) The balanced condition for V 7 in Figure 3.11 was calculated using Eq. (3.13). Since L 14 was approximately 3 times larger than L 13, C X7 was added to the denominator to minimize noise emission. (3.13) For noise V 2 in Figure 3.9, the impedance between Y and GND was infinity. As the result, the noise could not be completely removed by using the balance circuit structure. Instead, V 2 was minimized by adding C X2 at one of the locations in the denominator in Eq. (3.14). 56

74 (3.14) Based on Eqs. (3.11), (3.12), and (3.14), adding a capacitor to C l would have improved the noise due to V 1, V 2, and V 3. Although C X7 would help to reduce CM noise due to V 7, it would have been worse for V 2 and V 3. Similarly, adding a capacitor at C e would have decreased the CM noise generated by V 4, V 5, and V 6. Even though we were unable to compensate for the unbalanced condition of V 2, the overall CM noise emission could have still been improved with the additional capacitors at C l and C e. The CM noise generated by V 9 in Figure 3.12 already had a balanced structure because L 11 and L 12 are equal to L 22 and L 21. All the parasitic capacitances could have been assumed to have been the same because there is an equal distance between the board and reference plane. The circuit remained balance with an additional capacitor at C l and C e. Moreover, CM noise could be further improved by adding a capacitor at C d and C k. 3.4 Computer Simulation and Experimental Testing Simulation Results Computer simulation on the proposed circuit model was setup to study CM noise propagation and validate the proposed improvements. A scenario of improper capacitor placement which could lead to higher CM noise emissions was also demonstrated in the simulation. 57

75 The switching frequency of the circuit was set to 304kHz in order to achieve the zero current switching for S 1 and S 5. The DC bus voltage and peak charge current were 25V and 3.2A, respectively. The parasitic capacitances were difficult to directly measure; therefore, the values were obtained by trial-and-error to correlate with the experimental results. Because the capacitances are not equally distributed in reality, only a small portion of the noise magnitude and high frequency oscillation occurrence will be inconsistent with the experimental results. However, this will not affect the major CM noise distribution. The final parasitic capacitances were set to 20pF in the simulation. Two LISNs were connected to the positive and negative DC bus inputs to measure CM and DM noise. The total CM and DM noise collected by the LISNs were obtained according to Eqs. (3.15) and (3.16). (3.15) (3.16) The CM noise emission of the circuit is given in Figure 3.14 (a), which shows that the noise had a peak value of ±3.1V during the switching transients. If the parasitic capacitance at C a and C n were increased by 200pF, the CM noise measured on LISN would also increase due to the unbalanced condition of V 2, V 3, and V 7. According to Eq. (3.14), the noise generated by V 2 would be 1.7 times higher than in the original scenario. Similarly, Eq. (3.17) was used to calculate the noise generated by V 3 which would be 1.4 times higher than the original emission. For V 7, Eq. (3.18) suggests that the noise collected by LISN would remain the same as in the original 58

76 scenario. Simulation results in Figure 3.14 (b) confirmed that the peaks of the noise increased to ±10V, which was roughly three times higher than the original emission in Figure 3.14 (a). (3.17) (3.18) Since the switching speed and stray inductance of the board were fixed, CM noise improvement was realized by reducing the magnitude of the transient spikes. Based on the analysis in Section 3.3.2, two 10nF capacitors were added at C l and C e to test the effectiveness of CM noise reduction. Figure 3.14 (c) confirms that the peaks of CM noise were reduced from ±3.1V to ±1.2V. The frequency spectrum of the CM noise is shown in Figure Curve (a) in Figure 3.15 represents the CM noise distribution of the original circuit. Compared to curve (b) which corresponds to the scenario in which 200pF was added at C a and C n, the noise underwent a 10dB or 10% increase across 100k - 10MHz. Curve (c) represents the scenario in which 10nF was added at C l and C e. Compared to curve (a), there was a 10dB to 25dB or 11% to 24% improvement from 1-30MHz. However, improvement in the low frequency range was limited. 59

77 V DS_S3 (x15v) VCM (x1v) 1V/div (a) V DS_S1 (x15v) V CM (b) V CM (c) Figure 3.14 Total CM noise in time domain for (a) original circuitry, (b) 200pF added at C a and C n, (c) 10nF added at C l and C e 60

78 (a) dbµv 80dBµV (b) dbµv 80dBµV (c) Figure 3.15 Total CM noise in frequency domain for (a) original circuitry, (b) 200pF added at C a and C n, (c) 10nF added at C l and C e Experimental Results The voltage doubler converter was setup in the lab to verify the proposed circuit model and CM noise analysis. The combiner and splitter were used to extract the CM and DM noise measured by the two LISNs. Figure 3.16 (a), (b), and (c) show the experimental results of CM noise corresponding to the three scenarios in Figure 3.14 (a), (b), and (c). The measured negative and positive peaks of the original CM noise in Figure 3.16 (a) were -3.8V and 4.5V, respectively. Compared to Figure 3.14 (a), the peaks obtained in the experiment were approximately 1.0V higher. The magnitude disparity was expected because not all the parasitic capacitances in the circuit and measurement loop were considered. The peaks that occurred during switching transients were also expected, as shown in Figure 3.14 (a). 61

79 Figure 3.16 (b) shows that CM noise increased when 200pF was added at C a and C n. The measured negative and positive peaks of the CM noise are -10V and 15V respectively, approximately 3.3 times higher than the original scenario in Figure 3.16 (a). The test results correlated well with Figure 3.14 (b), which also estimated a 3X increase in the peak noise. Figure 3.16 (c) illustrates that total CM noise emission decreased when 10nF was added at C l and C e. The CM noise peaks were reduced from -3.8V to -2V and 4.5V to 2.5V. The noise improvement matches Figure 3.14 (c). Figure 3.16 (c) also suggests that the parasitic capacitance was not evenly distributed because the high frequency oscillation components reacted differently depending on whether S 1 was turned on or off. 62

80 V DS_S3 10V/div TIME 400ns/div V CM 1V/div (a) V DS_S1 10V/div V CM 5V/div (b) V CM 1V/div (c) Figure 3.16 Experimental result of CM noise for (a) original circuitry, (b) 200pF added at C a and C n, (c) 10nF added at C l and C e The frequency spectrum of CM noises in Figure 3.16 (a), (b), and (c) are given in Figure Compared to the original CM noise emission in Figure 3.17, Figure 3.18 shows that the CM noise increased by 5-25% across the range of 100k-30MHz when 200pF was added at C a and C n. Figure 3.19 shows that the CM noise was reduced by 5-24% across MHz when 10nF were inserted at C l and C e. 63

81 The experimental results verified that the proposed circuit model was able to accurately predict the trend of CM noise. Figure 3.16 (c) and Figure 3.19 confirm that the total CM noise was substantially reduced when 10nF were added at C l and C e. 80dBµV Figure 3.17 Original CM noise from 100kHz to 30MHz 80dBµV Figure 3.18 CM noise when 200pF is added to C a and C n 64

82 80dBµV Figure 3.19 CM noise when 10nF is added to C l and C e 3.5 Summary A detailed CM noise circuit model of the voltage doubler converter is developed. The hidden CM noise coupling paths propagating CM noise originating from different noise sources were identified. The key components such as the stray inductances and capacitors that affect the switching behavior were obtained through a Q3D extractor and impedance analyzer. The accuracy of the circuit model was verified through comparing the output voltage, V DS waveforms, and charging the current in the computer simulation with those from the experimental testing. We utilized the circuit balance concept based on the Wheatstone Bridge structure to reduce the overall CM noise. According to the CM noise equivalent circuit analysis, total CM noise was reduced by adding capacitors at C l and C e. As an example, another scenario which could lead to higher CM noise was also studied to validate the CM noise 65

83 equivalent circuit and the method of analysis. Experimental results confirmed that the noise sources and CM noise propagation paths were properly modeled. 66

84 Chapter 4: Electromagnetic Interference in Power Electronics 4.1 Introduction EMI issues in power electronic applications are generated due to the high dv/dt and di/dt from switching devices. The problem is expected to become more severe with the introduction of WBG devices since dt would become much smaller while maintaining the same dv and di. The square wave PWM would provide an excitation source for trace stray inductances to interact with the output capacitances of power devices and would result in high frequency oscillation during switching transient. In addition to higher conductive emissions, as discussed in previous chapters, the dv/dt and di/dt would also interfere with nearby circuits inside the converter or inverter through electromagnetic coupling. This chapter will focus on the EMI issues within a three phase inverter designed for traction motor drive application. The inverter was constructed using a SiC based BJT and junction barrier Schottky (JBS) diode. For this type of application, the inverter normally consists of four parts: the power circuit, the gate drive circuit, the control circuit and the on-board power supply, as shown in Figure

85 Source Battery Contactor Soft startup resistor DC Bus Three phase inverter Power circuit Electric Machine Bus voltage Onboard power supply 15V 3V, 5V, 15V V CE PWMs Gate drive circuit Power supply Gate drive circuit Protection circuit PWMs Faults DSP controller Control circuit Analog-to-digital conditioning circuit Position sensor circuit External peripherals Communication circuit Currents Voltages External inputs Thermistors Rotor position Digital I/Os Analog inputs RS-232 CAN Figure 4.1 Block diagram of a typical three phase inverter in motor drive application The DC source of the inverter can come from the battery or AC inputs through a rectifier or converter. Normally, a soft startup circuit is used to pre-charge the DC capacitor when the system is powered up for the first time. The load on the inverter is not limited to a single electric machine but can also be connected to a power grid. In a motor drive application, it would have external inputs, including the rotor position feedback, positive temperature coefficient (PTC) thermistor, digital and analog inputs/outputs, RS-232 as well as CAN for communication. The DSP on the control 68

86 board would collect all the gathered information and execute corresponding commands, such as motor field orientation control (FOC), acceleration, deceleration, shunt down, etc. The gate drive circuit would amplify the PWMs received from the control circuit and generate the proper voltage and current level to drive the power devices. Since the midpoint of each phase leg is floating, the gate drives input and output for both upper and lower switches would need to be isolated using an isolation power supply or non-isolated bootstrap topology. For greater safety, desaturation of the short circuit protection would be implemented to quickly shut down the PWMs when a fault condition is detected. A flyback converter is often used as the on-board power supply due to its ability to generate multiple isolated output voltages. The input of the flyback converter can be obtained from the DC bus or an external power supply, which would also introduce the conductive noise generated by other power circuits. This chapter will discuss the EMI issues identified in previous sections through computer simulation and experimental testing. Theoretical analysis and practical solutions will be provided to mitigate the EMI issues. 4.2 Power Circuits Power Device Test Setup The SiC BJT and JBS diodes to be tested are discrete components, as shown in Figure 4.2. We chose Thermal Clad Insulated Metal Substrate solution (T-Clad IMS) to maintain good thermal dissipation during the three phase operation. 69

87 (a) (b) Figure 4.2 SiC (a) BJT and (b) JBS diode under test The structure of a single layer IMS board was separated into three layers: circuit layer, dielectric and base layer, as given in Figure 4.3. The top circuit layer contained copper foil with a thickness of 4oz. The thickness of the dielectric layer was only 3mils, which provided the required electrical isolation and thermal conductivity. The base layer, made of aluminum or copper, was used to mount the IMS board onto a heatsink for heat dissipation. The SiC BJTs and diodes were soldered onto the top layer, while the IMS board was mounted to a fan forced cooling heatsink. See Appendix E for more detailed information on the selected dielectric material. Figure 4.3 T-Clad circuit board The inherited parasitic capacitance was expected to be large due to the short gap between the power device and the heatsink. If this was the case, then the level of CM noise current could be high, as seen in Eq. (4.1). 70

88 (4.1) Since the circuit topology and parasitic capacitance were fixed, the method to minimize conductive noise was limited to reducing dv or increasing dt. Normally, reducing dv would not be possible due to the fixed DC bus voltage. Increasing dt would result in additional undesired switching losses. Despite the limited solution, one important aspect of reducing the coupling effect would be to minimize the magnitude of voltage overshoot and oscillation during turn-on and -off transients. In addition to the benefits of higher reliability and power loss reduction,, removing oscillation components would also result in lower noise magnitude at high frequencies, which would reduce the conductive noise emission and near field coupling effects PCB Layout Considerations Voltage oscillation occurs when an excitation source is connected to the stray inductance and output capacitance, C CE of the device. If stray inductance is high, then the initial peak turn-off voltage would also be large, as seen in Eq. (4.2). (4.2) One solution for reducing the stray inductance between the DC bus capacitor and the power device is to implement the laminated DC bus bar structure, as the shown in Figure

89 Figure 4.4 An example of laminated DC bus bar The two bus bars were connected to the positive and negative terminal of the capacitor, and the currents through the two bus bars were equal but in the opposite direction. The generated magnetic flux would cancel out if the two copper plates were placed on top of each other, as shown in Figure 4.5. Only the leakage flux, stray inductance of the screw and the un-laminated portion would contribute to the total stray inductance. Φ 1 I 1 I 2 Φ 2 Figure 4.5 Relationship of magnetic flux in laminated bus bar Since the bus bar was connected to the capacitor, a copper jumper was used to represent the capacitor s ideal internal impedance. Aluminum screws were used to connect the jumper and bus bar. The experimental results of the laminated and non- 72

90 Impedance (Ω) Impedance (Ω) laminated bus bar are given in Figure 4.6 (a) and (b). The results show that the total stray inductance was reduced from 31nH to 20nH when the laminated structure was utilized. 1.00E+02 L est_laminated = 20.36nH 1.00E E E E-02 ZL meas. ZL est. 1.00E E E E E E E+08 Frequency (Hz) 1.00E+02 (a) L est_separate = 31.07nH 1.00E E E E-02 ZL meas. ZL est. 1.00E E E E E E+08 Frequency (Hz) (b) Figure 4.6 Experimental result and the estimated stray inductance of (a) laminated, (b) non-laminated DC bus bar Normally, the DC bus capacitor would be constructed using an electrolytic capacitor with a large capacitance but poor high frequency performance due to the large ESL. A film capacitor with low ESL was added near each phase leg to provide a low impedance path during switching, which reduced the peak voltage overshoot. In Figure 4.7, the total stray inductance in the film capacitor loop (red) is much smaller (ESL

91 L stray2 + L stray3 + L stray4 ) than the electrolytic capacitor loop (blue) (ESL 1 + L stray1 + L stray2 + L stray3 + L stray4 ). L stray1 ESR 1 ESR 2 ESL 1 DC Bus ESL 2 Film Cap. Lstray2 L stray3 S1 D1 S2 D2 L stray4 Figure 4.7 Reducing loop inductance in power circuits Stray inductance L stray3 can also be minimized by placing the upper and lower switch close to each other. This is because when S 1 turns off, the current through S 1 will flow freely through D 2. During this transition, L stray3 must be minimized in order to reduce unwanted voltage, current overshoot and oscillation effects. Since the design requirement included device evaluation, a shunt resistor with very low inductance was used to measure the pulsating current through SiC BJT and a diode, as illustrated in Figure 4.8 (a). For voltage measurement, a probe adaptor with a short ground loop was used to minimize loop inductance and improve the high frequency measurement, as shown in Figure 4.8 (b). 74

92 (a) (b) Figure 4.8 SDN series shunt resistor from T&M Research Product, (b) Probe adaptor, Tek for high voltage probe P5120 The final three phase inverter design is shown in Figure 4.9. A laminated DC bus bar was used to minimize L stray1 in Figure 4.7. The snubber capacitors were placed very close to the collector on the top SiC BJT and the emitter on the bottom SiC BJT to achieve the smallest L stray2 and L stray4. Since both BJTs were placed very close to each other, L stray3 was also minimized. Figure 4.10 is an experimental result showing a 50V overshoot when SiC BJT was turned off at 14.5A. 75

93 Laminated DC bus bar V CE measurement L stray4 Snubber capacitors G L stray3 BJT bot C E E BJT top C L stray2 G Current source gate drive Shunt resistor A B C AC output terminals Figure 4.9 SiC BJT and JBS diode based three phase inverter design Figure 4.10 Experimental result of I base (pink, 2A/Div) vs. I BJT (green, 10A/Div) vs. V CE (blue, 100V/Div) 76

94 4.3 Gate Drive Circuits A gate drive is normally placed very close to power devices in order to minimize the loop inductance between its output and the gate-source terminal. As a result, both input and output of the gate drive would be susceptible to noise during switching transients. If the parasitic capacitances, C BE, C BC, and C CE of power devices are large, then the chance of gate mis-triggering during fast switching transients would increase, especially when driving WBG devices. The noise generated by dv/dt and di/dt is coupled to the gate drive input signal radiatively. If the magnitude of the induced noise is higher than the input threshold, then gate mis-triggering could also occur. This section will analyze the EMI issues observed as a result of gate drive and provide mitigation techniques. SiC BJT is a current driven device; therefore, the gate drive must provide the required base current, I base in order to maintain low on-voltage during high current operation. For this particular SiC BJT, the required I base to drive 100A was 4A. IXYS RF MOSFET driver, DEIC421 was selected to obtain a 4A continuous output current. Since the typical operating voltage for DEIC421 is 15V, we chose a 3Ω gate resistor. We applied additional capacitors across the gate resistor to increase the switching speed of the device. Since the SiC BJTs and diodes were not commercial grade, they needed to be tested individually with the corresponding gate drive by configuring the three phase inverter into buck and boost, as shown in Figure 4.11 and Figure In buck mode, the top BJT and bottom diode were tested. While in boost mode, the top diode and bottom 77

95 BJT were evaluated. Once the quality of each device was verified, the inverter was ready for three phase operation. Shunt Resistor Top BJT Shunt Resistor Top Diode DC bus Shunt Resistor Bottom BJT Bottom Diode Shunt Resistor Figure 4.11 Buck circuit schematic Shunt Resistor Top BJT Shunt Resistor Top Diode Shunt Resistor Bottom BJT Shunt Resistor DC bus Bottom Diode Figure 4.12 Boost circuit schematic As the three phase output current and DC bus voltage increased, we observed a DC bus short circuit. An experiment setup, shown in Figure 4.13, under current limiting protection was carried out to reproduce and investigate the failure. Both switches were operating in complementary mode with a 4µs deadtime at the 50V DC bus. 78

96 R lim1 Top BJT Shunt Resistor Top Diode Bottom BJT Bottom Diode Shunt Resistor Figure 4.13 Circuit configuration for DC bus short circuit Investigation Despite the fact that no load was added at the phase output, a 6.75A current spike across R lim1 (5Ω, green) was observed and measured during switching transients, as shown in Figure The blue line in the figure is the top BJT base current. At point a, the top BJT was turning off and the bottom BJT was turning on after 4µs at point b. The current spike at the DC bus was observed during a transient caused by another switch turning on. 79

97 a b Figure 4.14 Experimental waveform of current measured at DC bus during switching transients. Ch1: DC bus voltage 25V/Div, Ch2: I base_top 2A/Div, Ch4: V Rlim1=5Ω 25V/Div A simplified circuit model, given in Figure 4.15, was setup in PSIM to bolster the analysis. The model only considered the static parasitic capacitances across BJT, gate resistors and capacitors in the gate drive circuit and trace stray inductance in the test setup. The provided capacitances of BJT, C BC, C CE, and C BE were 1.86nF, 1.75nF, and 1.0nF, respectively. Since the given bias voltage across V BE was approximately 5V, the gate resistor was set to 5Ω to match the 2A base current in the experiment. An ideal 20nF capacitor was added across the gate resistor to increase the switching speed. The PWM was switching at 10kHz with a 4µs deadtime, which was similar to the experimental setup. The current limiting resistor at the DC bus was reduced to 1Ω in order to enhance the effect of the current spike and also provide a dampening effect to the circuit simulation. In the actual experiment, this resistor represented the trace resistance which was very close to zero. 80

98 Figure 4.15 Simplified circuit schematic for abnormal bus current investigation The simulation result at the 50V DC bus is given in Figure 4.16 (a) where I base_top and I base_bot represented the gate drive current for the top and bottom switch, I g_top was the current flowing into the base terminal of the top switch, and I lim1 was the current through the limiting resistor. A peak current of 12A was observed at I lim1 when one of the switches was turned on, shown in Figure If the DC bus voltage were increased to 300V, I lim1 peak would increase to 35A, as shown in Figure 4.16 (b). Compared to Figure 4.16 (a), the I g_top peak was also higher when it was turned off. Since BJT is a current driven device, the additional base current would result in the device remaining partially turned-on even in the off state, which would result in higher I lim1. If R lim1 were reduced to zero, I lim1 would be very large. 81

99 I9 I I lim1 5A/Div I lim1 20A/Div I4 I I g_top 1A/Div I g_top 1A/Div I2 I7 6 I2 I7 4 2 I base_bot 2A/Div 4 2 I base_bot 2A/Div I base_top (a) Time (s) -2-4 I base_top (b) Time (s) Figure 4.16 Simulation result of switching transient at (a) 50V DC bus, (b) 300V DC bus When the bottom switch was turned on, voltage across the C bc and C ce of the top switch increased and therefore induced I bc and I ce, as shown in Figure If the top gate drive does not provide enough sinking capability, then the additional current would flow into the base terminal, which would cause the device to be turned on. Therefore, I lim1 would be higher due to extra current in I c. 82

100 I lim1 C bc I bc I c I ce C be I be I g_top C ce I base_top Figure 4.17 Circuit schematic of top switch with current flow direction when bottom switch turns on One method to prevent this from happening was to apply negative bias voltage during the off state to increase the safety margin. This would provide a low impedance path between the base and emitter and eliminate I g_top. The block diagram of the proposed new gate drive board is shown in Figure 4.18 where -10V were applied. A push-pull current boost circuitry was built to generate the required 4A base current. Short circuit protection was implemented to shut down PWM during fault situations and prevent further damage to the device. 83

101 Short circuit protection Source 1. Vce monitoring +15 V Integrated Gate Drive Chip Out ( TD350 ) -10 V D44H Fiber Optic 1. PWM inputs 2. Fault outputs Current boost circuitry Figure 4.18 Block diagram of the enhanced gate drive board The simulation result of the proposed gate drive under the 300V DC bus voltage is given in Figure The I g_top current spike was removed when another switch was turned on. The value of I lim1 did not increase compared to the scenario presented in Figure 4.16, which implies no additional I c was generated. 84

102 I I lim1 5A/Div 0 I I g_top 1A/Div 1 0 I4 I I base_bot I base_top 2A/Div Time (s) Figure 4.19 Simulation result of switching transient at 300V DC bus with the proposed gate drive The experimental results, shown in Figure 4.20, indicate that the current sink capability increased and the peak current measured at the DC bus was reduced to 5.7A at a 100V DC bus. The value was even smaller compared to the scenario in Figure 4.14, which was conducted at the 50V DC bus. 85

103 Figure 4.20 Switching transient of the top BJT gate drive. Ch1: DC bus voltage 100V/Div, Ch2: I lim1 5A/Div, Ch3: V Rlim1=5Ω 25V/Div, Ch4: I base_top 2A/Div Since the extra current flowing into base terminal is difficult to measure directly, another way to check for gate mis-triggering is by measuring V BE. For the SiC BJT, the typical turn on DC bias for V BE was between 4.5V to 5V. Therefore, if V BE were kept below 4.5V during the off state, then the device would remain off. Figure 4.21 shows that the new gate drive was able to keep V BE below 0V when another BJT was turned on. 86

104 0V V be_top V be_bot 0V V Rlim=5Ω I shunt (a) (b) Figure 4.21 Experimental result of V be at 100V DC bus when (a) bottom BJT turns on, (b) top BJT turns on Short circuit protection was implemented by detecting V CE when the switch was turned on. The simplified circuit schematic of desaturation of short circuit protection is given in Figure V ref I ref R D2 D1 Desat C BJT C PWM input B PWM output E Figure 4.22 Circuit schematic of short circuit protection 87

105 The proposed internal circuit was just one way to incorporate PWM and protection circuitry. The protection circuit did not include a short period latch-up, which can be implemented using a D flip flop. The latch-up would be cleared at the next rising edge; therefore the final latch-up was implemented on the control board. When BJT was turned on, a constant current source was applied from the Desat pin to BJT. The voltage across capacitor C slowly increased and created a blank time for V CE to settle down. The blank time reduced the chance of mis-triggering before V CE reached stabilization. After the blank time, the voltage between Desat and the ground built up, according Eq. (4.3). (4.3) where V D1, V D2, V CE and V R were the voltage drops across D1, D2, BJT, and R. V desat was compared to a reference voltage, V ref. If V desat were higher than V ref, then the comparator would put out a low signal and shunt down the PWM. By replacing V CE with I c R on, V desat with V ref and V R with I ref R in Eq. (4.3), the current-trip level can be determined according to Eq. (4.4). (4.4) where R on is the steady state on-resistance of BJT. Since V ref, V D1, V D2, and I ref are fixed values, the short circuit or over current protection level could be adjusted by changing R. In the SiC BJT based inverter, if R = 5.6kΩ, I ref = 250µA, and V D1 = V D2 = 0.6V, the estimated V ce to trigger the protection would be equal to 7.6 (5600 x 250e ) = 5V. A Buck circuit test was conducted to verify the estimated V ce and the experimental results of V desat versus V ce are given in Figure

106 Figure 4.23 Experimental result of desaturation protection circuitry. Ch1: V be 10V/Div, Ch2: V ce 5V/Div, Ch3: V desat 5V/Div In the figure, protection is initiated when V desat (orange) reaches 7.2V. The measured corresponding forward voltage drop of BJT (blue) was 5.2V which is slightly higher than the estimated 5V. This is likely due to the overestimated V D1 and V D2. Voltage blocking diodes, D1 and D2 were replaced with multiple resistors (to evenly distribute voltage stress) in series to improve the accuracy. PWM was turned off immediately and a fault signal was transmitted back to the control board to perform a proper PWM shut down. Since the gate drive board is normally placed very close to the power circuits, the input pin is usually quite susceptible to electromagnetic inference due to dv/dt and di/dt. In most cases, dv/dt would not cause severe EMI issues during testing because of the small distributed parasitic capacitances between the power device and the gate drive board. However, as the load current increased, higher noise magnitude was observed due 89

107 to magnetic coupling. According to the analysis in Appendix D, the coupled noise voltage can be described using Eq. (4.5). (4.5) in which the noise was caused by mutual inductance, M, frequency, ω and the current level in the noise source winding, I 1. The noise can be coupled to the gate drive input signal and cause gate mis-triggering if the noise level is higher than threshold values. In general, the gate drive input has a hysteresis loop to improve noise reduction. A hex inverting Schmitt trigger, as shown in Figure 4.24, will have a hysteresis loop, as depicted in Figure Figure 4.24 Logic diagram of hex inverting Schmitt trigger When V IN falls below V TH-, the Schmitt trigger output will be high. If the noise added to the low V IN signal is higher than V TH- + V H (or V TH+ ), then the circuit would emit a low voltage. V H is the hysteresis voltage which increases the input voltage threshold. Similarly, the output state will change to high if a noise spike is lower than V TH+ - V H (or V TH- ) during high input voltage. The switching mechanism described above is also depicted in Figure

108 5V Noise 1 Noise 2 Noise 3 V TH+ V OUT V H 0V V TH- V H V IN 5V V TH- V TH+ V IN V OUT Figure 4.25 Characteristic of hysteresis loop 0V Time (s) Figure 4.26 Hex Schmitt trigger input and output waveforms However, the Schmitt trigger could be limited by the noise fluctuation level, such as noise 3 in Figure The noise spike fell below V TH- and resulted in mis-triggering during output. If the duration of the noise is short or at a very high frequency, a simple RC filter can be installed, which causes a longer propagation delay and eliminates some narrow PWM pulses. Since the magnitude of noise was fixed, according to Eq. (4.5), the input signal could be amplified first by using a buffer or an open-collector type of circuit followed by a voltage divider, as shown in Figure V 1 V IN R 3 R 2 V 2 V 1 R 1 C 1 V OUT Figure 4.27 A simple circuit to minimize 91

109 As shown in Figure 4.27, the voltage divider reduced the original amplified signal, V 1 to an acceptable input voltage range (0-5V) to prevent the Schmitt trigger from mis-triggering. At the same time, the noise magnitude, V N was also reduced, according Eq. (4.6). (4.6) If V 1 = 15V and the peak input voltage is V 2 = 5V, then V N would also be reduced to one third. A small capacitor C 1 can be added close to the gate drive input to further improve noise reduction. This would be an ideal solution if the noise is coupled through V 1. In order to reduce the noise coupled through traces, R 1, R 2, and C 1 must be placed close to the IC input. 4.4 Control Circuits The PWM control signals were generated from the control board, which mainly included the digital signal processor (DSP), digital circuits for PWM conditioning and proper PWM shut down during a fault scenario, rotor position signal circuits, and analogto-digital (AD) conditioning circuits for current, voltage, and temperature measurement. The control board typically operates at 5V, 3.3V or lower and is located within the same set of power circuits. The major noise on-board in our experiment was generated from the high switching frequency and the speed of the digital circuits, oscillators, and communication circuits. The noise would affect the analog signal-to-noise ratio (SNR) through the power supply. Another noise source was coming from the external inputs, 92

110 including the rotor position signals, current, voltage, and thermistor signals, which are located deep inside the heatsink and motor windings. Since these sensors are typically located near the noise sources, the unwanted noise could easily couple into the control board through external cables radiatively during high power operation. This section will first discuss effective noise decoupling within the digital circuit, which is followed by considerations to achieve significant CM and DM noise deduction for AD conditioning circuits. Shielding effectiveness was also analyzed and verified via both computer simulation and experimental testing. Digital circuits, such as DSP and logic ICs, typically have higher transient currents due to the totem pole like output structure, as shown in Figure During the switching transient, the two transistors were partially turned on for a short period of time, which induced transient current, I d. L P1 L P3 V CC di DC C 1 di 1 V IN I L L P5 C P1 R L L P2 L P4 I d L P6 Figure 4.28 Transient currents of digital IC If the DC source is far away from the digital circuit, the stray inductances, L P1, L P2, L P3, L P4 will interact with di and induce voltage ripples (Ldi/dt) across the power supply. The magnitude of the voltage ripple can be reduced by decreasing the switching speed, dt and/or minimizing the loop inductances. Reducing dt is usually not desired; 93

111 Impedance (Ohm) therefore, minimizing loop inductance is a more practical approach which is implemented by adding a decoupling capacitor near the IC s power supply pin. The capacitance must be large enough to supply transient current and prevent voltage dips during digital IC switches. It would also provide a low impedance path for transient currents and minimize the noise injected back to the power supply. However, effective power supply decoupling becomes more challenging with the increasing clock frequencies and faster rise/fall times of digital ICs. The impedance curve for a typical 2.2µF, 0.1µF, 10nF, and 1nF ceramic capacitors used for noise filtering are shown in Figure 4.29, in which the resonance point for 2.2µF capacitor occurs much earlier than in other smaller capacitors due to larger C and ESL. The 2.2µF capacitor also has the highest ESL of the other three capacitors, which is expected to be less effective in noise reduction in the high frequency range in comparison to the other three capacitors Impedance of 2.2uF, 0.1uF, 10nF, and 1nF uF 0.1uF 10nF 1nF Frequency (Hz) Figure 4.29 Measured impedance for 2.2µF, 0.1µF, 10nF, and 1nF 94

112 Impedance (Ohm) One way to create an effective noise filter is to connect multiple capacitors with a small ESL in parallel. Figure 4.30 (a) shows the impedance when three 0.1µF capacitors are connected in parallel. Only one resonance at P3 (12MHz) was observed since all three 0.1µF capacitors have the same characteristics, as given in Figure Impedance of Parallel Capacitors 10 2 (a) (b) (c) (d) 0.1uF // 0.1uF // 0.1uF 0.1uF // 10nF // 1nF 2.2uF // 2.2uF // 2.2uF 0.1uF // 10nF // 2.2uF (P2) (P4) (P6) (P5) (P7) (P3) (P1) Frequency (Hz) Figure 4.30 Impedance of multiple capacitors connected in parallel (a) 0.1µF // 0.1µF // 0.1µF, (b) 0.1µF // 10nF // 1nF, (c) 2.2µF // 2.2µF // 2.2µF, (d) 0.1µF // 10nF // 2.2µF If the three capacitors are changed to 0.1µF, 10nF, and 1nF, the new impedances would have multiple resonances at P3-7, as shown in Figure 4.30 (b). P3, P5 and P7 correspond to the self resonances of 0.1µF, 10nF, and 1nF capacitors, respectively. The resonance point at P4 was caused by the interaction between ESL 1 in 0.1µF and 10nF impedance, as shown in Figure 4.31 (b). Since the impedance of 1nF was relatively high compared to 10nF and 0.1µF, the resonance frequency can be estimated by utilizing Eq. 95

113 (4.7). Similarly, the equivalent circuit for P6 is given in Figure 4.31 (c), where 1nF would resonate with ESL 1 //ESL 2 and ESL µF 10nF 1nF ESL 1 ESL 2 ESL 3 ESL 1 ESL 2 ESL 1 //ESL 2 ESL 3 C 1 C 2 C 3 C 2 C 3 (a) (b) (c) Figure 4.31 Equivalent circuit of (a) 0.1µF, 10nF, and 1nF connected in parallel, (b) resonant at P4, (c) resonant at P6 (4.7) According to Figure 4.31 (a) and (b), using 10nF and 1nF capacitors would actually degrade the decoupling performance, especially at P4 and P6. However, the self resonance at P7 due to 1nF would result in lower impedance compared to the other scenario. In some cases, larger capacitances are necessary to meet the high di/dt requirement for microcontrollers or high speed buffer ICs. Multiple ceramic capacitors, such as 2.2µF or higher, were used to reduce the voltage ripple and board size. When we compare Figure 4.30 (c) and (d), the mix capacitor combination contained several resonances at P2-5 as expected; however, it had lower impedance from 40 to 200MHz due to lower ESL. Based on this analysis, multiple capacitors with the same value and low ESL are preferred because they are more predictable and more efficient at 96

114 minimizing the resonance between ESL and other capacitors. The capacitors should be placed near the supply voltage pins in order to minimize the loop inductances as well. The current sensor output voltage span is not always within the analog-to-digital converter (ADC) input voltage range. In this case, the dynamic range of ADC would not be fully utilized. In addition, the sensor is located far away from the conditioning circuit and the output signal is transmitted through wires where noise can be coupled through an electromagnetic field generated by external noise sources or through the voltage supply. This could lead to errors in the readings for the feedback control loop and also increase the chance of damage being done to the ADC module if the noise spike is higher than the absolute maximum rating. In order to preserve the SNR of the low-level signals, an AD conditioning circuit using an operational amplifier (op amp) could be installed to achieve the required ADC input voltage span and noise filtering. An AD conditioning circuit, shown in Figure 4.32, was used to demonstrate the key elements affecting the SNR. 97

115 VCC VCC 0 R1 1k R2 1k 0 C1 0.1u 3 2 VCC U1A4 V+ + 1 OUT - 11 op amp V- 0 V_BIAS 0 C2 0.1u V- V+ V1 3.3Vdc 0 V_BIAS 0 0 V2 FREQ = 30e3 VAMPL = 0.5 VOFF = 0 V4 FREQ = 30e3 VAMPL = 0.5 VOFF = 0 R3 0.1 R7 0.1 V3 FREQ = 1000 VAMPL = 2 VOFF = 0 V5 FREQ = 1e6 VAMPL = 0.2 VOFF = 0 V+ V- C3 500p R5 15k R6 15k R4 10k U2A4 3 V+ + 2 R8 C k VCC 500p OUT 1 op amp V- 0 V- V_OUT V+ Figure 4.32 AD conditioning circuit with CM and DM noise consideration at signal input In Figure 4.32, V 3 represents the differential input signal from sensor. V 2 and V 4 are the CM noise voltage source, while V 5 represents DM noise. Since the peak of V 3 was pure AC and op amp was operating from a single power supply, the appropriate bias voltage would be half of the supply voltage to prevent output voltage clipping. If the ADC module were operating at 3.3V, then 1.65V bias voltage would maximize the ADC input resolution for the AC signal. The input and output voltage relationship can be derived using Eq. (4.8). (4.8) If R 5 = n R 4, R 6 = m R 8 and m = n, then Eq. (4.8) can be simplified into Eq. (4.9). 98

116 (4.9) To satisfy Eq. (4.8), n must be equal to m; however, R 5 and R 4 do not necessarily have to be equal to R 6 and R 8. The input terminal is said to be unbalanced if R 5 and R 4 are not equal to R 6 and R 8. To demonstrate CM noise immunity effectiveness for unbalanced and balanced input impedance, the circuit in Figure 4.32 was setup in PSPICE with CM noise injected from the input side. If R 6 = 15kΩ and R 8 = 10kΩ, the resistors for an unbalanced condition would be defined as R 5 = 1.5kΩ and R 4 = 1kΩ. The CM noise frequency and peak-to-peak voltage were set to 30kHz and 1V, respectively. The AC input signal had a frequency of 1kHz and a peak-to-peak voltage of 4V. The DM noise source, V 5 was removed for this test. Based on Eq. (4.9), the calculated output voltage for both cases was equal to 1.33V V = 2.98V. The simulation result of unbalanced and balanced input impedance is given in Figure 4.33 (a) and (b), respectively. In Figure 4.33 (a), a noticeable high frequency AC ripple was observed at V OUT, yet there was no significant high frequency noise in the balanced structure, as shown in Figure 4.32 (b). A Fast Fourier Transformation (FFT) of an unbalanced structure, given in Figure 4.32 (c), shows that approximately 0.1V peak noise occurred at 30kHz in addition to the desired output signal. CM noise reduction performance would be degraded if the positive and negative terminals of the op amp did not have the same input impedance. At higher frequencies, the stray inductance between sensor signal output and op amp terminal input would become not negligible. Therefore, the length of 99

117 the input traces must be kept as similar as possible for maximum CM noise rejection for all frequencies. V OUT (unbalanced) V BIAS Voltage (V) V IN (a) V OUT (balanced) Voltage (V) Voltage (V) V 0Hz V 1kHz (b) Time (s) V OUT (unbalanced) V 30kHz (c) Figure 4.33 Output voltage simulation result of (a) unbalanced, (b) balanced input impedance. (c) FFT result of unbalanced input impedance In addition to CM noise, the analog signal is also very susceptible to DM noise due to high frequency components in the power supply. Normally, DM noise occurs at frequencies much higher than the sensor s output signal, so a suitable C 4 can be added across R 8 to form a first order active low pass filter, as shown in Figure The size of 100

118 C 4 is based on the selected cutoff frequency, according to Eq. (4.10). The same capacitor also must be inserted across R 4 in order to maintain the same input impedance for both terminals. (4.10) A small RC low pass filter at the op amp output is recommended to remove any DM noise coupled into the trace between the op amp and the ADC input. The filter capacitor must be placed close to the ADC input to create a low impedance path for effective noise filtering. In addition to the noise generated by the digital circuits in the control board, more disruptive noise could be joined to the external signals, such as in the rotor position feedback, the thermistor enclosed in the windings for temperature measurement, and other external digital input and output signals. Shielded cable is normally used to provide noise reduction from the capacitive and magnetic effects. However, the shielding effectiveness can be greatly reduced with improper termination at both ends. A circuit configuration, shown in Figure 4.34, was setup to investigate the near field coupling effect of shielded cable. Conductor 1 carried the noise source, which could be the result of the three phase AC output cables, high frequency communication cables or the common reference frame. Conductors 2 and 3 carried low voltage signals, such as encoders and hall-effect position signals, etc. The two conductor outputs were connected to a high resistive load, which is equivalent to the IC input. An un-terminated shield was placed across conductors 2 and

119 Diameter of wire 1, 2, and 3 is 1mm Conductor 1 I 1 10mm Conductor 2 Conductor 3 I 2 I 2 Shielding layer R Load 1.5mm Diameter of inner shield 1.75mm Diameter of outer shield 2mm Figure 4.34 Electromagnetic effects of shielded cable A lumped circuit network was employed to represent the noise coupling effect. Parasitic capacitors were used to represent a time varying electric field between two conductors. If the magnetic field couples between two conductors, then a mutual inductance can be used to characterize the coupling effect. By applying this concept, the setup in Figure 4.34 can be transformed into an equivalent circuit in Figure a L 1 I 1 1b M 13 M 12 M 1sh C P1 2a L sh _ + V 1sh _ + V 2sh _ V 3sh + 2b R sh 3a I 2 M sh2 M sh3 L 2 C P2 + V 12 + V sh2 3b I 2 M 23 L 3 C P3 _ + + V 13 V sh3 _ Figure 4.35 Equivalent circuit of shielded conductors 102

120 In Figure 4.35, C P1 represents the parasitic capacitance between conductors 1 and 2. C P2 and C P3 represent the parasitic capacitances between the shield and the inner conductors. L 1, L 2, L 3, and L sh are the self inductances of conductors 1, 2, 3, as well as the shield. When there is current flowing through conductor 1, there will be mutual inductances, M 1sh, M 12, and M 13 coupling into the shield, conductor 2 and 3, respectively. If both ends of the shield are not connected to the ground, then C P1, C P2, and C P3 will provide a path to allow I 1 to flow into the load. In addition to capacitive coupling, mutual inductances, M 1sh, M 12 and M 13 will also induce a voltage drop in the shielding, conductors 2 and 3, according to Eq. (4.11). where X = sh, 2 and 3 (4.11) To minimize the capacitive coupling effect, one end of the shield was connected to the ground to form a path to bypass the noise current instead of via signal conductors. However, the induced voltages in conductors 2, 3 and the shield due to M 12, M 13, and M 1sh remained un-changed. If the other end of the shield was also connected to the ground, then I sh would be induced due to V 1sh, as given in Eq. (4.12). (4.12) In which R s is the equivalent resistance, including the shielding layer and ground connection. L sh is the self inductance of the shield. Due to I sh and M sh2, V sh2 was generated in conductor 2 with the opposite polarity of V 12 due to the opposite current direction between I 1 and I sh. The total noise on conductor 2 was changed, as seen in Eq. (4.13). 103

121 (4.13) The self inductance of the shield is defined in Eq. (4.14). If all the flux generated by the shield, Φ sh encircles the inner conductors, the mutual inductance between the shield and inner conductors would be equal to Eq. (4.15). M 1sh would also have similar value to M 12 and M 13 since the distance between the shielded cable and conductor 1 is approximately equal. (4.14) (4.15) Ideally, noise V 2N, in Eq. (4.13), could be reduced to 0V if R s = 0Ω, L sh = M sh2, and M 1sh = M 12. Therefore, the noise generated by capacitive and inductive coupling can be minimized when the cable is properly shielded. To verify the shielding analysis, the PSPICE computer simulation based on the test setup in Figure 4.34 was performed. The parameters of self and mutual inductances and wire resistances were obtained through Q3D FEA, as shown in Table 4.1. The result confirmed that the mutual inductance, M 1sh (363nH) was approximately equal to M 12 (363nH) and M 13 (362nH). The self inductance L sh (527nH) also had a magnitude approximately equal to M sh2 (529nH) and M sh3 (- 529nH). 104

122 Wire 1 Wire 2 Wire 3 Shield (Ω) (nh) (Ω) (nh) (Ω) (nh) (Ω) (nh) Wire Wire Wire Shield Table 4.1 Extracted self and mutual inductance of test setup in Figure 4.34 The coupling coefficient, k, between two conductors can be calculated using the method given in Section 3.4. The desired input signal was represented with a 10kHz square waveform switching from 0 to 5V. The introduced noise in conductor 1 was switching at 100kHz at 50% duty cycle. The final PSPICE model is given in Figure Figure 4.36 Equivalent circuit of the shielded cable Figure 4.37 shows the simulation result for three shielding configurations. When the shield was not connected to the ground at both ends, the noise detected by the load 105

123 side resistor had a peak to peak voltage of V NPP = 1.2V, as shown in Figure 4.37 (a)., V NPP was reduced to 0.6V, as illustrated in Figure 4.37 (b), when one end of the shield was grounded on the R load side. When both ends of the shield were grounded, as in Figure 4.36, V NPP was further decreased to 0.03V, as depicted in Figure 4.37 (c). Each noise spike occurred during the switching transient of the introduced noise. Since it was switching at 100kHz at 50% duty cycle, the period between each spike was 5µs. (a) Both end are not grounded (b) Grounded at one end (c) Grounded at both ends Figure 4.37 Simulation result of magnetic coupling with shield (a) un-grounded, (b) single end grounded, (c) both end grounded An experiment was performed to verify the proposed shielding analysis. The low voltage signal was generated using a function generator switching at 10kHz from 0 to 5V. The signals, including the segment of interest and coupled noise, were measured across the 10kΩ load resistor. The cable was placed near the GaN based switched-capacitor circuit, which was switching at 304kHz at 50% duty cycle. The experimental results of the three shielding configurations discussed above are given in Figure The measured V NPP when both ends of the shield were not grounded, shown in Figure 4.38 (a), was 1.6V, which was the highest of the three scenarios. When one end of the shield 106

124 was connected to the load side ground, as shown in Figure 4.38 (b), V NPP was reduced to 0.7V. By connecting both ends of the shield to the source and load side ground, V NPP was further reduced to 0.4V. Despite the fact that the noise could never be completely removed due to the unshielded portion between the function generator output and the cable input, this experiment confirmed that a high percentage of noise reduction is possible when the cable is properly shielded. The uncovered portion should be minimized in order to achieve a maximum shielding effect. 4µs V NPP = 1.6V V NPP = 0.7V (a) 1V/Div (b) V NPP = 0.4V (c) Figure 4.38 Experimental result of magnetic coupling with shield (a) un-grounded, (b) single end grounded, (c) both end grounded 107