Original Input Stage frequency response measurement verification

Transcription

1 Original Input Stage frequency response measurement verification By: branadic DUT: WELEC W04A, FW:..OS Measurement equipment: Signal Generator Rhode & Schwarz 00 khz 000 MHz SMG, Oscilloscope TDS504B It s known, that there are efforts to improve the analogue input stages of the WELEC oscilloscope for better performance. Walter started these improvements by replacing the OPA656 against OPA657. As it is necessary to confirm his results, I made following measurements for verification.. Some words at the beginning The completely analogue signal path was measured by setting a sinusoidal signal of constant amplitude overall frequency to the input of the channel. Measurements where then exported with the screenshot function and analysed with Qtoctave. Therefore the amplitude peak to peak was specified searching minimum and maximum in the exported data and normalized to 0 db at 00 khz. The frequency response of my ch. looks as follows: Picture : Frequency Response Ch. Comparing this result with Walters Original Input Stage frequency response measurement his measurements can t be confirmed. But there is an interesting fact. Walter removed R0, disconnected the pin of the MAX4704 and measured the frequency response of the stage with the three AD83 setting a signal directly at the input of the first AD83, with the following result:

2 Picture : Frequency Response of AD83 stage measured by Walter As you can see, the characteristic looks nearly the same as above. In further measurements, after replacing the OPA656 against OPA657, Walter showed the influence of a ~50 khz signal which was superimposed on his measured input signal. I could find out that this signal comes from the inverter part of the TFT-LCD. Both wires (pink/white) radiate and an influence by capacitive coupling can t be excluded. More probably this result is an influence of inductive coupling. Walter removed the shielding of channel. Close to this channel are two inductances and a bulky circuit path of the inverter. Measurements with a DIY sampling probe for magnetic fields showed radiations that could couple into the input stage and influence the signal dramatically. For the validation of Walter s improvement I decided to make all measurements on channel 3, because first measurements on all channels showed, that ringing by the value of the adc_change_reg in FW..OS.09 is still present on channel 4. Channel 3 is furthermore far away enough from the influence of the inductance and easy to reach for modification.. Complete signal path of Channel 3 original input stage First of all, I characterized the completely analogue signal path of the channel, to see what is The base of operations. Measurements were made with a 50 ohms load resistor at the input of channel 3 for matching the output of the signal generator.

3 Picture 3: Frequency Response Ch.3 3. Reduced signal path of Channel 3 original input stage After removing R0 and disconnecting the MAX I found it easier to disconnect the input pin 8 of the AD 83 from the rest of the circuit, to isolate it and set the signal directly to this pin instead of cutting the signal path to the MAX4704 or to de-solder the pin of the MAX measurements were repeated setting the sinus signal of constant amplitude through a coax cable directly to the input of the first AD83. In the following graphic the frequency response of the AD83 stage can be seen.

4 Picture 4: Frequency Response of the AD83 stage This result is similar to the results of Walter's measurements. The frequency response is probably an effect of the used analogue switches NC7SBU357P6X forming filters in the different gain stages. A device depending effect is hereby excluded. Scale factor OPA656 st AD83 nd AD83 3rd AD83 Complete gain 50mV/500mV/5V,5,5 0mV/00mV/V 4 0mV/00mV/V 8 4. Noise So the question is, what about noise? To better assess the results, take a look at the table above. Together with the values for the input signal noise can be discussed. input signal: range 5.0mV (amplitude of Ueff) = sqrt() 5.0 mv 4.7 mvpp range 0mV (amplitude of Ueff) = sqrt() 0 mv 8.8 mvpp range 5 35.mV (amplitude of Ueff) = sqrt() 35. mv 99.8 mvpp resulting signal at ADC: range 4.7 mvpp 3.36 mvpp range 8.8 mvpp 3.4 mvpp range mvpp mvpp

5 Picture 5: readout of the device memory (8k) Noise can be extracted by searching for min and max in the data. With the following expression the digital bit values are converted to analog voltage values: analogue_voltage = (55 digital_value -8) 0.65 / 56 The first part of the expression (55 digital_value) mirrows the digital values, because while data correction signal is mirrowed in the memory. The 8 sets the signal around zero line. The last expression converts the data into analogue voltage. Extracted voltage peak-peak: range 9.39 mvpp range.07 mvpp range mvpp If we now subtract the resulting signal at ADC from the extracted voltage peak-peak we get the noise in mvpp by the AD83 gain stage. Noise: range 9.39 mvpp mvpp = 6.03 mvpp range.07 mvpp mvpp = 8.93 mvpp range mvpp mvpp = mvpp 5. Result The frequency behaviour and noise of the AD83 stage shows that further improvement without touching the AD83 gain stage makes no sense and gives different options: no more touching the hardware, just improving firmware and VHDL piggyback board with optimised gain stage further, a complete new analogue/fpga board

6 The last both option necessitate that optimisation starts at the AD83 gain stage, before the OPA656 can finally be replaced by OPA657. This stage could be replaced by a programmable amplifier, such as LMH655 or AD8670. Therefore a separate board needs to be designed. Replacing the OPA656 by OPA657 is still necessary, because the first stage should have maximum gain, to increase SNR. OPA657 could be set fixed to gain = 0. At least there are three usable control wires, one at the OPA656 switching between gain = and gain =,5 and two at the switches of the AD83 gain stage. This control wires could be used, supported by the firmware, to control the gain of a programmable amplifier. branadic