Compared deep class-ab and class-b ageing on AlGaN/GaN HEMT in S-Band Pulsed-RF Operating Life

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1 Compared deep class-ab and class-b ageing on AlGaN/GaN HEMT in S-Band Pulsed-RF Operating Life J.-B. Fonder a, O. Latry b,, C. Duperrier a, M. Stanislawiak d, H. Maanane d, P. Eudeline d, F. Temcamani c a ETIS UMR 851 CNRS, ENSEA, 6, Avenue du Ponceau 95 Cergy-Pontoise,FR b GPM UMR 6634 CNRS, Université de Rouen, Avenue de l Université -BP Saint Etienne du Rouvray, FR c LaMIPS, CRISMAT UMR 658 CNRS, NXP, 2 Esplanade Anton Philips BP Colombelles, FR d THALES Air Systems, Zone Industrielle du Mont Jarret, 7652 Ymare, FR Abstract AlGaN/GaN HEMTs are on the way to lead the RF-power amplification field according to their outstanding performances. However, due to its relative youth, reliability studies in several types of operating conditions allow to understand mechanisms peculiar to this technology and responsible for the wearing out of devices. This paper reports the reliability study on two power amplifiers using NITRONEX AlGaN/GaN HEMT. Based on results of a previous study of 128 hours in standard operating conditions wherein no evolution of electrical parameters have been observed, two ageing tests in deep class-ab (432 hours) and class-b (795 hours) are performed under pulsed-rf operating life at high drain bias voltages and saturated operation. This study shows a drift in RF performances which is linked with the evolution of electrical parameters (R DS ON, g m and V P ). Similar kinetics and amplitude of degradations are observed revealing quasi similar contribution of thermal effects in both cases. Degradations are supposed to be related to trapped charges phenomena induced by high voltage operating conditions. Although, several results attest to this hypothesis, a part of the evolutions seems to be linked with structural changes. Keywords: AlGaN/GaN HEMT, Power amplifier, Reliability, RADAR, High V DS ageing 1. Introduction Over the last decade, we have assisted at many advances of the AlGaN/GaN HEMT technology. Due to the intrinsic properties of the GaN material and widely high energy band-gap semiconductors, such transistors can take part to the power-frequency challenge. Indeed, raw performances of recent AlGaN/GaN HEMT reach about ten times these reached by common technologies such as Si and GaAs transistors [1] which is the consequence of high breakdown voltages, great electron mobility and good thermal conductivity (for HEMT on SiC substrate). This leads to high power density devices allowing high frequency performances due to the shorter gate length (i.e. lower inner capacitive effects), and robust devices since they can cope with high Voltage Standing Wave Ratio (VSWR). That said HEMT AlGaN/GaN is a good candidate for medium to high power radio-frequency amplifiers found in telecommunication base stations, medical equipments or RADAR Corresponding author address: olivier.latry@univ-rouen.fr (O. Latry) T/R modules [2]. Another advantage of the high breakdown voltage power devices is, from the power amplifier designer point of view, the greater load impedance, making the matching networks design easier. Nevertheless, this technology suffers from some drawbacks inherent in fabrication process and material purity. Actually, GaN epitaxial layers and substrate interfaces are not free of defects which lead to a high density of charge traps, reducing the RF power performances of the device [3, 4]. This power slump phenomenon (reversible or not) induced by traps or crystalline defects is about to be explained [5]. Furthermore, recent researches tend to demonstrate the importance of the piezoelectric nature of AlGaN/GaN material [6] under high drain voltage and leading to permanent damages. Some technical solutions have been proposed to address these problems with more or less success: field plates, passivation layers, gate shaping, gate annealing [7, 8, 9]. In order to describe and quantify such phenomena, ageing benches are used to monitor relevant figures of merit. It is important to choose accurately ageing profile (DC-High Temperature Operating Life, RF-High Temperature Op- Preprint submitted to Microelectronics Reliability March 5, 212

2 erating Life, thermal storage, Electromagnetic Induced stress... ) to emphasize one type of degradation or another. The purpose of this paper deals with the ageing of GaN based power amplifiers in RADAR operating condition (i.e. pulsed RF, non linear) using the commercial AlGaN/GaN HEMT NITRONEX NPTB5 in class B and class AB configuration at 3GHz. The study focuses on degradation induced by enhanced drain bias voltage on pulsed RF performances. In a first part, the experimental setup will be described, then the characterization results on aged devices will be detailed to be discussed. Finally an explanation on RF performances degradation will be proposed. 2. Experimental setup 2.1. Power amplifier design Two identical power amplifiers have been designed around the NPTB5 power transistor from NI- TRONEX. This.5 µm gate length ceramic packaged power transistor is characterized for DC to 4GHz continuous wave operation and has no internal prematching circuit. Coming from the NRF1 GaN-on-Si process platform it features a source connected field plate, S i x N y passivation and gate anneal [1]. Saturated power peaks at approximately 5 W under 28V drain bias voltage. V DS breakdown has been measured greater than 11V. The black-box model provided by the manufacturer has allowed computer-aided design with ADS Agilent software, so as to meet the targeted working conditions: a maximum output power with the highest reachable power added efficiency. Impedance research had been carried out with simulated load pull technique at 3GHz and 28V drain bias voltage. Input and output matching circuits were designed with microstrip impedance transformers. Circuits are etched on Rogers Duroid RT61.2 Cu-clad substrate (ǫ r =1.2, h=.63mm) and mounted on brass base-plates. Low frequency stabilization is ensured by 1Ω resistor in series with gate bias tee. Pulsed-RF performances at 25 C, under V DS =28V and I DQ =ma are shown in Fig. 1. The saturated output power reaches 5W while power gain comes to approximately 9dB. The Power Added Efficiency (PAE) peaks at 53% Test bench and protocol description The test bench [11] is based on a central unit which can test several devices simultaneously. It consists in a computer driving control and data-recording peripherals (power supplies, triggers, memories). Power modules, made up of thermally regulated Cu base plates on 2 Figure 1: Pulsed-RF performances of amplifiers for V DS = 28V, I DQ = ma, T f lange = 25C. Gain (dots), Output power (squares), Power Added Efficiency (triangles). which test amplifiers are fixed and thermally coupled, are driven by this central unit. RF part consists in a signal generator, providing RF pulses triggered by the central unit, a power amplifier to ensure sufficient input power level on each devices, a power divider, couplers and circulators to measure input and reflected power. The output of devices under test is connected to a 4dB attenuator, itself connected to a power sensor. During the test, RF power, current, voltage and temperature are monitored and stored in memory. Ageing can be performed both in L-Band ([1 ; 2]GHz) [12] and S-Band ([2 ; 4]GHz). Previous ageing tests had been carried out on these amplifiers which consisted in 128 hours of run with a flange temperature of 8 C, 28V drain bias voltage, no bias current and 1dB gain compression at 3GHz with pulsed RF input power. At the end of this first study corresponding to RADAR type operating condition, it turns out that no decrease of either RF or DC performances of the transistor have been noticed [13]. The new protocol tends to increase device stress by raising the drain bias voltage and the input power level until a small amount of gate current is measured. This current is caused by the large voltage swing on gate which turns the gate-source Schottky junction on. These operating conditions corresponding to a compressed mode allow an accelerated RF life test under high electric field [14, 15]. During the test, only RF signal is pulsed, while gate and drain voltages are DC. Two amplifiers have been run under different bias conditions: V DS = 45V and I DQ ma at flange temperature of 2 C for class-b amplifier. V DS = 45V and I DQ = 2mA at flange tempera-

3 1 1 P OUT (t) / P OUT () (%) 95 9 Class B Class AB Model I D (t) / I D () (%) Class B Class AB Model Time (h) Time (h) Figure 2: Evolution of relative RF output power. ture of 2 C for class-ab amplifier. The test protocol is detailed below: Pulsed RF and compressed operating condition (with a minimum of 3µA average gate current). 45µs RF pulses with a period of 3ms. 3 GHz operating frequency. RF characterization: P OUT, P IN, I D, I G are monitored during the test. DC characterization: Pulsed I D = f (V DS, V GS ) before and after each stress at 2 C. Small signal RF characterization: S-parameters measurements between 5MHz and 4GHz at various bias points before and after each stress at 2 C. Relaxation post-stress measurements : DC characterization after approximately 4 hours (6 months) without any electric bias at 2 C and after depackaging and light exposition. In these operating conditions, RF output power peaks at twice the rated output power (1W). The input power is kept constant during stress test. The average dissipated power of devices reaches about 12W under 2 C flange temperature. 3. Results 3.1. RF power measurements All results show the same trends on both amplifiers. Fig. 2 depicts the relative output power which decreases 3 Figure 3: Relative average drain current evolution during stress test in percentage. PAE (%) Class B Class AB Time (h) Figure 4: Power Added Efficiency evolution during stress test in percentage. of about.45db (1%) after 5 hours. Relative average drain current is affected the same way but drops by only 6% (Fig. 3). The linked decrease in output power and average drain current involves a drop of about 6% on power added efficiency (PAE) visible in Fig. 4. Moreover, a large increase (+15%) of average gate current has been noticed during the stress test (Fig. 5) Pulsed I-V measurements RF power measurements have been supported with pulsed I V characteristics on fresh and aged transistors (Fig. 6). These curves presented hereafter are relative to class-ab amplifier since same trends have been observed on class-b amplifier with similar drifts. From these measurements, transfer characteristics I D = f (V GS ) are extracted for V DS = 3.5V, 7.8V and 25V to

4 2 15 I g (%) 1 5 Class B Class AB Time (h) Figure 5: Average gate current evolution during stress test in percentage. 5 4 V GS =.V -.2V -.4V Fresh _ Stressed 3 -.6V I D (A) V -1.V V DS (V) -1.2V -1.4V -1.6V Figure 6: Pulsed I-V characteristics for a fresh and an aged transistor. Quiescent bias point of V DS = 28V, V GS = -2.5V (pinch-off voltage at -1.9V). V GS voltage go from -1.6V to V with a.2v step highlight changes on the transconductance g m and/or on the pinch-off voltage V P. At first sight, one can observe that the knee of the I V curves is more pronounced on aged transistor. It is the consequence of the weakening of the transconductance g m in this region (low drain voltage, high drain current). For a drain voltage of 3.5V, g m has lost 5.8% of its original value. At V DS = 7.8V, g m is still impacted by a drop of 2.9% whereas at higher V DS, no impact on g m has been found. On the other hand, in the ohmic region, the increase of R DS ON (+8.3%) emphasizes this round knee phenomenon. At last, it can be noticed a slight change in V P in the high drain voltage-low drain current region. Actually, V P is shifted toward negative voltage since drain current is higher for the stressed device. At 4 Figure 7: [S] parameters measured for V DS = 5V and V GS = 1.16V (I D = 4mA) of fresh transistor (solid line) and aged transistor (dashed line). V DS = 25V it has been measured a shift of -27mV. This effect fades out as V DS increases (so as thermal dissipation). V P variations usually reported in literature are positive drifts [9, 14, 16, 17, 18] whereas it is here a negative shift. This phenomenon is responsible for an increase of quiescent drain current of about 4% (from 2mA to 28mA for class AB amplifier) Small signal measurements S-parameters have been carried out on fresh and aged transistors for different bias points: V DS = V, V GS = V V DS = 5V, V GS = -1.16V (I DQ = 4mA) V DS = 14V, V GS = -1.46V (I DQ = 2mA) V DS = 22V, V GS = -1.45V (I DQ = 2mA) As mentioned before, a negative shift on V P has occurred so that drain bias current is higher on aged transistor than the fresh one, for the same V GS. Considering

5 this point, S-parameters measurements have been made with constant V GS. No evolution of S-parameters has been observed in open-channel cold FET operating condition (V DS = V, V GS = V) pointing out that passive and linear elements of the package and die haven t been modified by the stress test. At a second bias point (V DS = 5V, V GS = -1.16V), a slight change on S 21 is noticed Fig. 7. This shift impacts especially the S 21 magnitude (approximately -.4dB at 3GHz) whereas the phase remains quite unchanged. It confirms observations on pulsed I V measurements: g m is weakened in this low drain voltage region. But, it also shows that the output capacitance C DS is barely affected which is confirmed by S 22. The same assessment can be done for the input capacitance C GS since no evolution happened on S 11. S-parameters measurements for both last bias points (V DS = 14V, V GS = -1.46V and V DS = 22V, V GS = -1.45V) haven t revealed significant changes confirming that gm is not impacted on high drain voltages. I G (A) -2x1-5 -4x1-5 -6x1-5 -8x1-5 After stress After 4 hours of relaxation After depackaging and illumination Before stress V DS (V) Figure 8: Time dependence of reverse gate current Relaxation measurements In order to detect a reversible ware out mechanism, I V measurements have been done on aged transistors after a relaxation period of 4 hours. During this period, the devices were at ambient temperature (2 C) without any electric bias. Then the ceramic cap of the device s package has been removed with a thermomechanic technique (T Package 12 C), exposing the transistor s die to the light. The same I V measurements as in paragraph 3.2 have been performed. Fig. 8 depicts the inverse gate current which is reduced by a magnitude of 8 after the stress tests. However, this current tends to recover its original value with time and light exposition. On the other hand, Fig. 9 describes the time dependence of V P. Although a shift of -27mV has been noticed on V P directly after the stress test, this drift reaches -6mV after a 4 hours relaxation period on the depackaged device. I D (A) After depackaging and illumination After 4 hours of relaxation After stress Before stress 4. Discussion 4.1. About the similar behaviour of class B and AB amplifiers RF power measurements point out similar dynamics and amplitude of degradations on both amplifiers. However, the dissipated power must be higher on class- AB amplifier (9W at idle) but power added efficiency of class-ab amplifier remains close to the class-b one which means that quiescent drain current I DQ during V GS (V) Figure 9: Time dependence of V P.

6 .2.15 A B m n Table 1: Fitting coefficients for output power. I DQ (A).1.5 I DQ without RF I DQ with RF Recovery time to I DQ without RF Time (s) Figure 1: Quiescent drain current drop and recovery under RF excitation. pulsed-rf operation (i.e. between pulses) is far smaller than in pure DC operation. Actually, drain current has been measured with a Hall probe showing a strong dependence between I DQ and RF input power: the greater RF input power, the smaller I DQ to such an extent that operating condition is moved to class B when input power reaches those of stress test. Fig. 1 illustrates this phenomenon for a 1 db compression input power and I DQ = 2mA. Furthermore, current collapse occurs very quickly: one RF pulse is enough to reduce I DQ. On the other hand, the recovery of I DQ after pulsed-rf operating condition can take several seconds and is linked with RF input power: the greater RF input power, the longer the I DQ recovery. There is an indication that trapped charges are responsible for this behaviour given the asymmetric nature of capture/relaxation time constants. Further measurements (not shown) have been carried out to correlate these effects with respect to gate voltage. Actually, it has been noticed that drain voltage has quite no effect which proves that this gate lag phenomenon is related to surface traps [4, 19, 2]. Finally, same wareout behaviours are obtained due to the trapping effects which weaken the quiescent drain current. Class AB devices are pulled down in a non-dissipated power configuration between RF pulses. Thus, thermal state is the same for class B and class AB devices About the origin of degradation Measurements made after stress test have revealed similar ageing behaviour for both power amplifier whatever the operating class. Regarding the decrease of RF output power, two phenomena are responsible: the g m drop in the low voltage high current region of 6 I V curves to which may be added the increase of R DS ON. The combination of these effects leads to a more pronounced knee shape reducing maximal drain current and drain voltage swings described by the load cycle and finally output power. Actually, g m and R DS ON changes are known to be a signature of trapped electrons as it has been already mentioned in [14, 16, 18, 2]. This assumption will be confirmed hereafter. Both relative output power and average drain current are modeled by a power law functions versus time. Relative average drain current: I D (t) I D () = A tn (1) Relative output power: P OUT (t) P OUT () = B tm (2) P OUT () and I D () stand respectively for the initial output power and the initial average drain current. A, B, m and n are listed in table 1. From table 1 we can apply the following relations: B A 2 (3) m 2 n (4) It means that average drain current and output power are linked with a square relation during the whole test. P OUT (t) P OUT () = Moreover we have : ( ) 2 ID (t) (5) I D () P OUT (t)=r LOAD I OUT (t) 2 cos(ϕ(t)) (6) where I OUT (t), R LOAD and cos(ϕ(t)) are respectively the RMS value of the current flowing through the load, the load resistance and the power factor of the amplifier. The latter is related to the load cycle surface. Since RF input power remains the same during the test, the transistor conduction angle stays constant. In this case there is a proportionality relation between the average drain current I D and the RMS current flowing through the load I OUT in such a way that : P OUT (t) P OUT () = ( IOUT (t) I OUT () ) 2 (7)

7 I GD (A).1 1x1-2 1x1-3 1x1-4 1x1-5 1x1-6 1x Extracted Schottky barrier Height multiplied by q Φ B =1.22eV (fresh) Φ B =1.11eV (stressed) Fresh Stressed V GD (V) Figure 11: Gate-drain junction I V curves for a new device and an aged device. In other words we have : cos(ϕ(t)) = cst (8) This indicates that no load mismatching (i.e. a load cycle opening) occurred during the stress meaning that output reactive elements of the transistor may not have changed. Thus the transistor s output admittance seems to be the same all along the test which has been observed in paragraph 3.3. Then, an impressive increase of average gate current has been observed during the stress test. This current can flow from the gate to the source or from the gate to the drain when enough voltage variation (i.e. RF input power) is applied to the gate. Even if gate-source and gate drain junction curves are affected the same way on aged devices, I V measurements on aged and fresh transistors have revealed a behaviour change. The threshold voltage is reduced on the aged device (Fig. 11) meaning that the barrier height has decreased during the stress test. This barrier height extracted for fresh and aged device is reduced by.1ev. This drop is due to the interfacial layer modification of the Schottky contact. It has been reported in previous work mentioned in [17]. Moreover, the existence of high electric fields induced by enhanced drain bias voltage and large V DS swings makes the trapping of hot electrons easier in the AlGaN layer near the gate edge on drain side [4, 8, 19, 2, 21, 22]. This hypothesis is confirmed by a significant reduction of reverse gate current (Fig. 8) [6]. This current tends to recover after a long period of relaxation (4 hours) and with heat and light illumination which confirms the presence of trapped carriers. 7 We also observed a negative shift of the pinch-off voltage V P which is at first glance not consistent with the trapped electrons hypothesis. In this last case, the V P shift would have to be positive according to [9, 14, 16, 17, 18]. In fact, these two phenomena are occurring. V P V P V P V P V P V P Stress period Shift Shift Shift Relaxation period (a) (b) Shift (c) Shift 7 h 4 h Illumination t Irreversible t Reversible Total Figure 12: Synoptic of coupled phenomenon impacting V P (V P stands for the initial value of V P ) : irreversible negative shift (a), reversible positive shift (b) and resultant of both contribution (c). If we carefully examine Fig. 9 we notice that V P becomes more and more negative even after the stress test (Fig. 12c) whereas there is no more electric field to trap charges. This indicates that there is a trapped charges release (Fig. 12b) merged with another nonreversible phenomenon which has induced a strong negative shift on V P during the stress test (Fig. 12a). This phenomenon must be related to the Schottky contact modification. Investigation are in progress to confirm it. Since this negative V P shift is greater in modulus than the positive one related to trapped charges, the resultant contribution on V P is negative but exhibits the time, heat and light dependence of the electron trapped reversible degradation. 5. Conclusion Two 5W-class amplifiers using commercial power transistors NITRONEX NPTB5 have been designed and aged under saturated pulsed-rf operating life with enhanced drain bias voltage. The devices were biased in class-b and deep class-ab. These tests have t

8 lead to an RF output power drop of 1% for both amplifiers going with an associated drain current reduction. A specific device characterization (RF, I-V, small signal) has showed that the decrease of g m and the rise of R DS ON seem to be the main causes of these degradations. Furthermore, a huge average gate current increase has been observed during the stress and was found to be correlated with the drop of the Schottky barrier height of the gate. Investigations around the gate Schottky contact have permitted to identify two coupled ware out mechanisms implying pseudo-reversible degradations. The reversible part is assumed to be related to surface traps while the irreversible one seems to come from a physical contact change. Finally, transient tests have also pointed out the contribution of these gate and surface traps on the bias point when large voltage swing is applied to the gate, thus explaining the similarity between class-b and deep class-ab ageing results. Acknowledgments The authors would like to acknowledge THALES Air Systems engineers for their advices on the design and realization of test amplifiers. This work is supported by MOVE O cluster in the AUDACE project, Conseil Général du Val d Oise and Agglomeration de Cergy Pontoise. References [1] Wu, M. Moore, A. Saxler, T. Wisleder, and P. Parikh. 4-W/mm Double Field-plated GaN HEMTs. Device Research Conference, pages , June 26. [2] R. Therrien, S. Singhal, J. W. Johnson, W. Nagy, R. Borges, A. Chaudhari, A. W. Hanson, A. Edwards, J. Marquart, P. Rajagopal, C. Park, I. C. Kizilyalli, and K. J. Linthicum. A 36mm GaN-on-Si HFET producing 368W at 6V with 7% drain efficiency. Electron Devices Meeting, 25. IEDM Technical Digest. IEEE International, pages , December 25. [3] S. De Meyer, C. Charbonniaud, R. Quere, A. Campovecchio, R. Lossy, and J. Wurfl. Mechanism of power density degradation due to trapping effects in AlGaN/GaN HEMTs. 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