HD74LS193RPEL. Synchronous Up / Down Binary Counter (dual clock lines) Features. REJ03D Rev.2.00 Feb

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1 Synchronous Up / own Binary Counter (dual clock lines) RJ Rev.2.00 Feb Synchronous operation is provided by having all flip-flops clocked simultaneously so that the output change coincidently with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes, which are normally associated with asynchronous (ripple clock) counters. The outputs of the four master-slave flip-flops are triggered by a low-to-high-level transition of either count (clock) input. The direction of counting is determined by which count input is pulsed while the other count input is high. This counter is fully programmable; that is, each output may be preset to either level by entering the desired data at the data inputs while the load inputs is low. The output will change to agree with the data inputs independently of the count pulses. This feature allows the counters to be used as modulo-n dividers by simply modifying the count length with the preset inputs. clear input has been provided which forces all outputs to the low level when a high level is applied. The clear function is independent of the count and load inputs. The clear, count, and load inputs are buffered to lower the drive requirements. This reduces the number of clock drivers, etc., required for long words. This counter was designed to be cascaded without the need for external circuitry. Both borrow and carry outputs are available to cascade both the upand down-counting functions. The borrow output produces a pulse equal in width to the count-down input when the counter underflows. Similarly, the carry output produces a pulse equal in width to the count up input when an overflow condition exists. The counters can be easily cascaded by feeding the borrow and carry outputs to the count-down and count-up inputs respectively of.the succeeding counter. Features Ordering Information Part Name H74LS193P ILP-16 H74LS193FPL H74LS193RPL Package Type pin SOP-16 pin (JIT) SOP-16 pin (JC) Package Code (Previous Code) PRP0016-B (P-16FV) PRSP0016H-B (FP-16V) PRSP0016G- (FP-16NV) Note: Please consult the sales office for the above package availability. Package bbreviation P FP RP Taping bbreviation (Quantity) L (2,000 pcs/reel) L (2,500 pcs/reel) Rev.2.00, Feb , page 1 of 11

2 Pin rrangement s ata B Input QB Q QB Q B Clear V CC ata Clear Inputs Inputs Count own Count Up 4 5 Count own Count Up Borrow Carry Borrow Carry s s QC Q 6 7 QC Q Load C Load ata C Inputs GN 8 9 ata (Top view) Rev.2.00, Feb , page 2 of 11

3 Block iagram Borrow ata Input own Count Up Count Q T Q Carry Q ata Input B QB T QB QB ata Input C QC T QC QC ata Input Clear Q T Q Q Load bsolute Maximum Ratings Item Symbol Ratings Unit Supply voltage V CC 7 V Input voltage V IN 7 V Power dissipation P T 400 mw Storage temperature Tstg 65 to +150 C Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Rev.2.00, Feb , page 3 of 11

4 Recommended Operating Conditions Item Symbol Min Typ Max Unit Supply voltage V CC V current I OH 400 µ I OL 8 m Operating temperature T opr C Clock frequency ƒ clock 0 25 MHz Pulse width t w 20 ns Setup time (Clear) t su (CLR) 40 ns Setup time t su 20 ns Hold time t h 3 ns lectrical Characteristics Input voltage voltage Input current Item Symbol min. typ.* max. Unit Condition V IH 2.0 V V IL 0.8 V 2.7 V 0.4 I OL = 4 m V 0.5 I OL = 8 m (Ta = 20 to +75 C) V CC = 4.75 V, V IH = 2 V, V IL = 0.8 V, I OH = 400 µ I IH 20 µ V CC = 5.25 V, V I = 2.7 V I IL 0.4 m V CC = 5.25 V, V I = 0.4 V I I 0.1 m V CC = 5.25 V, V I = 7 V V CC = 4.75 V, V IH = 2 V, V IL = 0.8 V Short-circuit output current I OS m V CC = 5.25 V Supply current** I CC m V CC = 5.25 V Input clamp voltage V IK 1.5 V V CC = 4.75 V, I IN = 18 m Notes: * V CC = 5 V, Ta = 25 C ** I CC is measured with all outputs open, clear and load inputs grounded, and all other inputs at 4.5 V. Switching Characteristics (V CC = 5 V, Ta = 25 C) Item Symbol Inputs s min. typ. max. Unit Condition Maximum clock frequency ƒ max MHz Count-up Carr y ns Count-down Borro w ns C L = 15 pf, Propagation delay time R L = 2 kω ither Count Q ns Load Q ns Clear Q ns Rev.2.00, Feb , page 4 of 11

5 Count Sequences Clear Load ata Inputs B C Count Up Count own Q s Q B Q C Q Carry Borrow Count Up Clear Preset Illustrated below is the following sequence: 1. Clear outputs to zero. 2. Load (preset) to binary thirteen. 3. Count up to fourteen, fifteen, carry, zero, one and two. 4. Count down to one, zero, borrow, fifteen, fourteen, and thirteen. Count own Rev.2.00, Feb , page 5 of 11

6 Testing Method Test Circuit V CC 4.5V RL Load circuit 1 Borrow P.G. Zout = 50Ω Input See Testing Table Up own B C Load Clear CL Carry Same as Load Circuit 1. Q Same as Load Circuit 1. QB Same as Load Circuit 1. QC Same as Load Circuit 1. Q Same as Load Circuit 1. Notes: 1. C L includes probe and jig capacitance. 2. ll diodes are 1S2074(H). Testing Table Inputs Item From input to output CLR Load Up own B C ƒ max Up Count GN 4.5V IN 4.5V GN GN GN GN own Count GN 4.5V 4.5V IN GN GN GN GN Up Count GN 4.5V IN 4.5V GN GN GN GN own Count GN 4.5V 4.5V IN GN GN GN GN Load Q GN IN GN GN IN IN IN IN Clear Q IN IN* GN GN 4.5V 4.5V 4.5V 4.5V Note: *. For initialized Item ƒ max From input to output s Q Q B Q C Q Carry Borrow Up Count OUT OUT OUT OUT OUT own Count OUT OUT OUT OUT OUT Up Count OUT OUT OUT OUT OUT own Count OUT OUT OUT OUT OUT Load Q OUT OUT OUT OUT Clear Q OUT OUT OUT OUT Rev.2.00, Feb , page 6 of 11

7 Waveforms 1 ƒ max,,, (Count Up) t TLH t THL s Count Up Q Q B Q C Q Carry 90% 90% 10% 10% (Measure at tn + 1) t w (H) (Measure before 1 clock of tn + 16) tw (L) (Measure at tn + 2) (Measure at tn + 4) (Measure at tn + 8) (Measure at tn + 16) (Measure at tn + 16) (Measure at tn + 2) (Measure at tn + 4) (Measure at tn + 8) Notes: 1. Input pulse; t TLH, t THL 7 ns, uty Cycle 50%, PRR = 500 khz (ata input). PRR = 1 MHz (except data input) 2. for ƒ max t TLH = t THL 2.5 ns. 3. t n is reference bit time when all outputs are low. 3V 0V Rev.2.00, Feb , page 7 of 11

8 Waveforms 2 ƒ max,,, (Count own) t TLH Count 90% 90% own 10% 10% t THL t w (H) t w (L) (Measure at tn + 1) (Measure at tn + 0) 3V 0V Q (Measure at tn + 2) (Measure at tn + 0) Q B s (Measure at tn + 4) (Measure at tn + 0) Q C (Measure at tn + 8) (Measure at tn + 0) Q Borrow (Measure before 1 clock of tn + 0) Notes: 1. Input pulse; t TLH 7 ns, t THL 7 ns, PRR = 1 MHz, duty cycle 50% 2. for ƒ max t TLH, t THL 2.5 ns. 3. t n is reference bit time when all outputs are high. (Measure at tn + 0) Rev.2.00, Feb , page 8 of 11

9 Waveforms 3,, (Load, Clear Q) t TLH t THL Clear 10% 90% 90% 10% 3V 0V ata Inputs ( to ) t w (CLR) 20ns 10% t TLH t THL 90% 90% 10% t su t h t su 3V 0V Load t THL 90% 90% 10% 10% t TLH 3V 0V Note: Q Input pulse: t TLH 7 ns, t THL 7 ns VOH Rev.2.00, Feb , page 9 of 11

10 1 H74LS193 Package imensions JIT Package Code P-IP16-6.3x RNSS Code PRP0016-B Previous Code P-16FV MSS[Typ.] 1.05g b 3 Z L Reference Symbol e 1 imension in Millimeters Min Nom Max e θ c b e 1 c θ e ( Ni/Pd/u plating ) Z L JIT Package Code P-SOP16-5.5x RNSS Code PRSP0016H-B Previous Code FP-16V MSS[Typ.] 0.24g *1 * F H 1 Z Index mark 8 *3 x M Reference Symbol 2 1 imension in Millimeters Min Nom Max b 1 c c 1 θ 0 8 H y c 1 NOT) 1. IMNSIONS"*1 (Nom)"N"*2" O NOT INCLU MOL FLSH. 2. IMNSION"*3"OS NOT INCLU TRIM OFFST. e Terminal cross section ( Ni/Pd/u plating ) L1 L θ e x etail F y Z L L Rev.2.00, Feb , page 10 of 11

11 H74LS193 JIT Package Code P-SOP x RNSS Code PRSP0016G- Previous Code FP-16NV MSS[Typ.] 0.15g 16 *1 9 F H 1 NOT) 1. IMNSIONS"*1 (Nom)"N"*2" O NOT INCLU MOL FLSH. 2. IMNSION"*3"OS NOT INCLU TRIM OFFST. Index mark *2 c Z 1 e *3 x M 8 Terminal cross section ( Ni/Pd/u plating ) Reference Symbol 2 1 imension in Millimeters Min Nom Max L b 1 c c 1 θ 0 8 y etail F L θ H e x y Z L L Rev.2.00, Feb , page 11 of 11

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