SCHEMATIC X32.4 X32.3 STPS160A DV3 PGND DU1 IRF7749 DV2 X25 X24. Drain_V. Source_V. X29 & X30: VBAT out to "A6862 Demo Board" X4 & X10.
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1 SCHEMATIC X32: Connects to "A6862 Demo Board" X3. Drain_U Connect to Bridge Drive. A X22 X32: Male header. A GU SU X32.2 X32.1 RU1 CU RU2 0R STPS160A DU3 DU1 MU IRF7749 DU2 X21 X23 Source_U Connect to Motor Load. Caution:- This board has been populated to work with the MOSFET's source outputs connected to the Motor Load and the drain outputs connected to the Bridge Drive. If the board is to be connected the opposite way round the diodes DU1, DV1 and DW1 must be fitted. Warning:- If the gate diodes (DU3, DV3 and DW3) on this board are removed the diodes DU2, DV2 and DW2 must be fitted. Table 1: Configuration Options Option 1 Option 2 Option 3 Populate Connection Recirculation DU3, DV3, DW3 DU2, DV2, DW2 DU1, DV1, DW1 Low Power Schottky, Bridge Drive to Drain, Gate to Pgnd Motor Load to Source High Power Diode, Source to Pgnd Bridge Drive to Source, High Power Diode, Motor Load to Drain Drain to Vbrg Fitted as standard (Not Required) (Not Required) (Not Required) FIT (Not Required) (Not Required) (Not Required) FIT DV1 B B X24 Drain_V Connect to Bridge Drive. GV SV X32.4 X32.3 RV1 CV RV2 0R STPS160A DV3 MV IRF7749 DV2 X25 Source_V Connect to Motor Load. X29 & X30: VBAT out to "A6862 Demo Board" X4 & X10. X29 & X30: Male headers. VBAT X29.1 X29.2 X29.3 X29.4 X29.5 X29.6 X30.1 X30.2 X30.3 X30.4 X30.5 X30.6 C C DW1 X26 Drain_W Connect to Bridge Drive. X28 & X31 & X33: out to "A6862 Demo Board" X1 & X2 & X11. X28 & X31 & X33: Male headers. GW SW X32.6 X32.5 RW1 CW RW2 0R STPS160A DW3 MW IRF7749 DW2 X27 X20 Source_W Connect to Motor Load. X28.1 X28.2 X28.3 X28.4 X28.5 X28.6 X31.1 X31.2 X31.3 X31.4 X31.5 X31.6 X33.1 X33.2 X33.3 X33.4 X33.5 X X20-X27: M6 bolt holes. D TITLE: D A6862 3ph Isolation Board : High current paths. Note: "" = "Do No Fit" (component not fitted). Allegro Microsystems Worcester MA USA REV: AUTHOR: 0 D Cameron DATE: PCB: 26th May 2016 SIZE: SHEET: A4 1 of 1 EDC137R A6862-IB
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8 BILL OF MATERIALS Designator Value Rating Tol Part Number Footprint Description Qty RS #1 Farnell #1 CU, CV, CW \ 16V X7R \ SM : 0805 Capacitor : Ceramic Chip (optional) 0 \ \ DU1, DU2, DV1, DV2, DW1, DW2 \ \ \ Sanken TH : Pitch 16mm Diode : Axial, 100V, 3A 0 \ \ DU3, DV3, DW3 \ \ \ STPS160A SM : DO214AC (SMA) Diode : Schottky, 60V, 1A \ HSINK1 \ \ \ \ 75x21.5x19(H)mm Heatsink : SK454-75SA MH1, MH2, MH3, MH4 \ \ \ \ TH : M3 (130mils) hole Mount Hole : Standoff M3 15mm (2 joined = 30mm) \ \ MU, MV, MW \ \ \ IRF7749 SM : L8 (DirectFET) Mosfet : N Channel, 200A, 60V \ PCB \ \ \ EDC137R0 FR4, 2oz Cu, 2 Layer PCB : 3ph Isolation Board \ 1 \ \ 1 \ \ \ \ TH : 7mm Pitch, 20swg Ground Bar : Tinned Copper Wire \ \ RU1, RV1, RW1 \ 0.125W 1% \ SM : 0805 Resistor : Ceramic Chip (optional) 0 \ \ RU2, RV2, RW2 0R 0.125W 1% \ SM : 0805 Resistor : Ceramic Chip \ X20, X21, X22, X23, X24, X25, X26, X27 \ \ \ \ TH : M6 hole Connector : M6 Brass Bolt, Nuts & Washers 0 \ \ X28, X29, X30, X31, X32, X33 \ \ \ \ TH : 2.54mm Pitch, 3x2 Connector : 6-way Header Unshrouded \ [ESDBAG_3x5_RESEAL] \ \ \ \ \ ESD Bag : 76x127mm (3x5") resealable \ [ESDBAG_6x10] \ \ \ \ \ ESD Bag : 152x254mm (6x10") \ [STANDOFF_NUT] \ \ \ \ \ Mount : Standoff Nut, Plastic, M3 \ \ [THERMAL1] \ \ \ \ \ Heatsink Adhesive : Low Bond Strength Note: "" = "Do No Fit" (component not fitted)
9 Revision History Number Date Description September 6, 2016 Initial release Copyright 2016, reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: 9
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1 1 1 8 7 7 8 A9 SCHEMATIC Allegro Microsystems Inc Worcester MA 010 USA DATE: PCB: 17th Jul 01 EDC AUTHOR: Yi Li SHEET: 1 of 1 REV: SIZE: A. TITLE: D A9 Demonstration Board Rev D X.1 X. X. X. X. X. FTDI
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