Chip-Package Co-Design of a 4.7 GHz VCO

Transcription

1 Intl. Journal of Microcircuits and Electronic Packaging Chip-Package Co-Design of a 4.7 GHz VCO Kristof Vaesen, Stéphane Donnay, Philip Pieters, Geert Carchon, Wim Diels, Piet Wambacq, Walter De Raedt, Eric Beyne, and Marc Engels IMEC vzw Kapeldreef 75 B-3001 Heverlee, Belgium Phone: Fax: vaesen@imec.be Abstract Future wireless communication applications require low-power and highly integrated transceiver solutions. The integration of the RF front-end poses a great challenge, in particular, as traditional implementations require a large number of external passive components. Single-package integration of complete transceivers based on an MCM-D technology with integrated passives is presented in this paper as a superior alternative to overcome the many problems of single-chip CMOS integration. Unloaded Qs of on-chip inductors are typically not higher than 5, which limits for example the phase noise performance of a VCO circuit. In this MCM-D technology, inductors with Qs higher than 50 are easily integrated. Active RF components can be assembled to the MCM substrate using Flip Chip technology. The parasitics introduced this way are much lower as compared to traditional chip bonding and packaging. To benefit from all the advantages offered by this approach, a careful co-design of ICs and passive components on the package is necessary. As an illustration, a 4.7 GHz VCO for a 5.2 GHz HIPERLAN-2 application is designed. The VCO consists of a core integrated in 0.35 µm BiCMOS technology and accompanying inductors for the resonator, which are integrated in the thin film MCM-D technology. This single-package solution results in a 5 db phase noise reduction and at the same time the power consumption is lowered by almost a factor of 2 (18 mw to 9.5 mw) as compared to a single-chip design. Key words: MCM-D, VCO, and WLAN. 1. Introduction For upcoming wireless communications systems, one can see a trend towards more flexible, wideband and higher frequency applications. A good example is the upcoming standard for wireless local area networks (WLAN) in the 5-6 GHz band. Designing analog front-ends for these future applications is quite challenging. For portable and battery-powered applications, low power consumption as well as a high level of integration to reduce size and weight are essential. In current digital telecommunication transceivers, the large number of discrete passive components, mainly in the radio front-end, is an important bottleneck for further integration. In this paper, the authors present a new implementation strategy called system-on-a-package, which can increase the level of integration and at the same time reduce the power consumption. First, the prospects and limitations of a single-chip approach are discussed. Next, the thin film MCM-D technology is introduced. This technology makes the integration of the required high quality passive components possible. In the last section, the co-design of an active IC and passive components integrated on the package is illustrated with the design of a 4.7 GHz VCO for a 5.2 GHz HIPERLAN-2 application. 272 International Microelectronics And Packaging Society

2 Chip-Package Co-Design of a 4.7 GHz VCO 2. Problems of System-on-a-Chip Integration In recent years, a lot of research has been devoted towards CMOS integration of RF circuits 2. However, a number of frontend blocks are (and will most likely remain) impossible to integrate in CMOS, such as, high-q and IF bandpass filters or antenna switches. For some other blocks, there is an important performance penalty associated with standard CMOS compared to a GaAs or Si bipolar implementation, e.g. very low-noise amplifiers or power amplifiers. Another very important problem is the supply voltage scaling that comes with CMOS technology scaling. As a result, analog front-end blocks realized in deep submicron CMOS technologies suffer from smaller dynamic ranges. The rationale behind the research in CMOS RF design is the perspective of future single-chip integration of the RF front-end together with the digital baseband processing circuits in standard CMOS technologies. However, several problems could prevent single-chip integration of mixed analog-digital transceivers. The signal-to-noise ratio of the analog blocks can degrade severely due to coupling via the substrate and power lines from the digital to analog blocks. Integrating inductors would allow to eliminate a large part of the discrete passives used in many commercial RF front-end implementations. The quality factor of on-chip inductors is very low compared to discrete inductors. Unloaded Qs of on-chip inductors are typically not higher than 5. Recent developments in silicon processing use copper damascene techniques on high resistive substrates to realize higher quality factors up to 15 at 3 GHz for 1.5 nh coils 11. However, these new techniques are very expensive and not always compatible with the rest of the silicon processing. Moreover, the area of the inductors and of the passive components in general can be very large in integrated circuits. Since the cost per square millimetre of deep-submicron silicon processes is increasing rapidly with technology scaling and the size of, for example, inductors does not scale, the area cost of these integrated passives will become more important in fully integrated RF front-ends. Alternatives for the traditionally used super-heterodyne frontend architecture have been explored recently, to allow higher levels of front-end integration by eliminating high-q discrete IF bandpass filters. However, these architectures have not succeeded in eliminating the need for RF bandpass filters, which remain difficult to integrate. The above arguments indicate that a fully integrated singlechip transceiver in a standard CMOS technology is probably not feasible in the foreseeable future. A single-chip solution in some expensive specialised process could be feasible but will it also make economical sense? 3. System-on-a-Package Integration An alternative implementation of integrated systems is to partition the RF tranceiver in multiple chips. A thin film multichip module technology (MCM-D is used) to interconnect these different chips and, at the same time, to integrate a large number of the passive components with very good quality. With this implementation technology, a number of RF components, each implemented in the most suitable IC technology, can be assembled in a relatively simple and economical way Thin Film MCM-D Technology Thin film MCM-Ds are fabricated by sequential deposition of conductor (typically Cu or Al) and dielectric layers (typically, polyimide or benzocyclobutene (BCB)) on a substrate base made of ceramic, glass, or metal. The IMEC MCM-D technology 4 consists of alternating 5 µm thick layers of photosensitive benzocyclobutene (BCB) dielectric and low loss copper metallizations deposited on a low loss glass carrier substrate. The thin dielectric layers are deposited by a conventional spin coating process, yielding a uniform and well controlled thickness. The thin metal layers are deposited by sputtering and patterned through selective etching. Further additive processing is achieved through electroplating. The widths and spaces of the conductors range from 10 µm up to a few 100 µm. 5. MCM-D Inductors 3 High quality integrated spiral inductors are hard to realize. In standard silicon, the low resistivity of the silicon causes dielectric losses, which limit the quality of the inductor to about 5 at 1 or 2 GHz. When realizing the same spiral inductors in MCM-D, its quality factor increases tremendously at a lower overall cost. Values up to 100 may be achieved at GHz frequencies. A photograph of such an inductor is shown in Figure 1. Figure 1. Photograph of a high Q spiral inductor in MCM- D. International Microelectronics And Packaging Society 273

3 Intl. Journal of Microcircuits and Electronic Packaging Figure 2. Lumped element model of the inductor shown in Figure 1. The spiral is multi-turn circular and in a coplanar fashion. The centre of the spiral is connected to the outside through an overpass on the top metal layer. A typical plot for the reflection, transmission, and unloaded quality factor for both measurement and the fitted model is shown in Figure 3. Figure 4. Network analyzer measurement and model simulation of a MCM-D Ta 2 O 5 capacitor. Figure 3. Network analyzer measurement and lumped element model simulations of a MCM-D 1.6 nh spiral inductor. Figure 5. Cross-section of the MCM-D technology including a Flip Chip solder bump. The behavior of such a spiral inductor may be modeled up the first resonance frequency using a simple lumped element model. This model is depicted in Figure 2. R accounts for the resistive losses, L included the desired inductive effect, and the capacitors model the capacitive coupling between the coil and the surrounding ground plane and the turns of the coil itself Chip-Package Co-Design of a 4.7 GHz VCO 12,13 With an implementation methodology that combines IC with MCM-D technology, one can fully benefit of the possibilities offered by both technologies. MCM-D passives can be optimally 6. MCM-D Capacitors and Resistors tuned to the active on-chip components and can be used as components within the active front-end blocks, such as a varactor and inductor in the LC tank of a VCO. This results in extra Two types of metal-insulator-metal (MIM) capacitors are supported in the described MCM-D technology. For the small ca- components and the MCM module. bonding pads and solder bumps between the Flip Chip mounted pacitors (capacitance/area ratio 6 pf/mm 2 ), the insulating dielectric is BCB. For the larger capacitance values (720 pf/mm 2 ), a layer sign for GHz applications. The Flip Chip model must include Accurate modeling of the assembly is necessary to circuit de- of anodized tantalum is realized on a glass carrier substrate. These the influence of the electromagnetic coupling between the chip Ta 2 O 5 capacitors are contacted with Al based contact metal. Good and the substrate 8. Figure 6 shows the equivalent circuit model agreement between the scalable capacitor model (transmission line for a Flip Chip connection, which is extracted from measurements. Note that these parasitics are much smaller than for RC transmission line) and the measurements is iilustrated in Figure 4. The resistors are realized immediately on the glass carrier wirebonding, where inductance values of nhs are typical. substrate. The used resistive material is TaN and has typical resistance values of ohms per square, Figure 5. the effects of these small parasitics can almost be neglected at the This model is used during the design of the VCO. However, working frequency of 4.7 GHz. Only a slight frequency shift, which is easily compensated by a small change in tuning voltage, is introduced. A more important parasitic effect is intro- International Microelectronics And Packaging Society

4 Chip-Package Co-Design of a 4.7 GHz VCO duced by the on- chip bonding pads of 80 µm x 80 µm, which also have to be modeled accurately. 31 ph MCM Chip 27 ff 41 ff Figure 6. Lumped element model of Flip Chip connection. The VCO is based on the common-collector Colpitts circuit in a balanced configuration to provide differential output for direct compatibility with double-balanced mixer inputs 9. The VCO circuit is shown in Figure 7. Figure 7. Schematic of the VCO circuit. The oscillator output is taken from the collector, which has the advantage of isolating the output load from the LC resonator tank 9. The half circuit can be viewed as a negative resistance oscillator where Z in is given by the following, In this equation, f osc is the oscillation frequency, f m the offset from the oscillation frequency, P s the supply power, and F the factor that takes the noise contribution of the active components into account. The higher the oscillation frequency, the harder it is to obtain a certain phase noise performance. If one assumes a high-q tunable capacitor, the quality factor of the LC tank is approximately equal to the Q of the inductor. The power consumption of a VCO with fixed phase noise specification is therefore inversely proportional to the inductor Q. In the circuit of Figure 7, the LC-tank is formed by the varactors, feedback capacitors and the inductors. The phase noise does not only depend on the Q-factor of the LC-tank, but also on the different noise sources in the circuit. The transistors have a large noise contribution. Therefore, the biasing was selected for optimum output power and minimal noise contribution. The transistor size is primarily determined by the base spreading resistance. To reduce the base resistance, a larger emitter area and a parallel transistor configuration is used. The core of the VCO is designed in the IMEC 0.35 mm BiCMOS process and operates at a 3.3V supply voltage. Three versions of the VCO circuit are designed. This is achieved to make a trade off between on-chip inductors/mcm inductors and between the on-chip varactors and an external MEMS varactor. The first version uses both on-chip inductors and varactors. The varactors are realized using the collector base junction of a bipolar transistor. The Q- factor of the varactor is about 20 and the on-chip inductor has a Q of 5. For the on-chip realization, the Q-factor and thus the phase noise is limited by the quality factor of the inductor. A tuning range plot for the single chip version is depicted in Figure 8. The tuning range is about 8% of the working frequency and is necessary to compensate for component tolerances. The lower edge of the tuning voltage is limited to 1V, in order to prevent the forward biasing of the collector-base junction of the varactor. y c n e u q e r F. c s O C f is the feedback capacitance between the base and the emitter of the BJT, and C 1 is the capacitance of the varactor. The circuit oscillates when the negative real term of Z in compensates for the losses in the LC resonator tank. The phase noise of a VCO is inversely proportional to the square of the quality factor Q of the LC tank and the square of the power 10, as follows, Figure 8. Simulated tuning range for the single chip version of the VCO. In the second version, depicted in Figure 7, the on-chip inductors are replaced by quality MCM inductor with a Q of 28 at 4.7 GHz. The quality factor of the MCM inductor is now higher than that of the varactor, which becomes the limiting factor in the second version. The phase noise performance of this single package version improves about 5 dbc/hz as compared to the single chip version. The phase noise plot is shown in Figure 9. International Microelectronics And Packaging Society 275

5 Intl. Journal of Microcircuits and Electronic Packaging The tuning range for the 1 V to 3 V tuning voltage, shown in Figure 10, is reduced from 400 MHz to about 200 MHz. This is due to an enlarged fixed part of the resonator capacitance as compared to the varactor. The extra capacitance of the bonding pads on both the BiCMOS and the MCM substrate causes this change in fixed capacitance. The layout of the MCM module containing the inductors, bias resistor and power decoupling capacitors is shown in Figure 11. Figure 12 illustrates the micrograph of the mounted BiCMOS chip on a MCM-D substrate. Figure 12. Microphotograph of a mounted BiCMOS chip on a MCM-D substrate. Figure 9. Simulated phase noise plot for the single package version using MCM-D inductors. y c n e u q e r F. c s O The third version uses the off-chip MCM inductors and a MEMS varactor with an estimated Q of 40. A varactor is good example of a RF component that can be fabricated with micromachining and mounted on the MCM substrate. In publications 6, such variable capacitors are described with tuning ranges of 16% over a 5.5V range applied bias, with capacitance values of about 2.2pF and Q factors of 62 at 1 GHz. The simulated phase noise and the power consumption (for equal output power) for these three cases are given in Table 1. The figure of merit (FOM) listed in Table 1 is based on the phase noise, but with correction terms for carrier frequency f 0, frequency offset f, and power consumption P d c10, are as follows, Figure 10. Simulated tuning range for the MCM version of the VCO. A considerable improvement of the figure of merit can be seen for the VCO with high-q MCM inductor and high-q off-chip varactor. Table 1. Simulation results for the VCO with several options for the LC tank. Version Pout (dbm) L(f)@100kHz (dbc/hz) Pdc (mw) FOM (db) Challenges The chip-package co-design approach using integrated passives on a MCM-D substrate can give better results in terms Figure 11. Layout of the MCM-D module containing the of performance, power consumption, and cost of integrated frontends. However, a big challenge for this multi-technology single resonator tank inductors. package approach is the development of a design and test methodology. In this approach, two different design tools where used, 276 International Microelectronics And Packaging Society

6 Chip-Package Co-Design of a 4.7 GHz VCO one for BiCMOS and one for MCM-D design. The BiCMOS designs are made using CADENSE, a commonly used design tool in the Si chip industry. The MCM-D modules are designed in HP- ADS using an MMIC type of design strategy. Each MCM layout component is coupled with an equivalent model for simulation. Layout generation is possible directly from the schematic window of the simulator. The different design tool for both worlds is an obstacle for easy co-design of both active dies and package. A second difficulty is testability. It is impossible to do an on wafer functional test of a VCO with off-chip passive components. This is only possible when the component is mounted on the MCM module, resulting in an overall lower yield. New test strategies need to be worked out in the future. 9. Conclusions A single-package integrated system design is proposed in this work as an alternative for single-chip integration. This method is not incompatible with the expected future improvement of CMOS and is not a temporary solution that will become obsolete with predicted CMOS technology scaling. Instead, these single-package transceivers will only benefit from the evolution in RF CMOS design and the development of new front-end architectures: the resulting single-package solutions will become more dense and cheaper. There will be fewer devices mounted on the MCM substrate, but the cost and performance gain by implementing the large passive components in the MCM substrate instead of on-chip will remain. Moreover, a number of RF components will not be integrated on-chip, such as, RF filters, T/ R switch, antennas etc., and these components can be integrated in the package. Acknowledgments IEEE Journal Solid-State Circuits, Vol. 33, No.7, pp , July J. Burghartz et al., RF Circuit Design Aspects of Spiral Inductors on Silicon, Proceedings ISSCC 1998, pp , P. Pieters, S. Brebels, and E. Beyne, Integrated of Passive Components for Microwave Filters in MCM-D, Proceedings of the 6 th Mulitchip Modules Conference, MCM 97, Denver, Colorado, R. Frye, MCM-D Implementation of Passive RF Components: Chip/Package Tradeoffs, IEEE Symposium on IC/Package Design Integration, Santa Cruz, pp , C. Nguyen et al., Micromachined Devices for Wireless Communications, Proceedings of the IEEE, Vol. 86, No. 8, pp , August P. Pieters and E. Beyne, Spiral inductors Integrated in MCM- D Technology Using the Design Space Concept, Proceedings of the 1998 International Conference On Multichip Modules and High Density Packaging, pp , Yukari Arai, et.al., 60-GHz Flip Chip Assembled MIC Design Considering Chip-Substrate Effect, IEEE Transactions on Microwave Theory and Techniques, Vol. 45, pp , L. Dauphinee, M. Copeland, and P. Schvan, A Balanced 1.5 GHz Voltage Controlled Oscillator with an Integrated LC Resonator, Proceedings ISSCC 1997, pp , P. Kinget, Integrated GHz Voltage Controlled Oscillators, Proceedings AACD Workshop, Nice, March M. de Samber, et al., Low-Complexity MCM-D Technology with Integrated Passives for High Frequency Applications, Proceedings International Conference On Multichip Modules and High Density Packaging, MCM 98, Denver, Colorado, April 15-17, p , A. Cangellaris, Electrical Modeling and Simulation Challenges in Chip-Package Co-design, IEEE Micro, Vol. 18, No. 4, pp , July-August K. Boustedt, GHz Flip Chip An Overview, Proceedings of the 48 th IEEE Electronic Components and Technology Conference, ECTC 98, New York, pp , The authors would like to thank both the MCM and MIRA development groups of IMEC for their contributions and support in this research. About the authors Kristof Vaesen received a Degree in References Industrial Engineering from the KdG, Antwerp, Belgium, in 1996 and an additional M.S. Degree in Electrical Engineering from the Katholieke 1. S. Donnay, P. Wambacq, M. Engels, and I. Bolsens, Single- Universiteit Leuven, Leuven, Belgium, Chip Versus Single-Package Radios, Proceedings of the 1999 in He joined the High Density International Confernce On Multichip Modules and High Interconnect and Systems Packaging Density Packaging, Denver, Colorado, April 7-9, group, IMEC, Leuven, Belgium, later 2. Q. Huang, F. Piazza, P. Orsatti, and T. Ohguro, The Impact in the same year. Since then, his main of Scaling Down to Deep Submicron on CMOS RF Circuits, research activities are focussed towards International Microelectronics And Packaging Society 277

7 Intl. Journal of Microcircuits and Electronic Packaging the single package integration of RF front-ends and the design of RF building blocks in RF MCM-D technology. Stéphane Donnay received the M.S. and Ph.D. Degrees in Electrical Engineering from the Katholieke Universiteit Leuven (K.U.Leuven), Belgium in 1990, and 1998, respectively. He was a Research Assistant in the ESAT-MICAS laboratory of the K.U.Leuven from 1990 until 1996, where he worked in the field of analog and RF modeling and design automation. In 1997, he joined IMEC, where he is now responsible for the Mixed-Signal and RF group. His current research interests are: integration of RF front-ends for digital telecommunication applications, in particular 5 GHz WLAN front-ends, chip-package co-design, modeling and simulation of substrate noise coupling in mixed-signal ICs, and modeling and simulation of RF frontends. Philip Pieters received a Degree in Industrial Engineering in 1991, and an additional M.S. Degree in Electrical Engineering from the Katholieke Univ. Leuven in In the same year, he started working in the High Density Interconnection and Packaging group of IMEC where he initiated the work on integrated passives in a multilayer thin film MCM-D technology. Since April 2000, he has joined the technology development group of CS2, a semiconductor assembly and test foundry located in Zaventem, Belgium, where he is responsible for the high frequency development projects. Geert Carchon received his M.Sc. Degree in Electrical Engineering from the Katholieke Universiteit Leuven, Belgium in As a Research Assistant of the IWT, he is currently working towards a Ph.D. Degree at the K.U.Leuven in close cooperation with the MCP-HDIP division of IMEC. His main interests include the measurement, characterization and modeling of passive devices and the design of RF and microwave circuits (LNAs, modulators, ) in MMIC and multilayer MCM-D. Wim Diels was born in Antwerp, Belgium, in He received an Industrial Engineering Degree in 1996 and a M.S. Degree in Electrical Engineering (burg.ir.) from the Catholic University of Leuven, Belgium, in The subject of his thesis was the design of a wideband medium power amplifier MMIC for the K-band. In the same year, he joined the mixed-signal and RF applications group, IMEC, Leuven, Belgium, where he is involved in the design of RF building blocks for integrated RF frontends. Piet Wambacq was born in Asse, Belgium in He received the Degree of M. Sc. in Electrical and Mechanical Engineering in 1986 from the Katholieke Universiteit Leuven, Belgium. From 1986 to 1996, he worked as a Research Assistant at the ESAT- MICAS Laboratory of the Katholieke Universiteit Leuven, where he obtained a Ph.D. in 1996 on symbolic analysis of large and weakly nonlinear analog integrated circuits. Since 1996, he is working at IMEC on design methodologies for mixed-signal and RF integrated circuits. His research interests are design and CAD of mixed-signal and RF integrated circuits. He has authored or coauthored more than 50 papers in edited books, international journals, and conference proceedings. He is the author of the book Distortion Analysis of Analog Integrated Circuits (Kluwer Academic Publishers 1998). Walter De Raedt received the M.S. in Electrical Engineering at the Katholieke Universiteit Leuven, Leuven, Belgium, in Subsequently, he joined the ESAT laboratory as a Research Assistant and worked on direct write Electron Beam Technology. From 1984, he is with IMEC where he started research on MICs and submicron technologies for advanced HEMT devices. Since 1997, he joined the MCM group where he is working on integrated passives and interconnections for RF front-end systems. 278 International Microelectronics And Packaging Society

8 Chip-Package Co-Design of a 4.7 GHz VCO Eric Beyne received the M.S. Degree in Electrical Engineering, and the Ph.D. Degree in Applied Sciences, from the Katholieke Universiteit Leuven, Leuven, Belgium, in 1983, and 1990, respectively. From 1983 to 1985, he was a Research Assistant at the K. U. Leuven. In 1986, he joined IMEC, where he worked towards his Ph.D. Degree on the interconnection of high-frequency digital circuits. He is presently responsible for projects on multichip modules and advanced packaging at IMEC. Dr. Beyne is a member of the IMAPS-Benelux Committee. International Microelectronics And Packaging Society 279