Experimental Analysis of Design Options for Spiral Inductors Integrated on Low Cost MCM-D Substrates

Transcription

1 Experimental Analysis of Design Options for Spiral Inductors Integrated on Low Cost MCM-D Substrates Didier Cottet, Janusz Grzyb, Michael Scheffler, Gerhard Tröster Electronics Laboratory, ETH Zürich Gloriastrasse 35, CH-9 Zürich, Switzerland Phone: , FAX: cottet@ife.ee.ethz.ch Abstract This paper presents the results of investigations on integrated inductors for a new low cost MCM-D substrate technology. The results are focused on the analysis of design options and design parameter for planar spiral inductors. Measurements on test structures were used to quantify process tolerances and inductor performance and to set up accurate models for em-simulations. Simulation results of many different inductor configurations and layouts were compared in terms of inductance L, quality factor Q and area A. The goal was to give a better understanding of inductor behavior to geometry changes and to offer inductor design guidelines for RF system designers. Special attention was given to inductor cost, driven by area consumption. 1. Introduction For RF applications in the frequency range below GHz, inductors are often implemented as planar spiral inductors. This can be done on-chip (RFICs and MMICs) or off-chip in LTCC and thin film substrates for multichip modules and high density packages. More and more, passive components are also integrated on laminate substrates for high performance printed circuit boards. From the manufacturing point of view the integration of planar spiral inductors is easy as for common inductance values with high Q-factors no additional process steps are required. From a design point of view the determination of the exact inductor geometry and layout leading to the required inductor values demands very complex methods with many iterations. Many different equivalent circuit models and closed form formulas for inductors have been presented in earlier publications [1] [] [3] []. These formulas are often valid only for a specific type of inductor and scalable only within a limited parameter range and with limited accuracy. EM methods offer higher accuracy and more flexibility but they are very computation intensive. As consequence the most common methods used to model the inductors for well defined processes are libraries. Very often the following issues are insufficiently covered by libraries: The effects of other components, assembly and packaging. It is for example crucial to know the impact of glob top materials on inductor performance. Layout modifications to match the exact inductance. It is helpful to know which geometric parameters to modify to obtain the expected changes of inductance and Q-factor. The inductor performance is related to cost aspects, which are area-driven and yield-driven. The goal of this work was therefore to discuss the design options given by the new low cost MCM-D technology. The paper is organized as follows. In section two, the process and the electrical performance of the LAP technology is reviewed. Section three introduces the design options and briefly explains and verifies the used simulation methods. Then, representative examples of the design options are investigated and final conclusions are drawn.. LAP Technology and Performance A new process for low cost MCM-D substrates was developed within the EU Esprit project LAP (Low cost Large Area Panel Processing of MCM-D substrates and packages) [5]. The cost target for this four-layer thin-film technology is US$1/in. To reach this target, the project consortium has increased the production size from today s in and 5 5in panels up to 1 1in and in panels..1. Test Vehicles To characterize the LAP technology a set of test vehicles (TV) has been designed and manufactured. These TVs are dedicated for reliability, assembly, process, electrical and high frequency characterization. The TVs for electrical characterization (EL-TV) consist of plate capacitors, meanders, microstrip lines and via chains. The TVs for high frequency characterization (RF-TV1 and RF- TV) contain lumped passive elements (capacitors and inductors) and distributed passives components (antennas, filters, couplers). The test structures cover the frequency range from lower RF frequencies (1GHz to GHz) for lumped components up to millimeter-wave frequencies (7GHz to 9GHz) for distributed structures. Recent publications have demonstrated that the LAP technology is well suited for the integration of high frequency signal interconnects and passive components [] [7] []. On RF-TV1, a set of twelve planar single-layer spiral inductors has been integrated. Only one geometric parameter is changed at a time from one inductor to the other, where possible, thus allowing to find the relations between inductor geometry and inductor performance. For this work the TVs were produced on the LAP manufacturing equipment at Thomson CSF, substrate manufacturer and LAP project partner. Thomson uses benzocyclobutene (BCB) as photodefinable dielectric for the isolation layers and electroplated copper for the conductor layers. The base carrier is a 1 1in Rogers 3 laminate. Figure 1 shows a photograph of one of the

2 C3 TV1 TV R L Port 1 Port C1 C TV3 TV Figure 3: Equivalent circuit model TV5 TV 1.9 Inductor C9 Inductor C Figure 1: Photography of Thomson s 1 1in panel with 1 1 test vehicles. C9 LAP C9: L [nh] Inductor C9 Inductor C 55 5 C: L [nh] C C9: Qmax C: Qmax Figure : Detail photography of the integrated spiral inductors on RF-TV1 Thomson LAP panel indicating the locations of the RF- TV1s and Figure details the inductors on RF-TV1... Measurements For the inductor measurements we used an Anritsu 379A network analyzer with microwave probes from GGB and LRM calibration. Two-port s-parameter of the twelve test inductors were measured from MHz to GHz on six different TVs on the 1 1in panel. The locations of the measured TVs are indicated with rectangles in Figure 1. To extract the inductor parameter we used a simple π-model (Figure 3) consisting of the inductance L and the equivalent elements R, C 1, C and C 3. Even though more complex model exist, the π-model offers enough accuracy for our purpose (see model verification in subsection 3.1). The circuit elements were extracted from the measured s-parameter with Agilent ADS and the Q-factor was computed in Matlab through s-matrix transformation into the z-matrix with short-cut at port Figure : Measured inductance ( and Q-factor ( of inductors C9 and C on different TVs Figure shows the results for L and Q of the inductors C9 and C (see rectangles in Figure ) with nominal values L C9 = nh and L C = nh respectively for the six TVs. In Figure 5 we see that the variations of the extracted series resistance R correlate with the Q-factor variations. The reason for these variations is visible in Figure. It shows the measured relative variation of the inductor line width w and the sheet resistance R S together with the combination of both. The sheet resistance R S of the four copper layers was measured on the entire panel (except for two corner regions, where no measurement structures were available). The sheet resistance on the top layer M has a mean value of R S = 7.mΩ with a standard deviation of.31mω and maximum tolerances of +% and -11%. The mean sheet resistance for the inner layer M3 is R S =.5mΩ with a standard deviation of.5mω and maximum tolerances of +11% and -1%. The results are plotted in Figure 7 and Figure.

3 3.9 Inductor C9 Inductor C C9: R [Ohm] C: R [Ohm] R sheet [mohm/sq] Figure 5: Extracted series resistance for C9 and C variations [%] line width sheet resistance combination Figure : Variations of lines width and sheet resistance test vehicles (rows) 1 test vehicles (columns) 1 Figure 7 Sheet resistance on top metal layer M R sheet [mohm/sq] 9 7 test vehicles (rows) test vehicles (columns) Figure : Sheet resistance on inner metal layer M3 Table 1: Categories of design options Category Design options and parameter Basic - multi-layer or single-layer - inner or top layer - circular, octagonal, hexagonal, rectangular - routing resources and packaging Coarse - number of coil turns N - inner and outer coil diameter D in - space to coplanar ground plane S GND Fine - line width w - line space s 3. Design Options The presented four-layer LAP process offers many different ways to integrate spiral inductors. The inductors can be implemented as a multi- or single-layer and of circular, octagonal, hexagonal or rectangular shape. Depending on the base material (e.g. laminate or metal) the power/ground planes can be removed or not. Different design rules such as the minimum distance to other components or packaging issues as the influence of glob top materials must be considered. And finally, the questions about cost of such inductors arises: How many routing resources must be sacrificed? What is the total area consumption? What is the inductor s final yield? To answer these questions we started with classifying the design options and parameters into three categories: the basic design options, the coarse design parameters and the fine design parameters. Table 1 lists these three categories with their associated design parameter. The coarse and fine design parameters are also illustrated in Figure Simulations In order to analyze the design space given by the many options of the LAP technology sufficiently, we used the 3D em-simulation tool Sonnet Suite release. based on the Method of Moments (MoM). Cross-sections from test structures and measurement results were used to define the process and inductor models. Figure compares the s-parameter of inductor C obtained from measurements, em-simulations with Sonnet and computed in HSPICE using the equivalent circuit model. Very good coincidence was found up to the inductor s self resonance frequencies. All simulation results presented in the following subsections are based on these verified models. 3.. Basic Design Options Multi-layer inductors can be implemented in two different configurations. In the first one, the serial connection of the layers is used to get higher inductance values within the same area. The second one is used to achieve higher Q-factors and is realized using parallel connection of overlapping coils through consecutive vias what reduces the series resistance. Both techniques are widely used for on-chip inductors on BiCMOS or GaAs ICs, where the conductors are thin aluminum or gold and intrinsic resistivity is much higher than with thick copper conductors. For more details on multi-layer inductors see [9] and [].

4 A D out D in interconnect lines S GND w s Figure 9: Coarse and fine design parameter for planar, rectangular spiral inductors -5 - s11 interconnect lines Figure 11: 3D-view of inductors with interconnect lines in x-direction ( and y-direction ( magnitude [db] s /, 3.5 turns with x-lines with y-lines with glob top phase angle [deg] - -5 C measurement -5 em-simulation HSPICE model C measurement em-simulation HSPICE model s11 s c) Figure : Comparison of s 1 and s 11 from VNA measurement (C), em-simulation and HSPICE simulation As to the inductor windings we have the choice between circular, octagonal, hexagonal and rectangular shapes. The circular shape minimizes the total line length with constant inductor diameter, reduces the current density at the corners and therefore reduces the series resistance. Consequently the Q-factors of hexagonal, octagonal and circular shaped inductors rank in this order. This effect has been reported in earlier publications [] [11]. The drawback when moving from rectangular coils to more complex shapes is that some IC/MMIC manufacturer and CAD tools only support manhattan-like geometries. For simplicity s sake all inductors in this article are rectangular. Q-factor Figure 1: Q-factor of inductors with interconnect lines and with glob top A problem that is more typical to mixed signal MCM substrates is the electromagnetic compatibility of analog and digital signals. The digital part of such systems often features very dense interconnects, where routing resources can be a limiting factor. On a four-layer process one can be tempted to use the remaining layers underneath inductors without being aware of possible mutual perturbation. Using these layers would reduce the substrate area consumed by the inductor by factor four. To analyze the impact of such a layout, a 3½-turn inductor with inductance L = 9.5nH was first simulated in standalone configuration and then with interconnect lines crossing in x-direction (Figure 11 and in y-direction (Figure 11. The inductor areas are about A = 1. 1.mm each. A is defined as the coil area including the space to ground (Figure 9). The simulation results show that the inductance is decreased by the crossing interconnect lines to L x =.nh and L y =.nh respectively. Equally important is the impact on the Q- factor with the presence of highly conductive copper (see Figure 1). In both simulations only eight small copper lines were added on one layer. The problem gets even worse with larger busses with more than one layer used or with power/ground planes instead of interconnects.

5 L=1nH L=nH L=nH L=1nH Figure 13: Inductance L ( and area A ( as function of the inner coil diameter D in The four-layer LAP process gives the option of integrating the inductors on an inner layer (M1, M, M3) or the top layer (M). Two advantages of M are visible in the sheet resistance R s measurement results shown in Figure 7 and Figure. The sheet resistance on M with a mean value of R s = 7.mΩ is about 13% lower than on the inner layers (R s =.5mΩ). Together with the tighter thickness tolerances for this layer the inductors on M have higher Q- factors and yield better accuracy. Another advantage is that no vias are needed to connect RF-ICs to off-chip inductors, thus avoiding further parasitic effects. Depending on the used package the effects of glob top or underfill materials must be considered. The influence of the glob top on inductor performance is analyzed in the next simulation, where we replaced the air of the simulation model with a common glob top material (ε r = 3.17, tan δ =.9 and height h = 5µm). As can be seen in Figure 1 the Q-factor is significantly lower whereas the inductance did not change. This is mainly due to higher dielectric losses (compared to BCB where tan δ =.) and higher dielectric permittivity which increase the parasitic capacitance and therefore lowers the resonance frequency. Figure 1: Q-factor as function of inner coil diameter D in ( and as function of frequency ( 3.3. Coarse Design Parameter In this category the parameters N for the number of coil turns, D in for the inner coil diameter and S GND for the space to the coplanar ground are listed. We can use these parameters to trim the inductor to the target inductance L and Q-factor. As there are three parameters for two targets there exist more than one solution. S GND can be set to a constant, arbitrary chosen value (S GND = µm in our examples) thus allowing to investigate the influence of the two remaining parameter N and D in. 15 similar inductors were simulated with N = 1½, 3½ and 5½ and D in = 1µm, µm, µm, µm and 7µm. Figure 13 and Figure 1 show the resulting design space for L, A and Q. Table shows three solutions, each for two arbitrarily selected inductors L 1 = 1nH and L = nh. Although the differences are quite small, the Q-factor is higher for smaller D in. The frequency plot of the Q-factor is very regular, curves with the same Q max have their maximum value at the same frequency (Figure 1. This does not really extend the design space. More interesting is the difference observed in the area consumption. Especially solution 3 for both inductors with the smaller number of turns N cannot compensate for the larger area A given with the larger inner diameter.

6 L [nh] Area A Inductance L Space to GND [um] A [sqmm] Q-factor um/um 5um/um 5um/um um/um Figure 15: Inductance L and area A as function of S GND Figure 17: Q-factor as function of frequency for different design rules Q-factor um um 3um um 5um Figure 1: Q-factor as function of frequency for different S GND Table : Solutions for L 1 = 1nH and L = nh Solutions L [nh] Q max A [mm ] 1: N = ½, D in = 1µm : N = 3½, D in = 3µm : N = ½, D in = µm : N = 5½, D in = µm..5.5 : N = ½, D in = µm : N = 3½, D in = 7µm..5.9 Directly related to the inductor area A is the parameter S GND - space between the coil itself and the coplanar return path or ground plane. In order to quantify the influence of S GND we have simulated inductors with N = 3½ and D in = µm and with the following values of S GND = 1µm, µm, 3µm and 5µm. The results in Figure 15 show that not only the area A is decreasing with smaller S GND but also the inductance L. Reason for that is the smaller gap narrowing the em-fields, this however minimizes the field dispersion and increases the usable frequency range and Q-factor (Figure 1). The coarse design parameter can be used to find the optimum for the needed inductance and with minimal area. But the influence on the Q-factor however is still very limited. 3.. Fine Design Parameter This category consists of the parameter line width w and line space s. Here we describe how far these parameter can influence L, Q and A. Some relations can seem very obvious. If the lines get wider the series resistance is smaller and the Q-factor should increase. At the same time the parasitic capacitance also increases. Enlarging the lines while keeping w + s constant, increases the risk of line shorts. And if the space is kept constant with larger w, the total line length is increased and thus the series resistance and the inductor area get bigger. In order to achieve high yield inductors, the minimum design rules should not be smaller than the design rules proposed for the used process. More details on the impact of design rules to MCM-D substrate yield and area are reported in [1]. Table 3: Inductor parameter for different design rules Parameter Ind. 1 Ind. Ind. 3 Ind. w [µm] 5 5 s [µm] S GND [µm] N D in [µm] A [mm ] L [nh] Q max Four inductors with different line widths and lines spaces were analyzed. The inductor parameters are listed in Table 3. The results in Table 3 show that the inductance L doesn t change much. This is because the coarse design parameter S GND, N and D in of the four inductors are kept constant. For small differences of w and s it is difficult to predict the behavior of L and Q (inductors 1, and 3). Therefore the line width of inductor was even more enlarged and set to w = µm, where the lower resistance starts to dominate other effects. This result can be observed in Figure 17 showing the Q-factors for the different

7 design rules as a function of frequency. We see that for inductor we could increase the Q-factor. The price for that is the lower usable frequency range and the larger inductor area. It is imperative at this point to compare these results with the process tolerances of our LAP technology. We see that the process accuracy of Q (Figure is within the same order of magnitude as the improvement achievable with small design rule changes. The Q-factor remains sensitive to process tolerances (mainly to variations of the sheet resistance) and should therefore be designed clearly on the safe side.. Conclusions In the first part of this work we demonstrated that the LAP technology is capable of integrating high Q spiral inductors. Measurements on 1 1in LAP panels showed that the accuracy on such large panels is very high, especially for the value of the inductance L. The second part of this work investigated the influence of packaging and layout on the integrated inductors. For this purpose, we used accurate em-simulations with inductor models based on cross-sections and measurement results. Then we have classified the design options and design parameter into three categories: basic design options, coarse design parameter and fine design parameter. For these categories we can summarize the following findings: The basic design options mainly depend on the used process. They define the range of feasible inductance L and Q-factor as well as the area-driven costs. The emphasis was to demonstrate the crucial impact of glob top materials and interconnect lines on inductor performance. The coarse design parameter are independent of the used technology. They are mainly used to set the inductance L and to minimize the inductor area consumption. Coarse design parameter determine areadriven costs. The fine design parameters may be limited by the specified process design rules. The influence on the inductance L is minimal but the Q-factor can significantly be improved by enlarging the line width. These parameter are sensitive to process tolerances and affect both area- and yield-driven costs. Acknowledgement The authors would like to thank all partners in the LAP consortium for their contribution leading to these results and the Swiss Federal Office for Education (BBW), which partially funded this work under project 97.. References 1. J. Zhao, R. C. Frye, W. Wei-Ming Dai, K. L. Tai, S Parameter-Based Experimental Modeling of High Q MCM Inductors with Exponential Gradient Learning Algorithm, in IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part B, Vol., No. 3, pp. -, August C. Patrick Yue, S. Simon Wong, Design Strategy of On-Chip Inductors for Highly Integrated RF Systems, in Proc. IEEE Design Automation Conference, Piscataway, NJ, USA; pp 9-7, Ping Li, A New Closed Form Formula for Inductance Calculation in Microstrip Line Spiral Inductor Design, in Proc. 5 th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP 9), Napa CA, USA, pp. 5-, S. S. Mohan, M. del Mar Hershenson, St. P. Boyd, T. H. Lee, Simple Accurate Expressions for Planar Spiral Inductances, in IEEE Journal of Solid-State Circuits, Vol. 3. No., pp , October Esprit project 1: LAP, Low cost large area panel processing of MCM-D substrates and packages, D. Cottet, M. Scheffler, J. Grzyb, B. Oswald, G. Tröster, RF Characterization of Low Cost MCM- D Substrates, Manufactured on Large Area Panels, in Proc. th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP 99), San Diego, USA, pp , October 5-7, D. Cottet, J. Grzyb, M. Scheffler, B. Oswald, G. Tröster, Integrated RF Components on Low Cost MCM-D Substrates, in Proc. IMAPS Europe, Prague, Czech Republic, pp. 1-17, June 1-,.. J. Grzyb, D. Cottet, G. Tröster, MM-Wave Integrated Antennas on Low Cost MCM-D Substrates, in Proc. 9 th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), Scottsdale AZ, USA, pp. 9-7, October 3-5,. 9. R. D. Lutz, V. K. Tripathi, A. Weisshaar, Design Considerations for Multilevel Spiral Inductors in RFICs, in Proc. 33 rd IMAPS International Symposium on Microelectronics, Boston MA, USA, pp. 1-19, September -,.. R. D. Lutz, Y. Seo, E. Godshalk, V. K. Tripathi, Spiral Inductor Design Issues in a Multilayered Medium, in Proc. International Symposium on Microelectronics ISHM, Reston, VA, USA, pp. 9-33, N. Klemmer, J. Hartung, High Q Inductors for MCM- Si Technology, in Proc. IEEE Multi-Chip Module Conference, MCM 97, Santa Cruz, CA, USA, pp , February M. Scheffler, D. Cottet, G Tröster, On the Impact of Design Rules to High Density Substrate Yield, in Proc. IMAPS Europe, Prague, Czech Republic, pp. 1-, June 1-,.