SD PROGRAMMABLE SYNCHRO/RESOLVER- TO-DIGITAL CONVERTER

Transcription

1 PROGRAMMABLE SYNCHRO/RESOLER- TO-DIGITAL CONERTER FEATURES Make sure the next Card you purchase has... TM Single + Power Supply Accuracy to. Arc-Minutes Pin Programmable Synchro/Resolver Input Option Pin Programmable 4-Bit or -Bit Resolution No 80 False Lock-up Internal Synthesized Reference Built-In-Test (BIT) Output Low Power Consumption Pin-for-Pin Replacement for Natel s 00 and 0 DESCRIPTION The is a low-cost, high reliability, programmable synchro/ resolver-to-digital converter with pin programmable 4- or -bit resolution. Packaged in a -pin DDIP, the features Built-In- Test (BIT) output. The series accepts broadband inputs: 0 to khz, or 47 to khz. Other features include solid-state signal and reference isolation and high common-mode rejection. The digital angle output from the is a natural binary code, parallel positive logic and is TTL/CMOS compatible. Synchronization to a computer is accomplished with the Converter Busy (CB) output and/or the Inhibit () input. APPLICATIONS Because of its high reliability, small size, and low power consumption, the is ideal for military ground or avionics applications. All models are available with MIL-PRF-84 processing. Designed with three-state output, the is especially well suited for use with computer based systems. Among the many possible applications are radar and navigation systems, fire control systems, flight instrumentation and flight trainers or simulators. 0 Wilbur Place Bohemia, New York Fax: FOR MORE INFORMATION CONTACT: Technical Support: -800-DDC-77 ext , 999

2 S4 PROGRAMMABLE SYNCHRO/ RESOLER CONDITIONER S SR R SIN θ COS θ STATE TTL BUFFER HBE BITS -8 HIGH ACCURACY CONTROL TRANSFORMER BIT CT TRANSPARENT LATCH DIGITAL ANGLE φ LOS BIT OUTPUT TRANSPARENT LATCH BIT UP/DOWN COUNTER STATE TTL BUFFER BITS 9- U T LBE GAIN SIN (θ-φ) D DEMODULATOR FIGURE. BLOCK DIAGRAM e T EDGE TRIGGERED LATCH 4B RESOLUTION CONTROL REF IN REFERENCE CONDITIONER R SYNTHESIZED REF LOS ERROR PROCESSOR LSB ANTIJITTER FEEDBACK 0 ns DELAY BIT DETECT EL +8. ANALOG RETURN (+4. ) Q T CO U IBIT TRANSPARENT LATCH OLTAGE DOUBLER E BIT e EL CB +

3 TABLE. SPECIFICATIONS Specifications apply over temperature range, power supply range, reference frequency, and amplitude range; % signal amplitude variation, up to 0% harmonic distortion in the reference, and up to 4 of signal to reference phase shift. PARAMETER RESOLUTION ACCURACY REPEATABILITY REFERENCE CHARACTERISTICS Carrier Frequency Range oltage Range Input Impedance:! Single Ended! Differential Common Mode Range SIGNAL CHARACTERISTICS (voltage options and minimum input impedance ) Input Impedance Imbalance! Synchro mode Zin Line-to-Line Zin Each Line-to-Gnd Common Mode Range! Resolver mode Zin Single Ended Zin Differential Zin Each Line-to Gnd Common Mode Range! Direct (.0 L-L) Input Signal Type Sin/Cos oltage Range Max oltage w/o Damage Input Impedance REFERENCE SYNTHESIZER ± Sig/Ref Phase Shift DIGITAL /OUTPUT Logic Type S: Inhibit () Resolution Control (4B) (for Programmable Units Only) Enable Bits to 8 (HBE) Enable Bits 9 to (LBE) (9 to 4 for 4-bit mode) UNIT Bits Min LSB Hz Hz rms Ohm Ohm % Ohm Ohm Ohm Ohm Ohm rms Ohm Deg ALUE 4 or (See note ).,.,., or. (See note ) max (0 Hz Unit) (400 Hz Unit) 4-0 (for.8 or 90 signal input) -00 (for direct signal input) 0k min 00k min 0 peak max 0. max.8 L-L 90 L-L 0k 00k 0k 0k 0 max 80 max.8 L-L 0k 0k 0k 0 max Sin and Cos resolver signals referenced to converter internal DC reference. nominal,. max. continuous 00 Peak Transient Zin > 0M 0pf voltage follower 0 typ, 4 guaranteed TTL/CMOS compatible Logic 0 = 0.8 max. Logic =.0 min. Loading = 0 µa max. Logic 0 inhibits Data stable within 0. µs (pull up) Logic for 4 bits Logic 0 for Bits (Pull-up current source to + pf max CMOS transient protected) Logic 0 enables Data alid within 0 ns Logic = High Z Data High Z within 00 ns Pull-down current source to GND pf max CMOS transient protected DIGITAL /OUTPUT (CONT.) OUTPUTS: Parallel Data Converter Busy (CB) BIT TABLE. SPECIFICATIONS (CONT.) PARAMETER UNIT ALUE Drive Capability ANALOG OUTPUT Analog Return () elocity (EL) (See note ) AC error (e)! 4-Bit Mode! -Bit Mode Load DYNAMIC CHARACTERISTICS POWER SUPPLY CHARACTERISTICS Nominal oltage oltage Tolerance Max oltage w/o Damage Current TEMPERATURE RANGES Operating (-XXX or -4XXX) (-XXX or -8XXX) Storage PHYSICAL CHARACTERISTICS Type Size Weight TRANSFORMER CHARACTERISTICS (See ordering information for list of Transformers. Reference Transformers are Optional for Both Solid-State and oltage Follower Input Options.) 400 Hz TRANSFORMERS Reference Transformer Carrier Frequency Range oltage Range Input Impedance Breakdown oltage to GND SIGNAL TRANSFORMER Carrier Frequency Range Breakdown oltage to GND Bits µs mrms mrms ma % ma C C C in (mm) oz(g) 4 or parallel lines; natural binary angles, positive logic. 0.8 to.0 positive pulse; leading edge initiates counter update. Logic for fault conditions. 0 pf + rated logic drive Logic 0; TTL load,. ma at 0.4 max Logic ; 0 TTL loads, 0.4 ma at.8 min High Z;0 µa pf max Logic 0; 00 m max driving CMOS Logic ; + supply minus 00 m min driving CMOS +4. nom See TABLE 4.. per LSB of error.7 per LSB of error See TABLE. + ±0 +7 max+digital output load - to + 0 to 70 - to +0 -Pin DDIP.9 x 0.78 x 0. (48 x 0 x.) 0.7 max (0) Hz kω min 00 peak Hz 700 peak

4 TABLE. SPECIFICATIONS (CONT.) PARAMETER TRANSFORMER CHARACTERISTICS (CONT.) Minimum Input impedances (Balanced) 90 L-L L-L.8 L-L 0 Hz TRANSFORMERS Reference Transformer Carrier Frequency Range Input oltage Range Input Impedance Input Common-Mode oltage Output Description Output oltage Power Required Signal Transformer Carrier Frequency Range Input oltage Range Input Impedance Input Common-Mode oltage Output Description Output oltage Power Required ALUE Notes: () Pin Programmable. () EL polarity is negative voltage for positive angular rate. () XX ordering option = ±. minutes resolver mode, ±. minutes synchro mode (-bit mode only). THEORY OF OPERATION SynchroZIN(ZSO) ResolverZIN 80 Ω 00 kω - 0 kω 0 kω 0 kω Hz 80-8 rms; rms nominal resistive 00 kω min, resistive 00 rms transformer isolated +R (in phase with -) and -R (in phase with - ) derived from op-amps. Short-Circuit proof..0 nominal riding on ground reference. Output oltage level tracks input level. 4 ma typ, 7 ma max from + supply Hz 0-00 rms L- L; 90 rms L- L nominal 48 kω min L- L balanced resistive ±00 rms, transformer isolated Resolver output, - Sine (- S) + Cosine (+C) derived from op-amps. Short circuit proof..0 rms nominal riding on ground reference. Output voltage level tracks input level. 4 ma typ, 7 ma max from + supply. The Series are small, -pin DDIP synchro-to-digital hybrid converters. As shown in the block diagram (FIGURE ), the can be broken down into the following functional parts: Signal Input Option, Converter, Analog Conditioner, Power Supply Conditioner, and Digital Interface. CONERTER OPERATION As shown in FIGURE, the converter section of the contains a high accuracy control transformer, demodulator, error processor, voltage-controlled oscillator (CO), up-down counter, and reference conditioner. The converter produces a digital angle which tracks the analog input angle to within the specified accuracy of the converter. The control transformer performs the following trigonometric computation: Where: sin(θ - φ) = sinθ cosφ - cosθ sinφ θ is angle theta representing the resolver shaft position φ is digital angle phi contained in the up/down counter The tracking process consists of continually adjusting φ to make (θ - φ) = 0, so that φ will represent the shaft position θ. The output of the demodulator is an analog DC level proportional to sin(θ - φ). The error processor receives its input from the demodulator and integrates this sin(θ - φ) error signal which then drives the CO. The CO s clock pulses are accumulated by the up/down counter. The velocity voltage accuracy, linearity and offset are determined by the quality of the CO. Functionally, the up/down counter is an incremental integrator. Therefore, there are two stages of integration which makes the converter a Type II tracking servo. In a Type II servo, the CO always settles to a counting rate which makes dφ/dt equal to dθ/dt without lag. The output data will always be fresh and available as long as the maximum tracking rate of the converter is not exceeded. The reference conditioner is a comparator that produces the square wave reference voltage which drives the demodulator. It s single-ended Input Z is 0k Ohms min, 00k Ohms differential. SPECIAL FUNCTIONS The synthesized reference section of the eliminates errors caused by quadrature voltage. Due to the inductive nature of synchros and resolvers, their signals typically lead the reference signal ( and ) by about. When an uncompensated reference signal is used to demodulate the control transformer s output, quadrature voltages are not completely eliminated. In a 4-bit converter it is not necessary to compensate for the reference signal s phase shift. A phase shift will, however, cause problems for the one minute accuracy converters. As shown in FIGURE, the converter synthesizes its own cos(ωt + α) reference signal from the sinθ - cos(ωt + α), cosθ - cos(ωt + α) signal inputs and from the cosωt reference input. The phase angle of the synthesized reference is determined by the signal input. The reference input is used to choose between the +80 and -80 phases. The synthesized reference will always be exactly in phase with the signal input, and quadrature errors will therefore be eliminated. The synthesized reference circuit also eliminates the 80 false error null hangup. Quadrature voltages in a resolver or synchro are by definition the resulting 90 fundamental signal in the nulled out error voltage 4

5 (e) in the converter. A digital position error will result due to the interaction of this quadrature voltage and a reference phase shift between the converter signal and reference inputs. The magnitude of this error is given by the following formula: Magnitude of Error=(Quadrature oltage/f.s.signal) tan(α) Where: Magnitude of Error is in radians, Quadrature oltage is in volts, Full Scale signal is in volts, α = signal-to-ref phase shift. An example of the magnitude of error is as follows: Let: Quadrature oltage =.8 m Let: F.S. signal =.8 Let: α = Then: Magnitude of Error = 0. min LSB in the th bit. Note: Quadrature is composed of static quadrature which is specified by the synchro or resolver supplier plus the speed voltage which is determined by the following formula: Speed oltage=(rotational speed/carrier frequency) F.S. signal Where: Speed oltage is the quadrature due to rotation, Rotational speed is the rps (rotations per second) of the synchro or resolver, Carrier frequency is the REF in Hz. BUILT-IN-TEST (BIT, PIN ) The Built-In-Test output (BIT) monitors the level of error (D) from the demodulator. D represents the difference in the input and output angles and ideally should be zero; if it exceeds approximately 80 LSBs (of the selected resolution) the logic level at BIT will change from a logic 0 to logic. This condition will occur during a large step and reset after the converter settles out. BIT will also change to logic for an over-velocity condition, because the converter loop cannot maintain input-output and/or if the converter malfunctions where it cannot maintain the loop at a null. BIT will also be set for a Loss-of- Signal (LOS) and/or a Loss-of-Reference (LOR). PROGRAMMABLE RESOLUTION (4B, PIN ) Resolution is controlled by one logic input,4b. The resolution can be changed during converter operation so the appropriate resolution and velocity dynamics can be changed as needed. To insure that a race condition does not exist between counting and changing the resolution, input 4B is latched internally on the trailing edge of CB (see FIGURE ). INTERFACING - S SIGNAL OPTIONS The series offers programmable synchro or resolver inputs. In a synchro or resolver, shaft angle data is transmitted as the ratio of carrier amplitudes across the input terminals. Synchro signals, which are of the form sinθcosωt, sin(θ+0 ) + MAX In Phase with - of Converter and R-R of CX. - MAX 0 - = SINθ MAX θ (DEGREES) CCW - = SIN(θ + 40 ) MAX - = SIN(θ + 0 ) MAX Standard Synchro Control Transmitter (CX) Outputs as a Function of CCW Rotation From Electrical Zero (EZ). + MAX -S4 = COS θ MAX CB 0. µs MIN 0 µs MIN In Phase with - of Converter and R-R4 of RX. - MAX θ CW (DEGREES) 4B - = SIN(θ) MAX Standard Resolver Control Transmitter (RX) Outputs as a Function of CW Rotation From Electrical Zero (EZ) With R-R4 Excited. FIGURE. RESOLUTION CONTROL TIMING DIAGRAM FIGURE. SYNCHRO AND RESOLER SIGNALS

6 cosωt, and sin(θ+40 )cosωt are internally converted to resolver format; sinθcosωt and cosθcosωt. FIGURE illustrates synchro and resolver signals as a function of the angle θ. The solid-state signal and reference inputs are true differential inputs with high AC and DC common mode rejection. Input impedance is maintained with power off. SYNCHRO/RESOLER PROGRAMMABLE OPTION The Synchro or Resolver Programmable input options are shown in FIGURES 4 and. SOLID-STATE BUFFER PROTECTION TRANSIENT OLTAGE SUPPRESSION The solid-state signal and reference inputs are true differential inputs with high AC and DC common rejection, so most applications will not require units with isolation transformers. Input impedance is maintained with power off. The recurrent AC peak + DC common-mode voltage should not exceed the values in TABLE. The 90 line-to-line systems may have voltage transients which exceed the 00 specification listed in TABLE. These transients can destroy the thin-film input resistor network in the hybrid. Therefore, 90 L-L solid-state input modules may be protected by installing voltage suppressors as shown. oltage transients are likely to occur whenever synchro or resolver are switched on and off. For instance a 000 transient can be generated when the primary of a CX or TX driving a synchro or resolver input is opened (see FIGURE ). REFERENCE OSCILLATOR LO HI TABLE. COMMON-MODE AND TRANSIENT MAXIMUMS COMMON-MODE MAXIMUM MAX. TRANSIENT PEAK OLTAGE R R S SR R CB (COUNT) EL (ELOCITY) PARALLEL DATA.8 L-L 90 L-L Reference L-L 0 Peak 80 Peak 0 Peak STATOR ROTOR S4 (IBIT) LBE HBE FIGURE 4. SYNCHRO CONNECTION DIAGRAM CR FOR 90 SYNCHRO S CR REFERENCE OSCILLATOR LO HI CR HYBRID.kE00C R4 STATOR R S4 ROTOR S SR R S4 CB (COUNT) EL (ELOCITY) PARALLEL DATA (IBIT) CR, CR, and CR are SA0CA, bipolar transient voltage suppressors or equivalent. 90 L-L RESOLER S4 CR4 FOR 90 RESOLER S CR S4 HYBRID LBE HBE FIGURE. RESOLER CONNECTION DIAGRAM CR4 and CR are SA0CA, bipolar transient voltage suppressors or equivalent. FIGURE. CONNECTIONS FOR OLTAGE TRANSIENT SUPPRESSORS

7 TRANSFORMER ISOLATION Many applications require electrical isolation to the input of the converter. DDC offers transformers suitable for these applications, as indicated in TABLE 8. These transformers are connected as shown in FIGURES and. INTERFACING - DIGITAL OUTPUTS AND CONTROLS DIGITAL INTERFACE The digital interface circuitry performs three main functions:. Latches the output bits during an Inhibit () command allowing stable data to be read out of the.. Furnishes parallel tri-state data formats.. Acts as a buffer between the internal CMOS logic and the external TTL logic. In the applying an Inhibit () command will lock the data in the inhibit transparent latch without interfering with the continuous tracking of the converter s feedback loop. Therefore the digital angle φ is always updated, and the can be applied for an arbitrary amount of time. The Inhibit Transparent Latch and the 0 ns delay are part of the inhibit circuitry. For further information see the IBIT (, PIN ) paragraph. DIGITAL ANGLE OUTPUTS (LOGIC /OUTPUT) The digital angle outputs are buffered and provided in a two-byte format. The first byte contains the MSBs (bits -8) and is enabled by placing HBE (pin ) to a logic 0. Depending on the user-programmed resolution, the second byte contains the LSBs and is enabled by placing LBE (pin 7) to a logic 0. The second byte will contain either bits 9-4 (4-bit resolution) or bits 9- (-bit resolution). All unused LSB s will be at logic 0. TABLE lists the angular weight for the digital angle outputs. The digital angle outputs are valid 0 ns after HBE or LBE are activated with a logic 0 and are high impedance within 00 ns, max after HBE and LBE are set to logic (See FIGURE 7). Both enables are internally pulled down. DIGITAL ANGLE OUTPUT TIMING The digital angle output is 4 or parallel data bits and Converter Busy (CB). All logic outputs are short-circuit proof to ground and +. The CB output is a positive, 0.8 to.0 µs pulse. The digital output data changes approximately 0 ns after the leading edge of the CB pulse because of an internal delay. Data is valid 0. µs after the leading edge of CB (See FIGURE 8). The angle is determined by the sum of the bits at logic. The digital outputs are valid 0 ns max after HBE or LBE go low and are high impedance within 00 ns max of HBE or LBE going high. IBIT (, PIN ) When an Inhibit () input is applied to the, the Output Transparent Latch is locked causing the output data bits to remain stable while data is being transferred (See FIGURE 9). The output data bits are stable 0. µs after goes to logic 0. A logic 0 at the T input of the Inhibit Transparent Latch latches the data, and a logic applied to T allows the bits to change. This latch also prevents the transmission of invalid data when there is an overlap between CB and. While the counter is not being updated, CB is at logic 0 and the latch is transparent; when CB goes to logic, the latch is locked. If CB occurs after has been applied, the latch will remain locked and its data will not change until CB returns to logic 0; if is applied during CB, the latch will not lock until the CB pulse is over. The purpose of the 0 ns delay is to prevent a race condition between CB and where the up-down counter begins to change as an is applied. An input, regardless of its duration, does not affect the converter update. A simple method of interfacing to a computer asynchronous to CB is: () Apply ; () Wait 0. µs min; () Transfer the data; (4) Release. A logic for the enables the output data to be updated. The time it takes for to go to a logic should be 00 ns minimum before valid data is transferred. To allow the update of the output data with valid information the must remain at a logic for µs minimum (See FIGURE 0). DATA TRANSFERS Digital output data from the can be transferred to 8-bit and -bit bus systems. For 8-bit systems, the MSB and LSB bytes are transferred sequentially. For -bit systems all bits are transferred at the same time DATA TRANSFER TO 8-BIT BUS FIGURES and show the connections and timing for transferring data from the to an 8-bit bus. As can be seen by the timing diagram, the following occurs:. The converter control is applied and must remain low for a minimum of 00 ns before valid data is transferred.. HBE is set to a low state (logic 0) 0 ns MIN after goes low and must remain low for a minimum of 0 ns before the MSB data (-8) is valid and transferred. 7

8 . As HBE is set to a high state (logic ), LBE is brought low for a 0 ns MIN before the LSB data is valid and transferred. 4. LBE should go high (to logic ) at least 00 ns MAX before another device uses the bus.. goes high and data transfer is done and the data refresh cycle can begin. Note the time it takes for to go to a logic should be 00 ns minimum before valid data is transferred. TABLE. DIGITAL ANGLE OUTPUTS BIT DEG/BIT MIN/BIT (MSB ALL MODES) (LSB 4 BIT MODE) (LSB BIT MODE) Note: HBE enables the 8 MSBs and LBE enables the LSBs. ASYNCHROUS TO CB HBE OR LBE 0 ns MIN OUTPUT HIGH Z ALID 00 ns MAX HIGH Z DATA 0. µs ;; ;; ALID FIGURE 7. TRI-STATE OUTPUT TIMING FIGURE 9. IBIT TIMING DIAGRAM CB. µs MIN DEPENDS ON dφ/dt µs MIN 0. µs µs 00 ns MIN 0. µs DATA ALID DATA STABLE UPDATE STABLE FIGURE 8. CONERTER BUSY TIMING DIAGRAM 8 FIGURE 0. OUTPUT DATA UPDATE TIMING

9 Note: For further understanding refer to the beginning of this section (i.e., Digital Interface, Digital Angle Outputs, Digital Angle Output Timing, and Inhibit). DATA TRANSFER TO -BIT BUS Data transfer to the -bit bus is much simpler than the 8-bit bus. FIGURES and 4 show the connections and timing for transferring data from the to a -bit bus. As can be seen by the timing diagram the following occurs:. The converter control is applied and must remain low for a minimum of 00 ns before valid data is transferred.. HBE and LBE are set to a low state (logic 0) 0 ns minimum after goes low and must remain low for a minimum of 0 ns before the data (-) is valid and transferred.. HBE and LBE should go high (to logic ) at least 00 ns MAX before another device uses the bus. 4. goes high and data transfer is done and the data refresh cycle can begin. Note the time it takes for to go to a logic should be 00 ns minimum before valid data is transferred. (MSB) BIT HBE BIT LBE BIT BIT 4 BIT BIT BIT 7 BIT 8 BIT 9 BIT 0 BIT BIT BIT BIT 4 BIT (LSB) BIT D7 D D D4 D D D D0 8 BIT BUS Note: For further understanding refer to the beginning of this section (i.e., Digital Interface, Digital Angle Outputs, Digital Angle Output Timing, and Inhibit). FIGURE. 8-BIT DATA TRANSFER INTERFACING - ANALOG OUTPUTS The analog outputs are AC error (e), Analog Return (), and elocity (EL). AC ERROR (e, PIN ) The AC error is proportional to the difference between the input angle θ and the digital input angle φ, (θ-φ), with a scaling of: 00 ns MIN. m rms/lsb (4-bit mode).7 m rms/lsb (-bit mode) The e output can swing ± min with respect to Analog Return (). HBE DATA -8 ALID 0 ns MIN 00 ns MAX ANALOG RETURN (, PIN ) This internal voltage is not required externally for normal operation of the converter. It is used as the internal DC reference and the return for the EL and e outputs. It is nominally +4. and is proportional to the + DC supply. ELOCITY (EL, PIN 0) The velocity output (EL, pin 0) is a DC voltage proportional to angular velocity dθ/dt. The velocity is the input to the voltagecontrolled oscillator (CO), as shown in FIGURE. Its linearity LBE DATA 9- ALID 0 ns MIN 00 ns MAX 9 FIGURE. 8-BIT DATA TRANSFER TIMING

10 and accuracy are dependent solely on the linearity and accuracy of the CO. The EL output can swing ±.0 with respect to Analog Return (). The analog output EL characteristics are listed in TABLES 4 and. The EL output has DC tachometer quality specs such that it can be used as the velocity feedback in servo applications. INTERFACING - DYNAMIC PERFORMANCE A Type II servo loop (K = ) and very high acceleration constants give the superior dynamic performance. If the power supply voltage is not the + DC nominal value, the specified input rates will increase or decrease in proportion to the fractional change in voltage. TRANSFER FUNCTIONS The dynamic performance of the converter can be determined from its transfer function block diagram (FIGURE ) and open and closed loop Bode plots (FIGURES and 7). alues for the transfer function block can be obtained from TABLE. RESPONSE PARAMETERS As long as the converter s maximum tracking rate is not exceeded, there will be no velocity lag in the converter output although momentary acceleration errors remain. If a step input occurs, as when the power is initially applied, the response will be critically damped. FIGURE 8 shows the response to a step input. After initial slewing at the maximum tracking rate of the converter, there is one overshoot (which is inherent in a Type II servo). The overshoot settling to a final value is a function of the small signal settling time. FASTER SETTLING TIME USING BIT TO REDUCE RESOLUTION Since the has higher precision in the -bit mode and faster settling in the 4-bit mode, the BIT output can be used to Polarity TABLE 4. ELOCITY CHARACTERISTICS PARAMETER UNITS TYP MAX Device Type Output oltage (see note) EL is negative for positive angular rate. 0 Hz. 400 Hz. 0 Hz. 400 Hz oltage Scaling rps/. See el. oltage Scaling TABLE. Scale Factor Error Reversal Error Linearity Error Zero Offset Load % % % output m ma Note: With respect to Analog Return () TABLE. ELOCITY OLTAGE SCALING (values in /rps) DEICE TYPE 4 BIT BIT HBE LBE 0 Hz 400 Hz (MSB) BIT BIT BIT BIT 4 BIT BIT BIT 7 BIT 8 BIT 9 BIT 0 BIT BIT BIT BIT 4 BIT (LSB) BIT D D4 D D D D0 D9 D8 D7 D D D4 D D D D0 BIT BUS Note: If the resolution is changed while the input is changing, then the velocity output voltage and the digital output will have a transient until it settles to the new velocity scaling at a speed determined by the bandwidth. HBE, LBE DATA - ALID 0 ns MIN 00 ns MIN 00 ns MAX FIGURE. -BIT DATA TRANSFER 0 FIGURE 4. -BIT DATA TRANSFER TIMING

11 program the for lower resolution, allowing the converter to settle faster for step inputs. High precision, faster settling can therefore be obtained simultaneously and automatically in one unit. CONNECTING THE TO A P.C. BOARD The can be attached to a printed circuit board using hand solder or wave soldering techniques. Limit exposure to 00 C (7 F) max, for 0 seconds maximum. Since the Series converters contain a CMOS device, standard CMOS handling procedures should be followed. TABLE. DYNAMIC CHARACTERISTICS PARAMETER Input Freq. Tracking Rate Bandwidth, cl Ka A A A B acc- LSB lag Settling Time 80 degree Step.4 degree Step UNIT Hertz rps Hertz /sec /sec /sec /sec /sec /sec ms ms 0 Hz UNIT 400 Hz UNIT 4-BIT -BIT 4-BIT -BIT 47-k 40 7, k k k k 0 0 9,000. 0, k. 0 48, , θ ERROR PROCESSOR CO CT A S + e + A B S S S + - 0B ELOCITY OUT DIGITAL POSITION OUT (φ) CLOSED LOOP BW (Hz) = A π H = A A ω (rad/sec) Open Loop Transfer function = Output S A + B S S + 0B WHERE: A = A A FIGURE. TRANSFER FUNCTION BLOCK DIAGRAM FIGURE 7. CLOSED LOOP BODE PLOT - db/oct OERSHOOT 4 B A (BW) A - db/oct ω (rad/sec) 0B MAX SLOPE EQUALS TRACKING RATE (SLEW RATE) θ θ SMALL SIGNAL SETTLING TIME SETTLING TIME FIGURE. OPEN LOOP BODE PLOT FIGURE 8. RESPONSE TO STEP

12 TABLE 7. PINOUTS PIN FUNCTION PIN FUNCTION (Res) (Syn) (Res) (Syn) Cos(x) (Res) (Syn) Sin(x) S4(Res) S(Res) S(Syn) N/C(x) SR(Res) SR(Syn) N/C(x) R(Res) R(Syn) N/C(x) EL Analog Return () e CB BIT 4B LBE GND HBE B (MSB) B B B4 B B B7 B8 B9 B0 B B B B4 B B (LSB) Note: (Res) means resolver, (Syn) means synchro, and (x) means direct. For a direct input unit pins,, and 7 (S, SR, R) are no connect. CONTRASTING COLORED BEAD IDENTIFIES PIN.700 ±0.00 (4. ±0.) PIN NUMBERS ARE FOR REF. ONLY.800 MAX (0.) PIN DENOTED BY CONTRASTING COLORED BEAD OR INDEX MARK MAX (0. MAX) BOTTOM IEW 0.00 ±0.00 (. ±0.).00 TYP (.4) 8.08±.00 (0.4 ± 0.0).900 MAX (48. MAX).900 MAX (48.) BOTTOM IEW 7 EQ. =.700 (TOL. NONCUM) 0. MAX (.) SEATING PLANE SIDE IEW 0.0 MAX (0.9) 0. MIN (. MIN) 0.00 TYP(.4) TOL. NON- CUMULATIE 0.08 (0.4) DIAM TYP.00 ±.00 TYP (0. ±0.0) MIN TYP (0.) NOTES:. Dimensions shown are in inches (mm).. Lead identification numbers are for reference only.. Lead cluster shall be centered within ±0.0(0.) of outline dimensions. Lead spacing dimensions apply only at seating plane. 4. Package is kovar with electroless nickel plating.. Case is electrically floating.. Leads are gold coated kovar..0 MAX (.) SIDE IEW NOTES:. Dimensions shown are in inches (mm).. Lead Cluster to be centralized about case centerline within ± ±.00 TYP (.4 ±0.) FIGURE 9. MECHANICAL OUTLINE -PIN DDIP (KOAR) FIGURE 0. MECHANICAL OUTLINE -PIN FLAT PACK (CERAMIC)

13 400 Hz SYNCHRO TRANSFORMER T 044 OR 04 SYNCHRO TA TB 0 0 S C D4 400 Hz RESOLER TRANSFORMER T 04 OR 047 OR 048 RESOLER S4 TA TB 0 0 S C D4 0 Hz SYNCHRO TRANSFORMER 4 * SYNCHRO S +C -s GND S C D 400 Hz REF TRANSFORMER 049 SYNCHRO T D4 0 Hz REF TRANSFORMER 4 + GND REF + -s 4 +R -R D 9 8 * NOTE AND CONNECTIONS FIGURE. TRANSFORMER CONNECTION DIAGRAMS

14 These external transformers are for use with converter modules with voltage follower buffer inputs. 400 Hz SYNCHRO AND RESOLER TRANSFORMER DIAGRAMS (TIA AND TIB) EACH TRANSFORMER CONSISTS OF TWO SECTIONS, TIA AND TIB. MECHANICAL OUTLINES 0.0 MAX (7.) 0.09 MAX (.9) 0. MAX (.49) 0. MAX (.8) 0. MAX (.8) 0. MAX (.49) 0.09 MAX (.9) 4 TA TB MAX (0.7) 0.00 (.4) SIDE IEW TERMINALS 0.0 ±0.00 (. ±0.0) DIAM 0. (.8) MIN LENGTH SOLDER PLATED BRASS. SCHEMATIC DIAGRAMS 0.00 (.4) TYP TOL NON CUM BOTTOM IEW BOTTOM IEW 0. MAX (.9) PIN NUMBERS FOR REF. ONLY. DOT ON TOP FACE IDENTIFIES PINS AND. TA AND TBG PAIRING NUMBERS LISTED IN SHORT SIDE. MARKING INCLUDES PART NUMBER AND TA AND TB. A. SYNCHRO B. RESOLER TA (-SIN) TA (-SIN) SYNCHRO TB 0 +SIN (-COS) RESOLER OUTPUT TO CONERTER RESOLER S4 TB 0 +SIN (-COS) RESOLER OUTPUT TO CONERTER 0 +COS 0 +COS 400 Hz REFERENCE TRANSFORMER DIAGRAMS (T). MECHANICAL OUTLINE 0.0 MAX (7.) 0.09 MAX (.9) 0. MAX (.49) 0. MAX (.8) 0 Hz SYNCHRO AND REFERENCE TRANSFORMER DIAGRAMS The mechanical outline is the same for the synchro input transformer (4) and the reference input transformer (4), except for the pins. Pins for the reference transformer are shown in parenthesis ( ) below. An asterisk * indicates that the pin is omitted. CASE IS BLACK AND NON-CONDUCTIE 0.8 MAX (0.7) 0.00 (.4) PIN NUMBERS FOR REF. ONLY. DOT ON TOP FACE IDENTIFIES PIN. MARKING INCLUDES PART NUMBER. *.4 MAX (8.9) + * (+ ) -S (-R) + * 0. (.) MIN. TERMINALS 0. ±0.00 (. ±0.0) DIAM 0. (.8) MIN LENGTH SOLDER PLATED BRASS 0.0 ±0.00 (.7 ±0.) 0.00 (.4) TYP TOL NON CUM.4 MAX (8.9) 4 or (4) 0.8 ±0.00 (.9 ±0.). SCHEMATIC DIAGRAM REFERENCE 0 OUTPUT TO CONERTER 4 () () () (+R) (-s) * +C -s + (BOTTOM IEW) 0.7 ±0.00 (4.4 ±0.) NONCUMULATIE TOLERANCE FIGURE. TRANSFORMER MECHANICAL OUTLINES 0. ±0.0 (.0 ±0.7) 0. ±0. (. ±0.7) ±0.00 DIA. PIN. SOLDER PLATED BRASS 0.4 (0.7) MAX.

15 ORDERING INFORMATION (see TABLE 8 for reference and signal transformer ordering information) XX-XXXX Supplemental Process Requirements: S = Pre-Cap Source Inspection L = Pull Test Q = Pull Test and Pre-Cap Inspection K = One Lot Date Code W = One Lot Date Code and PreCap Source Y = One Lot Date Code and 00% Pull Test Z = One Lot Date Code, PreCap Source and 00% Pull Test Blank = None of the Above Accuracy: = ±. Minutes 4 = ±. Minutes = ±. Minutes Resolver Mode, ±. Minutes Synchro Mode (-Bit Mode only) Process Requirements: 0 = Standard DDC Processing, no Burn-In (See table below.) = MIL-PRF-84 Compliant = B* = MIL-PRF-84 Compliant with PIND Testing 4 = MIL-PRF-84 Compliant with Solder Dip = MIL-PRF-84 Compliant with PIND Testing and Solder Dip = B* with PIND Testing 7 = B* with Solder Dip 8 = B* with PIND Testing and Solder Dip 9 = Standard DDC Processing with Solder Dip, no Burn-In (See table below.) Temperature Grade/Data Requirements: = - C to + C = -40 C to +8 C = 0 C to +70 C 4 = - C to + C with ariables Test Data = -40 C to +8 C with ariables Test Data 8 = 0 C to +70 C with ariables Test Data Input: =.8/400 Hz = 90/400 Hz = 90/0 Hz 4 = Direct/400 Hz = Direct/0 Hz Package: D = DIP F = Flat Pack (Consult factory for availability.) *Standard DDC Processing with burn-in and full temperature test see table below. STANDARD DDC PROCESSING TEST INSPECTION SEAL TEMPERATURE CYCLE CONSTANT ACCELERATION BURN-IN MIL-STD-88 METHOD(S) 009, 00, 07, and , Table CONDITION(S) A and C C A

16 TABLE 8. TRANSFORMER ORDERING INFORMATION TYPE FREQ. REF. OLTAGE L-L OLTAGE PART NUMBERS REF. XFMR SIGNAL XFMR Synchro Synchro 400 Hz 400 Hz * 04* Resolver Resolver Resolver 400 Hz 400 Hz 400 Hz * 047* 04* Synchro 0 Hz * The part number for each 400 Hz synchro or resolver isolation transformer includes two separate modules as shown in the outline drawings. 0 Hz synchro transformers are available in two temperature ranges: XXXXX- = - C to +0 C XXXXX- = 0 C to +70 C The information in this data sheet is believed to be accurate; however, no responsibility is assumed by for its use, and no license or rights are granted by implication or otherwise in connection therewith. Specifications are subject to change without notice. 0 Wilbur Place, Bohemia, New York 7-48 For Technical Support DDC-77 ext. 78 Headquarters - Tel: () 7-00 ext. 78, Fax: () 7-78 West Coast - Tel: (74) , Fax: (74) Southeast - Tel: (70) , Fax: (70) 40-0 United Kingdom - Tel: +44-(0)-840, Fax: +44-(0)-4 Ireland - Tel: +--40, Fax: France - Tel: +-(0)-4--44, Fax: +-(0)-4--4 Germany - Tel: +49-(0) , Fax: +49-(0) Japan - Tel: +8-(0) , Fax: +8-(0) World Wide Web - U RE GIS T E R E D FIR M DATA DEICE CORPORATION REGISTERED TO ISO 900 FILE NO. A97 F-0/0-0 PRINTED IN THE U.S.A.