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1 SỐ 14 THÁNG

2 CÔNG TRÌNH KHOA HỌC Nguyễn Văn Hải, Hoàng Tiến Dũng Điều khiển bám vị trí trục máy CNC trên cơ sở điều khiển trong chế độ trượt và bộ quan sát nhiễu Huỳnh Phước Sang, Nguyễn Chí Ngôn Ứng dụng FPGA thực hiện các kỹ thuật điều chế độ rộng xung dựa vào sóng mang cho bộ nghịch lưu ba pha Đặng Ngọc Trung, Đỗ Trung Hải Một phương pháp điều khiển robot dưới tác động của nhiễu từ bên ngoài Cao Nhật Tân, Nguyễn Minh Khai, Đỗ Đức Trí, Hoàng Ngọc Văn Bộ chuyển đổi DC-DC giảm tỷ số máy biến áp cách ly Lê Minh Hoàng Xây dựng mô hình nhiệt sử dụng mô hình mạch điện tương đương: Ứng dụng cụ thể cho một tòa nhà mẫu Nguyễn Quang Địch Ước lượng vị trí trục động cơ bằng phương pháp chèn tín hiệu phụ tần số cao trong hệ điều chỉnh vector động cơ đồng bộ kích thích vĩnh cửu Trần Vũ Trung, Nguyễn Phùng Quang Điều khiển động cơ đồng bộ kích thích vĩnh cửu nuôi bởi biến tần ma trận sử dụng phương pháp điều khiển dự báo tường minh Nguyễn Đình Luyện, Nguyễn Việt Tùng, Nguyễn Thị Lan Hương Khảo sát phụ tải điện của trạm BTS nhằm tối ưu hóa sử dụng điện năng Tháng 12/2015 BAN BIÊN TẬP CHUYÊN SAN Cố vấn khoa học Nguyễn Xuân Quỳnh Trưởng ban Nguyễn Phùng Quang Ủy viên Cao Tiến Huỳnh Thân Ngọc Hoàn Phạm Thị Ngọc Yến Phan Xuân Minh Hồ Đắc Lộc Phạm Thượng Cát Nguyễn Như Hiển Đoàn Quang Vinh Vũ Đình Thành Lê Hoài Quốc BAN THƯ KÝ CHUYÊN SAN Trưởng ban Nguyễn Văn Nhờ Ủy viên Nguyễn Quang Địch Nguyễn Hoàng Mai Nguyễn Chí Ngôn TỔNG BIÊN TẬP Trịnh Đình Đề PHÓ TỔNG BIÊN TẬP Đinh Văn Hiến Tạ Cao Minh Hoàng Quang Vinh THƯ KÝ TÒA SOẠN Trần Thị Giang TRỊ SỰ Vũ Thị Huệ LIÊN HỆ PHÁT HÀNH Văn phòng tạp chí Số 105 Hoàng Văn Thái, Thanh Xuân Hà Nội Tel.: / Fax: Hotline: tapchitudonghoa@gmail.com Website: automation.net.vn Văn phòng Hội TĐH TP. Hồ Chí Minh Số 203 Nguyễn Thái Bình, quận 1 TP. Hồ Chí Minh Hotline: (Nguyễn Văn Học) Giấy phép xuất bản số: 337/GP-BTTTT ngày 16/09/2013 của Bộ Thông tin và Truyền thông In tại Công ty TNHH MTV In quân đội 1 Giá: ,- VNĐ

3 SCIENTIFIC PAPERS Nguyen Van Hai, Hoang Tien Dung Position tracking control for axes of CNC machines based on sliding mode control and disturbance observer Huynh Phuoc Sang, Nguyen Chi Ngon FPGA implementation of carrier-based PWM strategies for threephase PWM inverters Dang Ngoc Trung, Do Trung Hai A robot control method under influence of external disturbances Cao Nhat Tan, Nguyen Minh Khai, Do Duc Tri, Hoang Ngoc Van Reducing turn-ratio of isolated transformer in DC-DC converters Le Minh Hoang Building thermal model using equivalent electric circuits: Application to the public building platform Nguyen Quang Dich Rotor position estimation using high frequency signal injection method for vector control of permanent-magnet synchronous motor Tran Vu Trung, Nguyen Phung Quang Explicit model predictive control of permanent-magnet synchronous motors fed by matrix converter Nguyen Dinh Luyen, Nguyen Viet Tung, Nguyen Thi Lan Huong Investigation of Base Transceiver Station power load for energy consumption optimization December 2015 EDITORIAL BOARD Scientific advisory Nguyen Xuan Quynh Head of board Nguyen Phung Quang Member of board Cao Tien Huynh Thân Ngoc Hoan Pham Thi Ngoc Yen Phan Xuan Minh Ho Dac Loc Pham Thuong Cat Nguyen Nhu Hien Doan Quang Vinh Vu Dinh Thanh Le Hoai Quoc SECRETARIAT Head of sekretariat Nguyen Van Nho Member of sekretariat Nguyen Quang Dich Nguyen Hoang Mai Nguyen Chi Ngon EDITOR IN CHIEF Trinh Dinh De DEPUTY EDITOR Dinh Van Hien Ta Cao Minh Hoang Quang Vinh EDITORIAL SECRETARY Tran Thi Giang ADMINISTRATION Vu Thi Hue DISTRIBUTION Journal office No. 105 Hoang Van Thai, Thanh Xuan Hanoi Tel.: / Fax: Hotline: tapchitudonghoa@gmail.com Website: automation.net.vn Office HCM City Automation Association No. 203 Nguyen Thai Binh, District 1 Ho Chi Minh City Hotline: (Nguyen Van Hoc) Publication license No. 337/GP-BTTTT 16 th September 2013 Printed by MTV In quan doi 1 Ltd. Co. Price: ,- VND

4 FPGA Implementation of carrier-based PWM strategies for three-phase PWM inverters Ứng dụng FPGA thực hiện các kỹ thuật điều chế độ rộng xung dựa vào sóng mang cho bộ nghịch lưu ba pha Huỳnh Phước Sang, Nguyễn Chí Ngôn Can Tho University Tóm tắt Mục đích của bài báo này là trình bày ưu điểm của việc thiết kế và thực hiện bộ điều chế độ rộng xung (PWM) có cấu hình linh hoạt cho bộ nghịch lưu ba pha bằng cách sử dụng FPGA. Bộ điều chế độ rộng xung được thiết kế sao cho có khả năng chuyển đổi giữa hai phương pháp điều chế bao gồm SVPWM và DPWMMIN. Mô hình thiết kế được đề xuất chỉ sử dụng một phần nhỏ tài nguyên của FPGA có kích cỡ trung bình nên có thể được tích hợp như một phần của bộ điều khiển phức tạp hơn trong các ứng dụng của bộ nghịch lưu ba pha. Ý tưởng thiết kế cung cấp giải pháp điều khiển đơn chip cho các ứng của bộ nghịch lưu ba pha. Mô hình thiết kế được phát triển trên bộ điều khiển ARM-FPGA SmartFusion, các kết quả thực nghiệm được đưa ra để minh chứng cho ưu điểm và hiệu suất của bộ điều chế. Keywords Carrier-based pulse width modulation, field programmable gate array, voltage source inverter Abstract 1 The paper aims to present the interest of designing and implementing a dynamically reconfigurable digital carrier-based pulse width modulation (PWM) generator for three-phase two-level voltage source inverters (VSIs) using field-programmable gate array (FPGA). The PWM generator is designed such that it is capable of switching between two different PWM schemes including SVPWM and DPWMMIN. The proposed design consumes a small fraction of the hardware resource of a medium-sized FPGA, and can be then incorporated as a part of larger control unit adapting to a wide range of three-phase inverter applications. The design concept provides a singlechip control solution for various industrial applications of three-phase inverters. The proposed PWM generator is developed on a SmartFusion ARM-based mixed-signal FPGA controller, and experimental verifications have been given to illustrate the advantages and performance of the proposed PWM generator. Symbol Symbol Unit Meaning e f 1 Hz Zero sequence signal Fundamental frequency f c khz Carrier wave frequency f clk MHz Clock frequency m Modulation index t d s Dead time 1 Ngày nhận bài: 14/07/2015; Ngày nhận bản sửa: 13/10/2015; Ngày chấp nhận: 24/12/2015; Phản biện: Hoàng Trang, Tạ Cao Minh, Thân Ngọc Hoàn v 1a, v 1b, v 1c Reference sinusoidal signals v a, v b, v c Modulation signals v ao, v bo, v co V Phase-to-DC link middle point output voltages v ab, v bc, v ca V Line-to-line voltages v an, v bn, v cn V Output phase voltages v no V Load neutral point-to-dc link middle point output voltage V dc DC link voltage V car Peak of the triangular carrier signal V m Amplitude of reference sinusoidal signals Abbreviations FPGA PWM SVPWM DPWMMIN VLSI VSI UPS ZSS Field programmable gate array Pulse width modulation Space vector PWM Discontinuous PWM using only lower zero vector (V 0 = 000) Very large scale integration Voltage source inverter Uninterrupted power supply Zero-sequence signal 1. Introduction Due to the significant improvement of fast-switching semiconductor power devices, the VSIs with PWM control are increasingly utilized in many applications such as motor drive, UPS, and renewable energy distribution, etc. Many real-time PWM strategies have been developed to obtain the following aims: wide linear modulation range, low harmonic content, low switching losses, easy realization and less 8

5 computation time. For a long time, the carrier-based PWM control strategies have been widely used for the VSI applications because of its simple analog and digital implementation. In this case, gating signals defining the ON/OFF instants of the power switches (MOSFETs, IBGT, etc.) are the result of the comparison between a common high-frequency triangular carrier signal and three-phase modulation signals. The earliest modulation signals for the carrier-based PWM are purely sinusoidal. However, it exhibits poor performance with regard to maximum attainable voltage and power. The use of an injected ZSS in [1] initiated the development of the nonsinusoidal PWM strategies for the three-phase inverters, in which the linear modulation range can be extended by 15.5% compared to SPWM [2]. These strategies also introduce less current harmonic distortion and less switching losses than SPWM [3]- [6]. Due to simple implementation, SVPWM and DPWMMIN methods widely used in many applications. ZSSs are simply generated by only detecting the instant maximum and minimum values of three-phase sinusoidal reference voltages. Fig. 1 shows the block diagram of three-phase inverter using the carrier-based PWM scheme. Fig. 1 Block diagram of three-phase PWM inverter In recent years, fast progress in VLSI technology has given an opportunity for the development of modern electronic field. Using FPGAs for the design and implementation of the various power conversion systems, especially in the PWM inverter controller [7]-[10], has widely emerged since they are considered as a powerful and cost-effective solution [11], [12]. Compared to microcontroller and DSPintegrated circuits, FPGAs have the advantage of hardware re-configurability offering dynamic and rapid modification in the design and improvement process to shorten the time to market of electronic products. Moreover, the parallel processing capability allows FPGAs to entail significantly faster algorithm execution time, dealing with one of the drawbacks of microcontroller or DSP-based digital systems. Consequently, the FPGA-based implementation of the PWM strategies provides benefits such as fast prototyping, simple hardware and software design, higher switching frequency, and in turn a higher control bandwidth achieved. This paper presents the simple FPGA-based design and implementation of a carrier-based PWM generator for three-phase power inverters. By exploiting the hardware re-configurability of FPGAs, the PWM generator designed can dynamically switch between two popular PWM schemes, SVPWM and DPWMMIN. Owing to simplicity and occupying a small fraction of the hardware resource, the proposed PWM generator can be integrated as a part in more complicated inverter control algorithms (power distribution control, output voltage regulation, motor speed control, etc.). Certainly, such the integrated systems result in the reduction of design complexity, power consumption, and total system cost [13], [14]. The PWM generator has been realized using the SmartFusion ARM-based mixed-signal FPGA controller. Compared to past-developed PWM control, the design in this paper exhibits much simpler architecture and better resource utilization because it does not need co-ordinate transformation, sector detection, and duty calculation. Moreover, it is applicable to support not only the mentioned PWM schemes but also to all major PWM schemes. Experimental results are provided to demonstrate the improvement and performance of the PWM generator. 2. Main content 2.1 Principle of carrier-based PWM The major purpose of the three-phase two-level PWM inverter is to generate three-phase sinusoidal voltages with variable amplitude and frequency by controlling ON/OFF state of power switches. For the carrierbased PWM, the inverter switches are set to ON or OFF as the result of the comparison between a common high-frequency triangular carrier with threephase modulation signals as shown in Fig. 1. The three-phase modulation signals are as follows: va v1a e vb v1b e (1) v v e c 1c where the reference sinusoidal signals v 1a, v 1b, v 1c are v1a Vm sin t v1b Vm sin t 2 3 (2) v1c Vm sin t 2 3 In the linear modulation range, in which the peak of modulation signals is less than or equal to the peak of the carrier signal, when the carrier frequency is sufficiently higher than modulation signal frequency and the high-order harmonics are neglected, the output voltages v ao, v bo, v co satisfy 9

6 Vdc va Vdc vb Vdc vc vao ; vbo ; vco 2 Vcar 2 Vcar 2 Vcar (3) The output line-to-line voltages v ab, v bc, v ca are expressed as follows: Vdc vab vao vbo 3 msin t 6 2 V (4) dc vbc vbo vco 3 msin( t 2) 2 Vdc vca vco vao 3 msin( t 5 6) 2 where m is the modulation index, defined as a ratio of amplitude of fundamental signals V m and peak of the triangular carrier signal V car Vm m (5) Vcar Many carrier-based PWM methods are proposed with different zero-sequence signals [2], [3]. Due to digital implementation simplicity, three of carrier-based PWM strategies including SPWM, SVPWM and DPWMMIN are widely used in three-phase inverter applications. a) b) c) Fig. 2 ZSS and modulation waveforms of PWM strategies: (a) SPWM (m = 1); (b) SVPWM (m =2/ 3); (c) DPWMMIN (m =2/ 3) When e = 0, SPWM is yielded. The narrow linear modulation range is a limitation of this strategy because the maximum modulation index reaches m max = 1, and the maximum peak of the line-to-line voltages is 0.866V dc in the linear range. By detecting the maximum and minimum values of the reference sinusoidal signals, the ZSSs of SVPWM and DPWMMIN strategies can be easily generated. Assume v 1min = min (v 1a, v 1b, v 1c ) and v 1max = max (v 1a, v 1b, v 1c ), then e = 0.5 (v 1min + v 1max ) and e = V car v 1min are the ZSSs of SVPWM and DPWMMIN, respectively. In SVPWM and DPWMMIN, the maximum peak of the line-to-line voltages is V dc corresponding the maximum modulation index m max = in the linear modulation range. Furthermore, the proper zero-sequence signal injection reduces significantly the switching losses (DPWMMIN) and the current harmonic content (SVPWM) [3]-[6]. Fig. 2 illustrates the modulation and ZSS waveforms of three above PWM strategies with the normalized peak value of carrier signal being unity. 2.2 FPGA implementation of PWM generator Fig. 3 and 4 shows the block diagram of digital carrier-based PWM generator and its flow chart, respectively. This PWM generator produces the gating signals for the three-phase two-level VSIs with some noticeable following specifications PWM schemes: SVPWM and DPWMMIN; Carrier wave frequency f c = 20 khz; Dead time t d = 0 ~ 6.4 s (tuning resolution is s). The PWM generator is designed in a module fashion with 10-bit integer arithmetic, and it consists of four internal modules of carrier wave generator, modulation wave generator, comparator and dead time generator. The PWM generator is implemented using the SmartFusion ARM-based mixed-signal FPGA controller. Fig. 3 Block diagram of digital PWM generator 10

7 2.2.2 Modulation wave generator Modulation wave generation is the most important part in dynamic reconfigurable carrier-based PWM controller. The modulation wave generator is designed such that it can switch between modulation waveforms of SVPWM and DPWMMIN. It receives external three-phase sinusoidal commands with specified amplitude and frequency to produce the modulation signals of SVPWM and DPWMMIN strategies. a) Fig. 4 Flow chart of digital PWM generator Carrier wave generator A 10-bit a bidirectional counter and a clock of 40 MHz are employed to generate a 20 khz triangular carrier wave with the peak value of 500. The counter digitally increases its value from -500 to 500 and then declines it back to -500 again over a specified period of time. The frequency of the carrier wave is determined as follows fclk f (6) c Vcar 4 where V car = 500. Fig. 5(a) and (b) show the hardware structure and the timing diagram of the carrier wave generator, respectively. b) Fig. 5 Carrier wave generator. (a) Hardware structure; (b) Timing diagram Fig. 6 Hardware structure of modulation wave generator 11

8 Fig. 6 shows the hardware structure of the modulation wave generator. Its structure can be explained following four parts. Firstly, the input three-phase sinusoidal commands are sorted to determine their minimum and maximum values. Then, ZZS generation are done according to e = 0.5 (v 1min + v 1max ) (SVPWM) and e = 500 v 1max (DPWMMIN). Finally, the desired modulation waves are generated by injecting one of ZSS signals into three-phase sinusoidal commands. The selection of the ZSS waveform is managed by a register k. The modulation waves are sampled every switching cycle at the bottom of the carrier wave Comparator The comparator module is responsible to compare the high-frequency constant-amplitude triangular carrier wave with the three-phase modulation waves to generate gating signals without dead time. The timing diagram of the a-phase comparison is shown in Fig. 7. When the a-phase modulation wave is greater than the digital value of the carrier wave, the upper gating signal at leg a is high in the next rising edge of the clock. Conversely, the upper gating signal is low in the next rising edge of the clock. The lower gating signal is produced by inverting the upper one. each falling edge of the clock. The output is forced to low until the counter value greater than the value of DT, and the output is then set high on the next rising edge of the clock. When the input gating signal is low, the counter value is cleared to 0 on the next falling edge of the clock, thereafter the output is forced to low on the next rising edge of the clock. a) b) Fig. 8 Dead time generator: (a) Hardware structure (x = 0, 1, 2, 5), (b) Timing diagram of inserting dead time in a-phase gating signals Fig. 7 Timing diagram of a-phase comparison Dead time generator The power semiconductor switches are not ideal, so they react with a certain delay to the gating signals corresponding to turn-on and turn-off. To avoid shoot-through in any leg of the power inverter, a dead time is introduced to delay the rising edges but not the falling edge of gating signals. The dead time generator is responsible to insert the delay time into the gating signals. Fig. 8(a) shows the hardware structure of the dead time generator. The main idea of the dead time generator is to use 8-bit up counters with a clock of 40MHz to produce the time delay from 0 to 6.4 s with the step resolution of s. The dead time interval t d is tuned by a register DT DT td (7) fclk Fig. 8(b) shows the timing diagram of inserting dead time in a-phase gating signals. When the input gating signal is high, the counter starts counting from 0 at 2.3 Experimental Verification The proposed PWM generator has been developed using the SmartFusion ARM-based mixed-signal FPGA controller A2F500M3F. An experimental setup of PWM control for the three-phase VSI is shown in Fig. 9, and it consists of an FPGA controller, a gate driver, a three-phase VSI, and a three-phase Y- connected R-L. It is assumed that the model load has a fixed R = 5 Ω, L = 0.8 mh and V dc = 18 V. The experimental results of open-loop control verify the performance of the proposed PWM generator. Fig. 9 Experimental setup 12

9 Fig. 10 shows the upper PWM signals of SVPWM and DPWMMIN with f c = 20 khz and f 1 = 50 Hz. The filtered waveforms of output voltages v ao, v bo, v co are illustrated Fig. 11. It is observed that the shape of these waveforms is the same to that of modulation signals. These results demonstrate the capability of the proposed PWM generator in producing exactly both SVPWM and DPWMMIN. collected from an oscilloscope LeCroy MXs-B by using PSim. These experimental results indicate that the proposed architecture can generate the desired output voltage with a wide range of fundamental frequency. Although, the fundamental frequency command is very high at 1 khz, the current trajectory is still assured to be circular, which is one of important factors to evaluate the performance of the PWM generation control. a) a) b) Fig. 10 Upper switching pattern: (a) SVPWM, (b) DPWMMIN b) a) c) Fig. 12 Performance of the PWM generator for SVPWM strategy at m = 0.8 and f 1 = 50Hz: (a) Output lineto-line voltage, (b) Output phase current, (c) Current trajectory b) Fig. 11 Filtered waveforms of output voltages v ao, v bo, v co : (a) SVPWM, (b) DPWMMIN Fig. 12 shows the output line-to-line voltage, the phase current and the current trajectory when the SVPWM strategy is applied at f 1 = 50 Hz and m = 0.8. Fig. 13 shows the current trajectory when the DPWMMIN strategy is employed at f 1 = 1 khz and m = 0.8. It is noticed that the current trajectories are drawn from measured three-phase current data Fig. 13 Current trajectory for DPWMMIN strategy at m = 1.0 and f 1 = 1 khz These experiments aim to verify the practical feasibility of the proposed dynamic reconfigurable 13

10 PWM control. The architecture designed in this paper can load two PWM schemes into a single FPGA, while conventional designs require two separate FPGAs or the device to be reprogrammed. The advantage of the dynamic reconfigurable architecture is the reduction of logic utilization by sharing the common modules in the design. The implementation report of the function modules in the PWM generator is showed in Table 1. Compared to dynamic reconfigurable PWM control developed in [14], the design in this paper is much simpler architecture because it does not need co-ordinate transformation, sector detection, and duty calculation. As a result, the total logic used for the PWM generator with 10-bit length in this paper is 577 slices, which is much lower than that of the counterpart with 8-bit length in [14]. Tab. 1 Implementation report of the function modules in the PWM generator Modules Slices Utilization Carrier wave generator % Modulation wave generator % Comparator % Dead time generator % Total % 3. Conclusion In this paper, a dynamic reconfigurable module-based PWM generator is successfully designed and implemented using FPGA. Due to taking advantage of the dynamic reconfigurable architecture, the proposed PWM generator can realize two popular PWM schemes, SVPWM and DPWMMIN. The experimental results are provided to demonstrate performance of the PWM generator; it can generate the desired output voltage with a wide range of fundamental frequency. It occupies a small fraction of FPGA s resource (only 5.1%), thus it is well suitable to incorporate with complicated inverter control algorithms (power control, output voltage regulation and motor speed control, etc.) in a single FPGA. Compared to past-developed PWM control, the design in this paper exhibits much simpler architecture and better resource utilization. Moreover, the design can be extended to support all major PWM scheme and to apply multilevel and multiphase modulator. The design concept provides reconfigurable single-chip control solution for various industrial applications of three-phase inverters. References [1] Houldsworth JA, Grant DA (1984) The use of harmonic distortion to increase the output voltage of a three-phase PWM inverter. IEEE Trans. on Industrial Application, vol. IA-20, pp [2] Zhou K, Wang D (1999) Relationship between space-vector modulation and three-phase carrier-based PWM: A comprehensive analysis. IEEE Trans. on Industrial Electronics, vol. 49, no. 1, pp [3] Hava AM, Kerkman RJ, Lipo TA (1999) Simple analytical and graphical methods for carrierbased PWM-VSI drives. IEEE Trans. on Power Electronics, vol. 14, no. 1, pp [4] Grandi G, Loncarski J (2013) Evaluation of current ripple amplitude in three-phase PWM voltage source inverter. Proc. of 8th Intern. Conf. CPE, pp [5] Jiang D, Wang F (2014) Current-ripple prediction for three-phase PWM converters. IEEE Trans. on Industrial Application, vol. 50, no. 1, pp [6] Blasko V (1997) Analysis of a hybrid PWM based on modified space-vector and trianglecomparison methods. IEEE Trans. on Industrial Application, vol. 33, vol. 3, pp [7] Tzou YY, Hsu HJ, Kuo TS (1996) FPGA-based SVPWM control IC for 3-phase PWM inverter. Proc. of IEEE Intern. Conf. on Industrial Electronics, Control and Instrumentation, vol. 1, pp [8] Hu H, Yao W, Lu Z (2007) Design and implementation of three-level space vector PWM IP core for FPGAs. IEEE Trans. on Power Electronics, vol. 22, no. 6, pp [9] Lakka M, Koutroulis E, Dollas A (2014) Development of an FPGA-based SPWM generator for high switching frequency DC-AC inverters. IEEE Trans. on Power Electronics, vol. 29, no. 1, pp [10] Agarwal A, Agarwal V (2012) FPGA realization of trapezoidal PWM for generalized frequency converter. IEEE Trans. on Ind. Information, vol. 8, no. 3, pp [11] Buccella C, Cecati C, Latafat H (2012) Digital control of power converters A survey. IEEE Trans. on Ind. Information, vol. 8, no. 3, pp [12] Monmasson E, Cirstea MN (2007) FPGA design methodology for industrial control systems - A review. IEEE Trans. on Industrial Electronics, vol. 54, no. 4, pp [13] Yang Y, Wang Y, Gao Y (2008) Design of digital three-phase SPWM signal generation system based on SoC. Proc. 9th Intern. Conf. on Solid State Integrated Circuit Technology, pp [14] Pongiannan RK, Paramasivam S, Yadaiah N (2011) Dynamically reconfigurable PWM controller for three-phase voltage-source inverters. IEEE Trans. on Power Electronics, vol. 26, no. 6, pp