AC/DC Converter Based on Instantaneous Power Balance Control for Reducing DC-Link Capacitance

Transcription

1 IEEJ Journal of Industry Applications Vol.4 No.6 pp DOI: /ieejjia Paper AC/DC Converter Based on Instantaneous Power Balance Control for Reducing DC-Link Capacitance Akira Tokumasu Member, Kazuhiro Shirakawa Member Hiroshi Taki Member, Keiji Wada Member (Manuscript received Aug. 7, 2014, revised June 9, 2015) In AC/DC converters for on-board chargers, the DC-link capacitor on the output side in a power factor correction (PFC) converter uses aluminum electrolytic capacitors in order to obtain a large capacitance for a low voltage ripple and small size. On the other hand, it is desirable to use a film capacitor instead of the aluminum electrolytic capacitors in order to obtain a long lifetime for the DC-link capacitor. However, the DC-link capacitance must be reduced as compared with the aluminum electrolytic capacitors in order to avoid increasing the size of the DC-link capacitor. This paper presents a control strategy for the AC/DC converter with a reduced DC-link capacitance. This strategy is basedon the instantaneouspowerbalance ofa PFC converterand a DC/DC converter, and it controls the AC-side input current without being affectedby thelarge ripple voltageoftwice the utility line frequencyowing to thereduced capacitance. The simulation and experimental results are presented to validate the proposed strategy, and it is confirmed that it is possible to reduce the DC-link capacitance to one-fifth when compared with the conventional AC/DC converter, without additional circuits. Keywords: AC/DC converter, instantaneous power balance, on-board charger, power factor correction 1. Introduction In the automotive industry, vehicles with a combustion engine have been converted into electric vehicles (EVs) or plugin hybrid vehicles (PHVs) with a large capacity battery (1).As for the battery charger for EVs/PHVs, a DC quick charger and an on-board charger are used on the market. The onboard charger charges the battery from a single phase utility line at home, as shown in Fig. 1. The charger requires both small volume and a long lifetime of more than 50,000 h because it is installed in the limited space of the EVs and used to charge for 8 h per day. Figure 2 shows the circuit configuration of the on-board charger. The charger consists of a power factor correction (PFC) converter and an isolated DC/DC converter. The DClink capacitors for suppressing the output voltage ripple of the PFC converter is connected on the DC-link which is the output side of the PFC converter. Aluminum electrolytic capacitors are used for the capacitors in order to obtain a large capacitance with low cost and small size (2) (4).However, it is difficult to achieve the required lifetime of more than 50,000 h because the lifetime of these capacitors is set to less than 8,000 h in the higher-temperature environment. Therefore, it is necessary to use film capacitors for the DC-link capacitors to achieve these requirements. Generally, the film capacitors have a long lifetime; however, their size is larger than that of the aluminum electrolytic capacitors under the same capacitance and the voltage rating. In order to achieve DENSO CORPORATION 1-1, Showacho, Kariya, Aichi , Japan Tokyo Metropolitan University 1-1, Minamiosawa, Hachioji, Tokyo , Japan Fig. 1. Fig. 2. Charging system of the on-board charger Configuration of the on-board charger the small size of the film capacitors, it is necessary to reduce the DC-link capacitance as compared with the conventional PFC converter. During charging of the battery, the input current of the AC/DC converter is controlled to be a sinusoidal waveform in phase with input voltage by the PFC converter for a high power factor in order to satisfy regulations (IEC ). Therefore, the frequency of the ripple in the input power waveform is twice the line frequency. On the other hand, the output power is controlled to be a constant power for charging the battery. Therefore, an energy buffer absorbing the power ripple between the input and output is required. In general, the function of the buffer is achieved by charging/discharging c 2015 The Institute of Electrical Engineers of Japan. 745

2 the DC-link capacitors at twice the line frequency. Therefore, the DC-link voltage also contains the ripple of twice the line frequency. In the case of decreasing the DC-link capacitance, twice the line frequency ripple of the DC-link voltage is increased. In this case, an increase in twice the line frequency ripple voltage affectsthe input current distortion, becausethe DC-link voltage is used for controlling the input current (5). In order to avoid the influence of the ripple voltage, a control strategy has been proposed for compensating the voltage ripples (6) (8). However, the error in manufacturing and deterioration and the approximate calculation cause a reduction in the calculation accuracy, and this distorts the input current. A compensation method for the ripple voltage using additional circuits has been proposed (9) (12), and it is possible to suppress the voltage ripple to almost zero. However, the additional circuit increases the total size of the converters for an on-board charger of more than 3 kw for residential application. A predictive control strategy has been proposed for realizing high performance (13). However, the predictive control is required implementation to the high-performance DSP or FPGA because the control is need high accuracy calculations at high speed. These conventional methods have been discussed only the PFC converter as the target. In contrast, the proposed control strategy realizes high performance without high accuracy calculations or additional circuits by coordinating a PFC converter and a DC/DC converter. The purpose of this paper is to reduce the DC-link capacitance without any additional circuit. This paper describes a control strategy for the AC/DC converter by coordinating both a PFC converter and a DC/DC converter. The instantaneous power balance concept of both the PFC converter and the DC/DC converter is used as the control strategy. In order to avoid the influence of the voltage ripple on the input current distortion, this control uses the output power of the DC/DC converter without the ripple component instead of the DC-link voltage. The simulation and experimental results are presented to validate the proposed strategy, and it is confirmed that it is possible to reduce the DC-link capacitance to one-fifth when compared with the conventional AC/DC converter. 2. Conventional Control for Reducing the Capacitance 2.1 Circuit Configuration of the On-Board Charger Figure 3 shows the circuit configuration of the on-board charger that consists of a PFC converter and an isolated DC/DC converter. The intermediate stage is the DC-link part and the DC-link capacitor is arranged this part. Table 1 shows the specifications of the circuit. 2.2 Design of the DC-Link Capacitance Figure 4 shows the electric power balance of the input side, the output side and the DC-link part of AC/DC converter in the steady state. When the input current i s is controlled to be a sinusoidal waveform in phase, and the instantaneous input power p in is expressed as follows: v s = V s sin ωt i s = I s sin ωt p in = V s I s sin 2 = 1 2 V si s (1 cos 2ωt) (1) Fig. 3. Circuit configuration of the on-board charger Table 1. Specification of on-board charger Input voltage Maximum input voltage peak Utility line frequency Max input current DC output voltage DC output power V 375 V 50/60 Hz 15 A 300 V 3kW Fig. 4. The electric power of the input side, the output side and the DC-link part where V s means the peak value of the input voltage, I s is the peak value of the input current, and ω is the utility line angular frequency. As can be observed from (1), the frequency of the ripple in the input power is twice the line frequency. On the other hand, the output power of the on-board charger is controlled to be a constant value for charging the battery, and the output power P o is expressed as follow: P o = V o I o = 1 2 V si s (2) where V o is the output DC voltage and I o is the output DC current. In order to absorb the power ripple as twice the line frequency, the instantaneous charge/discharge power p c of the DC-link capacitor is required as in (3), and the energy of the capacitor W c is obtained by (4) from (3), because W c equal to the charging electric charge of the capacitor in half cycle of the power ripple. p c = p in P o = P o cos 2ωt (3) W c = π 2 0 p c dt = P o ω (4) As can be observed from (3), the DC-link capacitor charge/discharge the power at twice the line frequency. Therefore, the capacitor voltage that contains ripple of twice the line frequency appears at the DC-link part. Moreover, the W c is obtained from the relationship between the electric power and the voltage of the capacitor as W c = 1 2 C dcv 2 dcmax 1 2 C dcv 2 dcmin (5) 746 IEEJ Journal IA, Vol.4, No.6, 2015

3 Fig. 5. The relationship between the DC-link voltage ripple and the capacitance where V dcmax is the allowed maximum voltage, and V dcmin is the allowed minimum voltage of the DC-link part in the steady state and they are determined by the voltage rating of the capacitors and power devices. The DC-link capacitance C dc is calculated by (6) from (4) and (5), and the DC-link ripple voltage V rip is expressed in (7). 2P o C dc ω(vdcmax 2 (6) V2 dcmin ) V rip = V dcmax V dcmin (7) Fig. 6. Diagram of the conventional control According to (6), DC-link capacitance is determined from the relationship between the output power, utility line angular frequency, and the allowed maximum and minimum voltage of the DC-link part. For reducing the DC-link capacitance, it is necessary to increase V dcmax or to increase the difference between V dcmax and V dcmin by increasing the ripple voltage of the DC-link part. Figure 5 shows the relationship between the DC-link capacitance C dc and the ripple voltage V ripple. The ripple voltage greatly affectsthe capacitanceas shownin Fig Effect of the DC-Link Ripple Voltage in the Conventional Control Figure 6 shows a conventional control diagram of the PFC converter in the AC/DC converter (14) (15). The control of the PFC converter has the input current control as the inner loop and the DC-link voltage control as the outer loop. In the voltage control, the amplitude of the input current reference I Lre f is produced by a proportional-integral (PI) controller from the error between the DC-link voltage v dc and the DC-link reference voltage V dcre f. In the current control, the input current reference i Lre f is generated by multiplying I Lre f and the absolute sine wave signal sin(ωt), which is in phase with the input voltage. Therefore, the input current reference i Lre f is expressed as follows: i Lre f = I Lre f sin(ωt) (8) The power factor of the PFC converter can be controlled to 1.0, because the reference signal of the PWM control is controlled such that the input current i L follows i Lre f by the PI controller. As discussed in Sect. 2.2, it is necessary to increase twice the line frequency ripple voltage of the DC-link part to reduce the DC-link capacitance. In the case of increasing the ripple voltage, twice the line frequency ripple appears at the error voltage signal Δv dc which is shown in Fig. 6. Therefore, the input current reference I Lre f contains twice the line frequency ripple component and the input current reference i Lre f is a distorted waveform including harmonic components as Fig. 7. Distortion of the input current reference by the ripple voltage of the DC-link part shown in Fig. 7. The input current contains harmonic component because the input current i L is controlled by the distorted current reference. In order to reduce the harmonic components, the response frequency of the DC voltage control needs to be set sufficiently lower than twice the line frequency. In the case of connecting the utility line of 50 Hz, the response frequency is set to less than 10 Hz. However, it is difficult to suppress the DC-link voltage fluctuation at the time of the load change by the voltage control response of less than 10 Hz. Therefore, the voltage fluctuation at load change is further increased under the condition of reducing the DC-link capacitance. As a result, the voltage rating of the power devices should be increased. Therefore, it is difficult to reduce the capacitance in the conventional control owing to the issues of the input current distortion and the DC-link voltage fluctuation during the load change. 3. Proposed Control Strategy based on the Instantaneous Power Balance 3.1 Principle of the Control When the input current power factor is set to 1.0 by the PFC converter and the output voltage and -current are controlled to be a constant value, the instantaneous power balance on both the input and the output sides is expressed as follows from (1), (2): p in = p c + P o = P o (1 cos 2ωt) (9) 747 IEEJ Journal IA, Vol.4, No.6, 2015

4 3.2 Control Strategy of Instantaneous Power Balance The propose control realizes a high power factor by controlling the duty ratio to satisfy the Eq. (9) of the input power. Figure 8 shows the control diagram of proposed control strategy. The control diagram consists of an instantaneous power control and a DC-link voltage control. In the voltage control, a control signal of DC-link voltage v dc control is produced by a PI controller from the error between the DC-link voltage v dc and the DC-link reference voltage V dcre f. In the power control, the instantaneous input power is controlled to the input power reference p inre f. The instantaneous input power reference p inre f is expressed as p inre f = P inre f (1 cos 2ωt) = (P o + v dc control )(1 cos 2ωt) (10) P inre f is the amplitude of the input power reference. P inre f is produced by summing the output power P o and the control signal of DC-link voltage v dc control. Even though the DC-link capacitance is decreased and the DC-link ripple voltage is increased, the output power of the converter can be controlled to a constant value by the DC/DC converter. Therefore, the input power reference p inre f (= P inre f (1 cos 2ωt) contains few distortion component regardless of the ripple voltage as shown Fig. 9. Thus, the proposed strategy based on the instantaneous power balance can also control the input current to a high power factor in the case of reducing the DC-link capacitance. Fig. 8. Diagram of the proposed control Moreover, the instantaneous input power reference is changed instantaneously to correspond the output power at the time of load change because the reference is generated from the output power calculated the output voltage and - current. Therefore, the input power in the proposed method is controlled to the appropriate value at faster response, and the buffering energy of the DC-link capacitors is small at the time of load change. Thus, the proposed method can reduce the voltage fluctuation at load change even when using a smaller DC-link capacitance when compared with the conventional control method. 4. Experimental Verification 4.1 Design Method of the DC-Link Capacitances As discussed in Sect. 2.2, the DC-link capacitance is determined by the output power, the maximum- and minimum- DC-link voltage and the utility line angular frequency. The allowed maximum voltage V dcmax is limited by the voltage rating of power devices and DC capacitors. The allowed minimum voltage V dcmin is limited by the peak value of the input voltage because the PFC converter operates under the condition of higher DC-link voltage than the rectified input voltage. In this experiment, V dcmax is set to 500 V, and V dcmin is determined to be 380 V because of the margin from the maximum peak of the input voltage, as summarized in Table 1. For these parameters, a DC-link capacitance of 220 uf is required from (6). Therefore, the film capacitors can be used instead of the aluminum electrolytic capacitors. Under these conditions, the DC-link ripple voltage is from 380 V to 480 V, and its average value is 434 V. Thus, the ripple current of the DC-link capacitors becomes large because of large DC-link ripple voltage. However, the film capacitor which withstand high ripple current is possible to use under the these conditions. 4.2 Design of Controllers This section deals the controller design of the proposed method. Figure 10 shows the control diagram of the AC/DC converter based on the instantaneous power balance control. Here, G il d is the transfer function from the duty ratio of the PFC converter d to the inductor current i L,andG vil is the transfer function from the inductor current i L to the DC-link voltage v dc. G il d and G vil are derived using the State Space Averaging Equation of the PFC converter. The control design for the input power control loop is as follows. In order to track the input power reference of twice utility line frequency that is 100 Hz or 120 Hz, the bandwidth of the input power control loop is set to 4 khz, and the phase margin of that is set to over 60. The open loop transfer function of the input power loop G ploop is given by: Fig. 9. No effect on input power reference by the ripple voltage of the DC-link (v s = 200 V/50 Hz, V dcref = 450 V, p out = 3kW) Fig. 10. Block diagram of the PFC converter 748 IEEJ Journal IA, Vol.4, No.6, 2015

5 Table 2. The experiment parameters Input voltage Utility line frequency Output load Output power PFC boost inductance DC-link capacitance 200 V 50 Hz 30 Ω 3kW 500 uh 220 uf Fig. 11. Bode plot of the open loop transfer function of the input power loop 2 V dc ( RC 2 G ploop = s + 1) RLC dc s 2 + Ls + R(1 d) (11) 2 where V dc is the average voltage of the DC-link, L is the inductance of the boost inductor, C dc is the capacitance of the DC-link capacitors, R is the output load of the PFC and d is the duty ratio of the PFC converter. In order to set the same parameter as the prototype converter in the following experiment, the parameters are set to 430 V, 500 μh, 220 μf and 30 Ω, respectively. From the above Eq. (11), the response of the open loop transfer function is changed by the duty ratio. Therefore, the gain design that meets the control specification in condition of several d is required. Also, it is important to take account of the lag of calculation due to consist of the digital control system in the following experiment. The delay is 50 μsec in order to control every PWM frequency of 20 khz. In this experiments, the value of gain Kp p and Kp i are determined as follows: (a) Conventional control with the DC-link capacitors of 1000 uf (b) Conventional control with the DC-link capacitors of 220 uf Kp p = (12) Kp i = (13) Figure 11 shows the bode plot of the open loop transfer function of the input power loop with above gain when the duty d is set to 0.5. From this figure, the input power loop has a bandwidth of 4 khz and phase margin of 60. The control design for the DC-link voltage controller is shown as follows. In order to avoid distortion of the input power reference p inre f from the DC-link ripple voltage, the bandwidth of the voltage controller needs to be set sufficiently lower than twice the line frequency. Especially, under the condition of high voltage ripple due to reducing the DClink capacitance, the bandwidth needs to be set further low to avoid the distortion. Therefore, the bandwidth of the controller is set to 5 Hz in this experiment. In this experiments, the value of gain Kv p and Kv i are determined as follows: Kv p = (14) Kv i = (15) 4.3 Simulation Results The operation of the proposed control is demonstrated by the simulation. Table 2 shows the simulation parameters. Figure 12 shows the simulated waveforms with the DC-link capacitors of 1000 uf or 220 uf by the conventional control and the simulated waveform with that of 220 uf by the proposed control. As can be (c) proposed control with the DC-link capacitors of 220 uf Fig. 12. Simulation waveforms by the conventional control and proposed control observed from Figs. 12(a), 12(b), the input current waveform with the DC-link capacitance of 1000 uf can be controlled a sinusoidal, however, the waveform with that of 220 uf is distorted, and its power factor is 0.87 for the conventional control. In contrast, as can be observed from Fig. 12(c), the input current can be controlled to be a sinusoidal waveform without distortion in the condition of large DC-link voltage ripple, and its power factor is 0.99 for the proposed control. Figure 13 shows the effects on the third harmonic current when the DC-link capacitance is changing. In the case of decreasing the DC-link capacitance, the third-harmonic current is increased in the conventional control. In contrast, the third harmonic current in the proposed control is almost unchanged, and it is much lower than the conventional control. Figure 14 shows the simulated transient responses at the load change by the conventional control and the proposed control. The output load is changed from 3 kw to 1.5 kw. As 749 IEEJ Journal IA, Vol.4, No.6, 2015

6 Fig. 13. Third harmonic current by the conventional control and the proposed control Experimental waveforms by the proposed con- Fig. 15. trol (a) conventional control Fig. 16. Fig. 15 The harmonic spectrum of the input current in (b) propose control Fig. 14. Simulation waveforms in the transient response can be observed from Fig. 14, the input current is controlled at a faster response by the proposed control in comparison with the conventional control. Therefore, the fluctuation voltage of the DC-link is greater than 150 V in the conventional control, whereas it is approximately 5 V or less in the proposed control. These simulation results are presented that the proposed control with small DC-link capacitor has a equal or higher performance compared with the conventional control with large DC-link capacitor. Therefore, it is unnecessary to compensate the large ripple voltage using the large DC-link capacitor or the additional circuit. In these simulations, the reduction of the DC-link capacitance is limited 220 uf by the voltage rating of the power devices and the allowed ripple current of the capacitors. However, the proposed control also operates with 120 uf by using ideal devices and increasing the DC-link voltage ripple larger in the simulations. 4.4 Experimental Results In order to verify the proposed control strategy, a prototype converter of 3 kw has been tested. The experimental parameters are the same as those in simulation conditions in Table 2. Figure 15 shows the experimental waveforms of the current and voltage by the proposed control. The input current is a sinusoidal waveform without distortion, and its power Experimental waveform in the transient re- Fig. 17. sponse factor can be controlled Figure 16 shows the spectrum of the input current harmonic. As a result, the input current harmonic is much lower than the regulated limits of the harmonic current (IEC ), and the total harmonic distortion (THD) of the input current can be controlled to 3.1%. Figure 17 shows the experimental transient responses by the proposed control method, when the output load is changed from 3 kw to 1.5 kw. As discussed in the previous chapter, the control parameters of the proposed method are set. The voltage of the DC-link fluctuation is 20 V. The DClink voltage is within device withstand voltage, but there is a difference of 20 V to the calculated result. The cause of the difference between experimental results and theoretic calculation is that the theoretical calculation does not consider the loss of the power device and inductor. Simulation was carried out in conditions without any loss in the circuit, but the loss occurs in fact and the loss is compensated by the DC-link voltage control that is slow response. 5. Conclusion This paper described an AC/DC control strategy for an onboard charger based on the instantaneous power balance for 750 IEEJ Journal IA, Vol.4, No.6, 2015

7 reducing DC-link capacitance. The proposed control strategy uses the output power of the DC/DC converter instead of the DC-link voltage in order to avoid the influence to the input current distortion by twice the line frequency ripple of the DC-link voltage. Therefore, it is possible to achieve low input current distortion in the case of a large DC-link voltage ripple owing to reduction in the capacitance. The validity of the proposed strategy is confirmed by the simulation and experimental results. The third harmonic current is improved to one-eighth as compared with the conventional control when using a DC-link capacitor of only 220 uf, which is approximately one-fifth of DC-link capacitance when compared with conventional on-board chargers. Thus, it is possible to use film capacitors of small capacitance instead of aluminum electrolytic capacitors and to realize an on-board charger with a long lifetime. In this work, the reduction of the DC-link capacitance is limited four-fifth by the voltage rating of the power devices and the allowed ripple current of the capacitors. However, the proposed control also operates with one-tenth of the capacitance by using ideal devices and increasing the DC-link voltage ripple larger in the simulations. power filter to reduce the DC bus capacitor in a hybrid electric vehicle traction drive, in Proc. Energy Conversion Congress and Exposition (ECCE), pp (2009) (12) S. Li, B. Ozpineci, and L.M. Tolbert: A Novel Concept to Reduce the DC- Link Capacitor in PFC Front-End Power Conversion Systems, in Proc. Applied Power Electronics Conference and Exposition (APEC), pp (2012) ( 13) Y.-S. Lai, C.-A. Yeh, and K.-M. Ho: A Family of Predictive Digital- Controlled PFC Under Boundary Current Mode Control, IEEE Trans. on Industrial Informatics, Vol.8, No.3, pp (2012) (14) J. Chen, A. Prodic, R.W. Erickson, and D. Maksimovic: Predictive digital current programmed control, IEEE Trans. on Power Electronics, Vol.18, No.1, pp (2003) (15) M. Fu and C. Qing: A DSP based controller for power factor correction (PFC) in a rectifier circuit, in Proc. Applied Power Electronics Conference and Exposition, Vol.1, pp (2001) Akira Tokumasu (Member) received the M.S. degree in engineering, from University of Tsukuba, Ibaraki, Japan, in Since then, he has been a researcher with DENSO CORPORATION. His research interests include power electronics and converter control. References ( 1 ) K. Yamamoto: The Background of Electric Vehcle Spread, International Electric Vehicle Technology Conference (EVTeC) (2011) ( 2 ) D. Gautam, F. Musavi, M. Edington, W. Eberle, and W. Dunford: Design of on-board charger for plug-in hybrid electric vehicle, in Proc. International Conference on Machines and Drives (PEMD), pp.1 6 (2010) ( 3 ) M. Grenier, M.G. Hosseini Aghdam, and T. Thiringer: An Automotive Onboard 3.3-kW Battery Charger for PHEV Application, IEEE Trans. on Vehicular Technology, Vol.61, No.11 pp.1 6 (2012) ( 4 ) H.J. Chae, W.Y. Kim, S.Y. Yun, Y.S. Jeong, J.Y. Lee, and H.T. Moon: 3.3 kw on board charger for electric vehicle, in Proc. International Conference on Power Electronics and ECCE Asia (ICPE & ECCE), pp (2011) ( 5 ) J. Sebastian, D.G. Lamar, M.M. Hernando, A. Rodriguez-Alonso, and A. Fernandez: Steady-State Analysis and Modeling of Power Factor Correctors With Appreciable Voltage Ripple in the Output-Voltage Feedback Loop to Achieve Fast Transient Response, IEEE Trans. on Power Electronics, Vol.24, No.11, pp (2009) ( 6 ) T. Takeshita, Y. Toyoda, and N. Matsui: Harmonic Suppression and DC Voltage Control of Single-phase PFC Converter, in Proc. Power Electronics Specialists Conference (PESC), Vol.2, No.1, pp (2000) ( 7 ) D.G. Lamar, A. Fernandez, M. Arias, M. Rodriguez, J. Sebastian, and M.M. Hernando: A Unity Power Factor Correction Preregulator With Fast Dynamic Response Based on a Low-Cost Microcontroller, in Proc. Applied Power Electronics Conference (APEC), pp (2007) ( 8 ) A. Pandey, B. Singh, and D.P. Kothari: A simple fast voltage controller for single-phase PFC converters, in Proc. Conference of the Industrial Electronics Society (IECON), Vol.2, pp (2002) ( 9 ) Y. Ohnuma and J. Itoh: A Novel Single-phase Buck PFC AC-DC Converter using an Active Buffer, in Proc. Energy Conversion Congress and Exposition (ECCE), pp (2012) (10) H. Wang and H. Chung: Study of a new technique to reduce the dc-link capacitor in a power electronic system by using a series voltage compensator, in Proc. Energy Conversion Congress and Exposition (ECCE), pp (2011) (11) S. Li, B. Ozpineci, and L.M. Tolbert: Evaluation of a current source active Kazuhiro Shirakawa (Member) received the B.S. and M.S. degrees in electrical engineering from Tokyo Metropolitan University, Tokyo, Japan in 2003 and 2007, respectively. Since 2007, he has been with DENSO COR- PORATION, Japan as a power electronics engineer, where his main responsibility is to develop power conversion circuits for automotive. His research interests include EMI design and high-frequency technique. Hiroshi Taki (Member) received the B.S. degree in electrical engineering from Shizuoka University, Japan in Since 1984, he has been working as a research engineer at DENSO CORPORATION, Japan. His research interests include engine control system, power electronics, and EMI design. Keiji Wada (Member) received the Ph.D. degree in electrical engineering, from Okayama University, Okayama, Japan, in From 2000 to 2006, he was a Research Associate with Tokyo Metropolitan University, Tokyo, Japan, and Tokyo Institute of Technology. Since 2006, he has been an Associate Professor with Tokyo Metropolitan University. His research interests include medium-voltage inverters, electromagnetic interference filters, and active power filters. 751 IEEJ Journal IA, Vol.4, No.6, 2015