Fariborz Musavi. Wilson Eberle. William G. Dunford Senior Member IEEE

Transcription

1 A High-Performance Single-Phase AC-DC Power Factor Corrected Boost Converter for plug in Hybrid Electric Vehicle Battery Chargers Fariborz Musavi Student Member IEEE Wilson Eberle Member IEEE 2 William G. Dunford Senior Member IEEE Delta-Q Technologies Corp. Burnaby, BC, Canada fmusavi@delta-q.com Abstract -- In this paper, several conventional plug in hybrid electric vehicle charger front end AC-DC converter topologies are investigated and a new bridgeless interleaved PFC converter is proposed to improve the efficiency and performance. Experimental and simulation results of a prototype boost converter converting universal AC input voltage to 4 V DC at 3.4 kw are given to verify the proof of concept, and analytical work reported in this paper. Index Terms Bridgeless PFC, Interleaved PFC, PFC boost converter, PHEV charger. I. INTRODUCTION A plug-in hybrid electric vehicle (PHEV) is a hybrid vehicle with a storage system that can be recharged by connecting the vehicle plug to an external electric power source []. The accepted charger power architecture includes an AC-DC converter with power factor correction (PFC) [2] followed by an isolated DC-DC converter with input and output EMI filters [3], as shown in Fig.. Selecting the optimal topology and evaluating power loss in the power semiconductors are important steps in the design and development of these battery chargers. The front-end AC-DC converter is a key component of the charger system, and a proper topology selection is essential to meet the regulatory requirements of input current harmonics [4-6], output voltage regulation and implementation of power factor correction [7]. The University of British Columbia Kelowna, BC, Canada 2 Vancouver, BC, Canada wilson.eberle@ubc.ca, 2 wgd@ece.ubc.ca II. REVIEW OF EXISTING TOPOLOGIES A. Conventional Boost Converter The conventional boost topology is the most popular topology for PFC applications. It uses a dedicated diode bridge to rectify the AC input voltage to DC, which is then followed by the boost section, as shown in Fig. 2. In this topology, the output capacitor ripple current is very high [8] and is the difference between diode current and the dc output current. Furthermore, as the power level increases, the diode bridge losses significantly degrade the efficiency, so dealing with the heat dissipation in a limited area becomes problematic. Due to these constraints, this topology is good for a low to medium power range up to approximately kw. For power levels >kw, typically, designers parallel semiconductors in order to deliver greater output power. The inductor volume also becomes a problematic design issue at high power. Vin D D2 D4 D3 L B Q B D B C o L O A D Fig. 2. Conventional PFC boost converter Fig.. Simplified system block diagram of a universal battery charger In the following sub-sections, three existing continuous conduction mode (CCM) AC-DC PFC boost converters are evaluated, and a solution is proposed for front end AC-DC converter. B. Bridgeless Boost Converter The bridgeless configuration topology avoids the need for the rectifier input bridge yet maintains the classic boost topology [9-6], as shown in Fig. 3. It is an attractive solution for applications >kw, where power density and efficiency are important. The bridgeless boost converter solves the problem of heat management in the input rectifier diode bridge, but it introduces increased EMI [7, 8]. Another disadvantage of this topology is the floating input

2 line with respect to the PFC stage ground, which makes it impossible to sense the input voltage without a low frequency transformer or an optical coupler. Also in order to sense the input current, complex circuitry is needed to sense the current in the MOSFET and diode paths separately, since the current path does not share the same ground during each half-line cycle [, 9]. Fig. 5. Proposed bridgeless interleaved (BLIL) PFC boost converter Fig. 3. Bridgeless PFC boost converter C. Interleaved Boost Converter The interleaved boost converter, Fig. 4, is simply two boost converters in parallel operating 8 out of phase [2-22]. The input current is the sum of the two inductor currents I LB and I LB2. Because the inductors ripple currents are out of phase, they tend to cancel each other and reduce the input ripple current caused by the boost switching action. The interleaved boost converter has the advantage of paralleled semiconductors. Furthermore, by switching 8 out of phase, it doubles the effective switching frequency and introduces smaller input current ripples, so the input EMI filters will be smaller [23-25]. It also reduces output capacitor high frequency ripple, but it still has the problem of heat management for the input diode bridge rectifiers. In the following section, a new bridgeless interleaved boost PFC converter is proposed in order to improve overall efficiency of the AC-DC PFC converter, while maintaining all the advantages of the existing solutions. Fig. 4. Interleaved PFC boost converter III. BRIDGELESS INTERLEAVED BOOST TOPOLOGY The bridgeless interleaved (BLIL) PFC converter shown in Fig. 5 is proposed to address the problems discussed in section II. This converter introduces two more MOSFETs and two more fast diodes in place of 4 slow diodes used in the input bridge of the interleaved boost PFC converter. A detailed converter description and steady state operation analysis is given in the following section. Table shows the advantages and disadvantages of each topology. TABLE I REVIEW OF EXCISING TOPOLOGIES FOR BOOST CONVERTER Conventional PFC PFC Bridgeless Interleaved Topology PFC BLIL PFC Power Rating < W < 2W < 3W > 3W EMI / Noise Fair Poor Best Fair Capacitor Ripple High High Low Low Input Main Ripple High High Low Low Magnetic Size Large Medium Small Small Efficiency Poor Fair Fair Best IV. CIRCUIT OPERATION AND STEADY STATE ANALYSIS To analyze the circuit operation, the input line cycle has been separated into the positive and negative half cycles as explained in sub-sections A and B that follow. In addition, the detailed circuit operation depends on the duty cycle, therefore positive half cycle operation analysis is provided for D >.5 in sub-section C and D <.5 in sub-section D. A. Positive Half Cycle Operation Referring to Fig. 5, during the positive half cycle, when the AC input voltage is positive, Q/Q2 turn on and current flows through L and Q and continues through Q2 and then L2, returning to the line while storing energy in L and L2. When Q/Q2 turn off, energy stored in L and L2 is released as current flows through D, through the load and returns through the body diode of Q2 back to the input mains. With interleaving, the same mode happens for Q3/Q4, but with a 8 degree phase delay. The operation for this mode is Q3/Q4 on storing energy in L3/L4 through the path L3-Q3- Q4-L4 back to the input. When Q3/Q4 turn off, energy is released through D3 to the load and returning through the body diode of Q4 back to the input mains. B. Negative Half Cycle Operation Referring to Fig. 5, during the negative half cycle, when the AC input voltage is negative, Q/Q2 turn on and current flows through L2 and Q2 and continues through Q and then L, returning to the line while storing energy in L2 and L. When Q/Q2 turn off, energy stored in L2 and L is released as current flows through D2, through the load and returns

3 through the body diode of Q back to the input mains. With interleaving, the same mode happens for Q3/Q4, but with a 8 degree phase delay. The operation for this mode is Q3/Q4 on storing energy in L3/L4 through the path L4-Q4- Q3-L3 back to the input. C. Detailed Positive Half Cycle Operation and Analysis for D >.5 The detailed operation of the proposed BLIL PFC converter depends on the duty cycle. During any half cycle, the converter duty cycle is either greater than.5 (when the input voltage is smaller than half of output voltage) or smaller than.5 (when the input voltage is greater than half of output voltage). Fig. 6 shows the three unique operating interval circuits of the proposed converter for duty cycles greater than.5 during positive half cycle operation. Waveforms of the proposed converter during these conditions are shown in Fig. 7. a) Interval : Q and Q2 are ON, and body diode of Q4 conducting b) Intervals 2 and 4: Q, Q2, Q3 and Q4 are ON c) Interval 3: Q3 and Q4 are ON, and body diode of Q2 conducting Fig. 6. BLIL PFC boost converter operating at D >.5 Fig. 7. BLIL PFC boost converter steady-state Waveforms at D >.5 Since the switching frequency of proposed converter is much higher than the frequency of input line voltage, the input voltage is considered constant during one switching period. The input voltage is given by: 2 () In a positive half cycle of the input voltage, the duty ratio of the proposed converter determines the following voltage relation: (2) The intervals of operation are explained as follows. In addition, the ripple current components are derived, enabling calculation of the input ripple current, which provides design guidance to meet the required input current ripple standard. Interval [t -t ]: At t, Q/ Q2 are ON, and Q3/Q4 are off, as shown in Fig. 6-a. During this interval, the current in series

4 inductances L and L2 increases linearly and stores the energy in these inductors. The ripple currents in Q and Q2 are the same as the current in series inductances L and L2, where the ripple current is given by: (3) The current in series inductances L3 and L4 decreases linearly and transfers the energy to the load through D3, C o and body diode of Q4. The ripple current in series inductances L3 and L4 is given by: (4) (5) Interval 2 [t -t 2 ]: At t, Q3/Q4 are turned on, while Q/Q2 remain on, as shown I Fig. 6-b. During this interval, the current in the four inductors each increase linearly, storing energy in these inductors. The ripple currents in Q and Q2 are the same as the ripple current in series inductances L and L2 as given by. (6) Similarly, the ripple currents in Q3 and Q4 are the same as the ripple current in series inductances L3 and L4: (7) (8) Interval 3 [t 2 -t 3 ]: At t 2, Q/Q2 are turned off, while Q3/ Q4 remain on, as shown in Fig. 6-c. During this interval, the current in series inductances L3 and L4 increases linearly and stores the energy in these inductors. The ripple currents in Q3 and Q4 are the same as the ripple current in series inductances L3 and L4: (9) The current in L and L2 decreases linearly and transfers the energy to the load through D, C o and body diode of Q2. The ripple current in series inductances L and L2 is given by: () () Interval 4 [t 3 -t 4 ]: At t 3, Q3/Q4 remain on, while Q/Q2 are turned on, as shown I Fig. 6-b. During this interval, the currents in the four inductors each increase linearly, storing energy in these inductors. The ripple currents in Q and Q2 are the same as the ripple currents in L and L2: (2) Similarly, the ripple currents Q3 and Q4 are the same as the ripple current in series inductances L3 and L4: (3) (4) D. Detailed Positive Half Cycle Operation and Analysis for D <.5 Fig. 8 shows the operating interval circuits of the proposed converter for duty cycles smaller than.5 during the positive half cycle. The waveforms of the proposed converter during these conditions are shown in Fig. 9. The intervals of operation are explained as follows. a) Intervals and 3: Body diodes of Q2 and Q4 conducting b) Interval 2: Q and Q2 are ON, and body diode of Q4 conducting c) Interval 4: Q3 and Q4 are ON, and body diode of Q2 conducting Fig. 8. BLIL PFC boost converter operating at D <.5

5 Interval 2 [t -t 2 ]: At t, Q/Q2 turn on, while Q3/Q4 remain off, as shown in Fig. 8-b. During this interval, the current in series inductances L and L2 increases linearly, storing energy in these inductors. The ripple currents in Q and Q2 are the same as the current in series inductances L and L2, where the ripple current is given by: Fig. 9. BLIL PFC boost converter steady-state waveforms at D <.5 Interval [t -t ]: At t, Q and Q2 turn off, while Q3 and Q4 remain off, as shown in Fig. 8-a. During this interval, the current in series inductances L and L2 decreases linearly and transfers the energy to the load through D, C o and body diode of Q2. The ripple current in series inductances L and L2 is: (5) In addition, the current in the series inductances L3 and L4 also decreases linearly, transferring the energy to the load through D3, C o and body diode of Q4. The ripple currents in series inductances L3 and L4 is: (5) The input current is the sum of currents in L/L2 and (6) (7) The current in series inductances L3 and L4 decreases linearly and transfers the energy to the load through D3, C o and body diode of Q4. The ripple current in L3 and L4 is: (8) The input ripple current is the sum of the currents in L/L2 and (9) Interval 3 [t 2 -t 3 ]: At t 2, Q/Q2 are turned off, while Q3/Q4 remain off, as shown in Fig. 8-a. During this interval, the current in series inductances L and L2 decreases linearly and transfers the energy to the load through D, C o and body diode of Q2. The ripple current in series inductances L and L2 is given by: (2) Similarly, the current in the series inductances L3 and L4 also decreases linearly, transferring the energy to the load through D3, C o and body diode of Q4. The ripple current in series inductances L3 and L4 is: (2) The input current is the sum of currents in L/L2 and (22) Interval 4 [t 3 -t 4 ]: At t 3, Q3/Q4 are turned on, while Q/Q2 remain off, as shown in Fig. 8-c. During this interval, the current in series inductances L3 and L4 increases linearly and stores the energy in these inductors. The ripple currents in Q3 and Q4 are the same as the current in series inductances L3 and L4, where the ripple current is given by: (23) The current in series inductances L and L2 decreases linearly and transfers the energy to the load through D2, C o and body diode of Q4. The ripple current in L and L2 is: (24) (25) The operation of converter during the negative input voltage half cycle is similar to the operation of converter during the positive input voltage half cycle.

6 V. SIMULATION RESULTS PSIM simulation software was used to verify steady state waveforms of each component. Fig. shows the PSIM simulation circuits of the proposed BLIL PFC converter. As it can be seen the power stage section of converter consists of four boost inductors Ld to Ld4, four fast boost diodes Db to Db4, four switches Q to Q4 and their body diodes Dq to Dq4. Also it consists of two current loops and one voltage loop. The sensed input voltage is multiplied by the compensated output voltage, and then generates a control signal to be compared with the switching career waveforms to generate the gating signals for main FETs. Fig. shows the PSIM simulation results of a BLIL PFC boost converter. The input current is in phase with input voltage, and it has close to unity power factor. Also the output voltage is regulated at around 4V, with a 2 Hz low frequency ripple. The converter is operating at 7 khz switching frequency, 24 V input voltage and 3.4 kw output power. Fig.. PSIM simulation circuit for the proposed BLILL PFC boost converter Fig.. Simulation waveforms for the proposed BLIL PFC boost converter including output voltage, input voltage and input current VI. EXPERIMENTAL RESULTS An experimental prototype, illustrated in Fig. 2, was built to verify the operation of the proposed converter. Fig. 3 shows the input voltage, input current and PFC bus voltage of the converter under the following test conditions: V in = 24 V, I in = 5 A, P o = 34 W, f sw = 7 khz. The input current is in line and phase with the input voltage, and its shape is close to a sinusoidal waveform. In order to verify the quality of the input current, its

7 harmonics up to 39 th harmonic order are given and compared with the EN standard. Fig. 4 shows the input current harmonics versus harmonic numbers at full load for 2 V and 24 V input voltages. It is clearly shown that the generated harmonics are well below IEC standard for the input line harmonics which is required for PHEV chargers. In Fig. 5, the input current total harmonics distortions are given at full load and for 2 V and 24 V input voltages. It can be noted that mains current THD are smaller than 5% from 5% load to full load and it is compliant to IEC Another parameter to show the quality of input current is power factor. In Fig. 6, the converter power factor is shown at full load for different input voltages. As it can be seen, power factor is greater than.99 from 5% load to full load. is available from the mains feed to charge the batteries, reducing charging time and electricity costs. Harmonic Current (A) EN Class D Limits (A) Amplitude (A) Vin = 2 V Amplitude (A) Vin = 24 V Harmonics Order Fig. 4. Input current harmonics at full load for Vin = 2 V and 24 V 2 cm Fig. 2. Breadboard prototype of BLIL PFC boost converter THD (%) Vin=24 Vin=2 Output Voltage Input Voltage 5 5 Output Power (W) Fig. 5. Total harmonics distortion vs. output power at Vin = 2V and Vin = 24V Input Current Fig. 3. Proposed BLIL PFC experimental waveforms; Test Condition: Po = 34W, Vin = 24V, Iin = 5A Power factor Vin=24 Vin=2 The efficiency of converter versus output power for different input voltages is provided in Fig. 7. High efficiency over entire load range is achieved in this topology, enabling fewer problems with heat dissipation and cooling systems. Furthermore, a higher efficiency means more power Output Power (W) Fig. 6. Power Factor vs. output power at Vin = 2V and Vin = 24V

8 Efficiency (%) 5 5 Output Power (W) Fig. 7. Efficiency vs. output power at Vin = 9V, Vin = 2V, Vin = 22V and Vin = 24V VII. CONCLUSION A high performance AC-DC boost converter topology has been presented in this paper for the front-end AC-DC converter in PHEV battery chargers. The proposed converter topology has been analyzed and performance characteristics presented. A prototype converter was built to verify the proof-of-concept. The theoretical waveforms were compared with the simulation results and the results taken from prototype unit. Also some key experimental waveforms are given. Finally input current harmonics at each harmonic order was compared more explicitly with the IEC standard limits. The total harmonics distortion and power factor was measured on prototype unit and showed great results. The converter topology shows a high input power factor, high efficiency over entire load range and excellent input current harmonics. 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