16-Bit Audio ANALOG-TO-DIGITAL CONVERTER

Transcription

1 P 6-Bit Audio ANALOG-TO-DIGITAL CONVETE FEATUES LOW COST/HIGH PEFOMANCE 6-BIT AUDIO A/D CONVETE FAST 5µs MAX CONVESION TIME (4µs typ) VEY LOW THDN ( typ 88dB at FS; max 8dB) ±V INPUT ANGE TWO SEIAL OUTPUT MODES POVIDE VESATILE INTEFACING COMPLETE WITH INTENAL EFEENCE AND CLOCK IN 8-PIN PLASTIC DIP ±5V TO ±5V SUPPLY ANGE (6mW Power Dissipation) APPLICATIONS DSP DATA ACUISITION TEST INSTUMENTATION SAMPLING KEYBOAD SYNTHESIZES DIGITAL AUDIO TAPE BOADCAST AUDIO POCESSING TELECOMMUNICATIONS DESCIPTION The P is a low-cost 6-bit analog-to-digital converter which is specifically designed and tested for dynamic applications. It features very fast, low distortion performance (4µs/ 88dB THDN typical) and is complete with internal clock and reference circuitry. The P is packaged in a reliable, lowcost 8-pin plastic DIP and data output is available in user-selectable serial output formats. The P is ideal for digital audio tape (DAT) recorders. Many similar applications such as digital signal processing and telecom applications are equally well served by the P. The P uses a SA technique. Analog and digital portions are efficiently partitioned into a highspeed, bipolar section and a low-power CMOS section. The P has been optimized for excellent dynamic performance and low cost. Audio Input Convert Command External Internal Circuit 6-bit D/A Converter 6-bit SA Timing Control Comp Serial Output Serial Output Output International Airport Industrial Park Mailing Address: PO Box 4 Tucson, AZ 8574 Street Address: 67 S. Tucson Blvd. Tucson, AZ 8576 Tel: (5) 746- Twx: Cable: BBCOP Telex: FAX: (5) Immediate Product Info: (8) Burr-Brown Corporation PDS-989A Printed in U.S.A. October, 99

2 SPECIFICATIONS ELECTICAL At T C = 5 C, V DD = 5V, and ±V CC = ±V, and one minute warm-up in convection environment, unless otherwise noted. P PAAMETE CONDITIONS MIN TYP MAX UNITS ESOLUTION 6 Bits INPUT/OUTPUT ANALOG INPUT Input ange V Input Impedance.5 kω DIGITAL INPUT/OUTPUT Logic Family TTL Compatible CMOS Logic Level: V IH I IH = 4µA 5.5 V V IL I IL = µa.8 V V OH I OH = TTL Loads.4 V V OL I OL = TTL Loads.4 V Data Format Serial BOB or BTC Convert Command Negative Edge () Pulse Width 5 5 ns CONVESION TIME 4 5 µs DYNAMIC CHAACTEISTICS SIGNAL-TO-NOISE ATIO (SN) () f S = khz/t CONV = 4µs () f = khz (db) BW = khz 9 db (4) f = khz (db) BW = khz 8 db TOTAL HAMONIC DISTOTION (5) f S = khz/t CONV = 4µs f = khz (db) BW = khz 9 db f = 9kHz (db) BW = khz 9 db f = khz (db) BW = khz 9 db f = 9kHz (db) BW = khz 89 db TOTAL HAMONIC DISTOTION NOISE (6) f S = khz/t CONV = 4µs f = khz (db) BW = khz 88 8 db f = khz ( db) BW = khz db f = khz ( 6dB) BW = khz 4 db f = 9kHz (db) BW = khz 87 db f = khz (db) BW = khz 8 db f = 9kHz (db) BW = khz 8 db TANSFE CHAACTEISTICS ACCUACY Gain Error ± % Bipolar Zero Error ± mv Differential Linearity Error ±. % of FS (7) Integral Linearity Error ±. % of FS Missing Codes None 4 Bits (8) DIFT Gain C to 7 C ±5 ppm/ C Bipolar Zero C to 7 C ±4 ppm of FS/ C POWE SUPPLY SENSITIVITY V CC ±.8 %FS/%V CC V CC ±. %FS/%V CC V DD ±. %FS/%V DD POWE SUPPLY EUIEMENTS Voltage ange: V CC V V CC V V DD V Current: V CC V CC = V 5 ma V CC V CC = V ma V DD V DD = 5V 7 ma Power Dissipation ±V CC = ±V 575 mw TEMPEATUE ANGE Specification 7 C Storage 5 C Operating 5 85 C NOTES: () When convert command is high, converter is in a halt/reset mode. Actual conversion begins on negative edge. See detailed text on timing for convert command description when using external clock. () atio of Noise rms/signal rms. () f = input frequency; f S = sample frequency (P and SHC7 in combination); BW = bandwidth of output (based on FFT or actual analog reconstruction using a khz low-pass filter). (4) eferred to input signal level. (5) atio of Distortion rms/signal rms. (6) atio of Distortion rms Noise rms/signal rms. (7) FS: Full-Scale ange = 6Vp-p. (8) Typically no missing Codes at 4-bit resolution.

3 PIN ASSIGNMENTS PIN NAME I/O DESCIPTION Analog In I Analog Signal Input (.5kΩ impedance). V CC I Analog power supply ( 5V to 5V). MSB Adjust I Internal adjustment point to allow adjustment of MSB major carry. 4 V DD I Power connection for comparator (5V). 5 No Connection No internal connection. 6 Comparator Common I Comparator common connection. Connect to ground. 7 MSB O Parallel output of bit (MSB) inverted. 8 BTC/BOB Select I Two s complement (open) or straight binary (grounded) data output format selection. 9 O Output signal held high until conversion is complete. Out O Internal clock output generated from C network on pins and (also present when external clock is used lagging external clock by ~4ns and same duty cycle). C I C connection point used to generate internal clock. Sets clock high time. See text for details. C I C connection point used to generate internal clock. Sets clock low time. See text for details. S OUT O Internal shift register containing the previous conversion result. (Alternate latched data output mode). 4 V DD I Power connection for 5V logic supply. 5 S OUT O Primary real-time data output synchronized to clock out. 6 External I External clock input point (internal clock must be disabled). 7 Int/Ext Select I Selects either internal or external clock mode (low = internal; open = external). 8 Short Cycle I Terminates conversion at less than 6 bits (open for 6-bit mode). See text for details. 9 Convert Command I Starts conversion process (can optionally be generated internally). S OUT Latch I Latches previous conversion result for readout (must be issued with the S OUT clock to initiate latch and an internal convert command). S OUT I Used to read out internally latched data from previous conversion. Digital Common I Digital grounding pin. V CC I Analog supply connection (5V to 5V). 4 V POT O Voltage output (~.5V) for optional adjustment of MSB transition. 5 eference Decouple I eference decoupling point. 6 Analog Common I Analog grounding pin. 7 eference Out O V reference out. Should not be used except as shown in connection diagram. 8 Speed Up I Connection point for a capacitor to speed reference settling. See text for details. NOTE: Analog and digital commons are connected internally. INPUT/OUTPUT ELATIONSHIPS DIGITAL OUTPUT ANALOG INPUT CONDITION BTC BOB.99998V Full Scale 7FFF Hex FFFF Hex.V Full Scale 8 Hex Hex.V Bipolar Zero Hex 8 Hex.9V Zero- FFFF Hex 7FFF Hex PACKAGE INFOMATION ABSOLUTE MAXIMUM ATINGS V CC to Analog Common... to 6.5V V CC to Analog Common... to 6.5V V DD to Analog Common... to 7V Analog Common to Digital Common... ±.5V Logic Inputs to Digital Common....V to V DD.5V Analog Inputs to Analog Common... ±6.5V Lead Temperature (soldering, s)... C Stresses above these ratings may permanently damage the device. PACKAGE DAWING MODEL PACKAGE NUMBE () P 8-Pin Plastic DIP 5 NOTE: () For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BU-BOWN assumes no responsibility for inaccuracies or omissions. BU-BOWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BU-BOWN does not authorize or warrant any BU-BOWN product for use in life support devices and/or systems.

4 TYPICAL PEFOMANCE CUVES At T A = 5 C, V CC = ±5V, unless otherwise noted. BPZ Error (mv) BPZ EO vs TEMPEATUE mv 9mV 8mV 7mV 6mV 5mV 4mV mv mv mv Temperature ( C) Number of Units BIPOLA GAIN EO as % FS 5 C; N = UNITS % FS % / % V CC PS at FS INPUT V CC V DD Temperature ( C) % / % V CC PS at FS INPUT V CC V DD Temperature ( C). V EF vs TEMP I SS vs SUPPLY VOLTAGE. V CC V (V) EF Current (ma) Temperature ( C) 5 4 V CC Supply Voltage (V) 4

5 TYPICAL PEFOMANCE CUVES (CONT) At T A = 5 C, V CC = ±5V, unless otherwise noted. 7. INTEGAL NONLINEAITY at 5 C.4 DIFFEENTIAL NONLINEAITY at 5 C INTEGAL NONLINEAITY at C.4 DIFFEENTIAL NONLINEAITY at C INTEGAL NONLINEAITY at 5 C.4 DIFFEENTIAL NONLINEAITY at 5 C

6 TYPICAL PEFOMANCE CUVES (CONT) At T A = 5 C, V CC = ±5V, unless otherwise noted. Histograms done with conversion time = 8µs. 7. INTEGAL NONLINEAITY at 7 C.8 DIFFEENTIAL NONLINEAITY at 7 C INTEGAL NONLINEAITY at 5 C.5 DIFFEENTIAL NONLINEAITY at 5 C INTEGAL NONLINEAITY EO (to 4-Bit ). DIFFEENTIAL NONLINEAITY EO (to 4-Bit )..5 Differential BIN BIN 6

7 TYPICAL PEFOMANCE CUVES (CONT) At T A = 5 C, V CC = ±5V, unless otherwise noted. Histograms done with Conversion Time = 8µs. Magnitude (db) SPECTAL ESPONSE, f IN khz Input Frequency 976.6Hz Fund:.7dB 6th: 5.dB nd: 87.8dB THD: 87.dB rd: 97.4dB SN: 8.5dB 4th:.5dB SINAD: 8.9dB 5th: 7.86dB Magnitude (db) SPECTAL ESPONSE, f IN khz Input Frequency 997.7Hz Fund:.8dB 6th:.44dB nd: 9.dB THD: 88.dB rd: 9.59dB SN: 79.5dB 4th:.dB SINAD: 78.7dB 5th: 9.dB Frequency (khz) Frequency (khz) Magnitude (db) SPECTAL ESPONSE, f IN khz Input Frequency 976.6Hz Fund:.7dB 6th:.6dB nd: 8.6dB THD: 76.75dB rd:.44db SN: 6.79dB 4th:.5dB SINAD: 6.65dB 5th:.6dB Magnitude (db) SPECTAL ESPONSE, f IN khz Input Frequency 997.7Hz Fund: 9.94dB 6th: 7.dB nd: 5.69dB THD: 7.8dB rd: 95.9dB SN: 6.6dB 4th: 6.7dB SINAD: 6.8dB 5th: 97.57dB Frequency (khz) Frequency (khz) Magnitude (db) SPECTAL ESPONSE, f IN khz Input Frequency 976.6Hz Fund: 6.6dB 6th: 6.dB nd: 9.8dB THD: 4.5dB rd: 8.dB SN:.7dB 4th: 4.66dB SINAD:.69dB 5th: 4.7dB Magnitude (db) SPECTAL ESPONSE, f IN khz Input Frequency 997.7Hz Fund: 59.96dB 6th:.dB nd: 9.9dB THD: 4.6dB rd: 4.49dB SN:.9dB 4th: 6.4dB SINAD:.88dB 5th:.8dB Frequency (khz) Frequency (khz) 7

8 TYPICAL PEFOMANCE CUVES (CONT) At T A = 5 C, V CC = ±5V, unless otherwise noted. THDN (%) THDN vs CONVESION TIME (db) Convert Time (µs) THDN vs CONVESION TIME ( db) THEOY OF OPEATION The P is a successive approximation A/D converter; this type of converter is well suited to high speed and resolution. The accuracy of a successive approximation converter is described by the transfer function shown in Figure. All successive-approximation A/D converters have an inherent quantization error of ±/. The remaining errors in the A/D converter are combinations of analog errors due to the linear circuitry, matching and tracking properties of the ladder and scaling networks, power supply rejection, and reference errors. In summary, these errors consist of initial errors including Gain, Offset, Linearity, Differential Linearity, and Power Supply Sensitivity. Gain drift over temperature rotates the line (Figure ) about zero, and Offset drift shifts the line left or right over the operating temperature range. Total Harmonic Distortion Noise (THDN) is a measure of the magnitude and distribution of the Linearity Error, Differential Linearity Error, and Noise, as well as quantization errors. The THDN specification is most useful in audio or dynamic signal processing applications. To be useful, THDN should be specified for both high level and low level input signals. This error is unadjustable and is the most meaningful indicator of A/D converter accuracy for dynamic applications. THDN (%) THDN (%) Convert Time (µs) THDN vs CONVESION TIME ( 6dB) Convert Time (µs) DYNAMIC ANGE Dynamic range is a measure of the ratio of the smallest signals the converter can resolve to the full scale range and is usually expressed in decibels. The theoretical dynamic range of a converter is approximately 6 x n, where n is the number of bits of resolution. A 6-bit converter would thus have a theoretical dynamic range of 96dB. The actual useful dynamic range is limited by noise and linearity errors and is therefore somewhat less than the theoretical limit. Digital Output (BTC Code)* All Bits On Gain Error / Offset Error / All Bits Off E IN On Analog Input FS E IN Off FS ) *See Input/Output elationship Table for code definitions. ( ( ) FIGUE. Input vs Output for Ideal Bipolar A/D Converter. 8

9 B&K Digital Oscillator Sync SHC7 Serial-To-Parallel Convert Command Timing IEEE-488 Communication Signal Level (db) Frequency (khz) Digital Distortion Analyzer Software DataPhysics Corp HP- Scientific Computer FIGUE. Block Diagram of Distortion Test Circuit. DISCUSSION OF SPECIFICATIONS TOTAL HAMONIC DISTOTION Evaluating distortion specifications can be a difficult task, as distortion is often specified in different ways. Total Harmonic Distortion (THD) is defined as the ratio of the square root sum of the squares of the value of rms harmonics to the value of the rms fundamental and is expressed in percent or db. Note that this measurement only includes energy present in those frequencies which would contain harmonics, and therefore is less than Total Harmonic Distortion plus Noise. The Total Harmonic Distortion plus Noise (THDN) is defined as the ratio of the square root of the sum of the squares of the value of the rms harmonics and rms noise to the value of the rms fundamental and is expressed in percent or db. This is the most meaningful measurement of a dynamic converter s performance because it includes all energy present in the signal that is not fundamental. A block diagram of the test circuit used to measure the THD and THDN of the is shown in Figure. This digital system is capable of differentiating harmonic energy and noise; conventional distortion analyzers which operate on a tracking notch filter principle cannot distinguish this energy, and therefore only measure THDN. Unfortunately, in the past, these systems were used for measuring distortion performance of converters, and the distortion was often simply specified as THD, when in fact it was really THDN. For this reason, it is often confusing to compare specifications of converters unless one knows exactly what was being measured. If we assume that the error due to the test circuit of Figure is negligible, then the rms value of the error referred to the input can be shown to be THDN = N N [ E L (i) E (i) E N (i)] i= E rms X % where N is the number of samples, E L (i) is the linearity error at each sample, E (i) is the quantization error at each B&K Digital Oscillator Sync SHC7 Serial-To-Parallel Convert Command Timing 64k Memory Error () HP- Scientific Computer IEEE Codes FIGUE. Block Diagram of Histogram Test. 9

10 MSB Adjust S/H Amplifier Convert Command S/H Control Audio Oscillator Shibasoku AG6A or Equivalent DUT P A B S C D Timing Control Logic Latch 74LS64 74LS7 Latch Enable 6-Bit DAC Deglitcher Control Deglitcher Shibasoku AG6A or Equivalent Low-Pass Filter Programmable Gain Amp Distortion Tester Toko Model 98BL-N or PCM or Equivalent Attenuation (db) LOW-PASS FILTE CHAACTEISTICS Frequency (MHz) FIGUE 4. Production Distortion Noise Test System Block Diagram. eference A(S/H) B (CC) S () () C (Data Latch) D (Deglitcher Control) FIGUE 5. Timing Diagram for Figure 4. sample, and E N (i) is the residual noise energy present at each sample. Similarly, THD alone can be expressed as THD = 5ns <8µs N N i= 5ns 8.5µs E () i L E rms X % These expressions indicate that there is a correlation between THDN and the square root of the sum of the squares of the linearity errors at each digital word of interest. In order to find this error at each code, a histogram test must be performed on the, as illustrated in Figure. The histogram for every converter is unique, as the linearity errors from converter to converter will vary in their placement along the transfer function. Typical histogram data is shown in the Typical Curves. However, this expression for THDN does not mean that the worst case linearity error of the A/D is directly correlated to the THDN because the digital output words from thea/d vary according to the amplitude and frequency of the sine wave input as well as the sampling frequency. For the the test sampling frequency was chosen to be khz, near the s fastest rate of conversion. The test frequencies used vary within the audio range, and are stepped in amplitude from db, to db, to 6dB. In manufacturing the, the test system shown in Figure 4 is used to test for guaranteed THDN. ACCUACY VS CONVESION TIME AND INPUT SIGNAL LEVEL The relationship of THD vs input signal level and THD vs conversion time is shown is the typical curves. Slowing the conversion time to more than 8µs results in little added benefit in terms of THDN. For applications which are not as concerned with dynamic performance but require DC accuracy and linearity, it is best to use the at the longest conversion time possible for the system requirements. Slowing the to 8µs-µs conversion time results in a substantial improvement in linearity. The typical curves show DNL and INL plots for a typical device, at an 8µs conversion time. Due to the segmented architecture of the internal DAC used in the successive approximation conversion technique, significant differential linearity errors occur near bits and 4. Allowing more settling time for the DAC (by slowing the conversion speed) will improve this differential linearity error and give equivalent performance to more costly DCspecified -bit to 4-bit A/D converters. SYSTEM DESIGN CONSIDEATIONS DIGITAL CICUIT CONNECTIONS The comes complete with an internal clock circuit, or it may be clocked by an external clock. Choosing which mode to operate with depends upon the application for which the will be used. In an application where the sample rate may not be fixed (transient recording, etc.), using the internal clock set to give a very fast conversion may be the best solution. In systems where the sample rate is fixed, an external clock is probably the better choice since it will allow the digital system design to be synchronous.

11 In either case, the requires 7 clock cycles to complete a conversion. To calculate the clock frequency necessary for a given conversion time, the following equation may be used: f CLOCK = 7 Conversion Time The internal clock operates only during a conversion, and is gated on by the falling edge of the convert command. See Figure 6. The internal clock is available on pin, Out. The high and low time of this clock is set by C and C respectively. The duty cycle of the clock should be between % to 8%, and may be set to 5% for simplicity. High Time (in ns) =. C Low Time (in ns) =. C in kω; C in pf. These equations are approximate (±5%); they should be used for determining an initial part value which will then need to be tweaked for accurate timing. If highly accurate time bases are required, use of an external clock is recommended. The external clock is applied at pin 6, and the Int/Ext select (pin 7) should be left open (an internal pullup resistor assures that the logical state of an open pin is ). Using the external clock requires careful placement in time of the convert command. Figure 7 diagrams the recommended timing with an external clock. A simple circuit which assures the proper timing of the convert command is shown in Figure 8. Due to the design of the /Logic chip in the, a conversion is begun inside the by an asynchronous state machine. This places stringent requirements on the timing of the convert command, as improper timing can cause metastable states within this state machine. Using the circuitry shown in Figure 8, the user is assured of consistent operation, and these invalid states within the state machine are entirely avoided. (Note that this is not a consideration when using an internal clock, as nothing is being clocked when a convert command is presented to the ). The Out function is a gated form of the external clock, i.e. the 7 clock cycles used in the conversion are present on this pin during conversion. This allows use of a continuous external clock, with Out being the clock that the converter is actually using for conversion. Note that this is simply a delayed (~4ns) version of the external clock, and will have the same frequency and duty cycle. The S OUT Latch enables the user to latch data from the previous conversion and read it out at a higher speed than the convert clock. This feature allows the converter to easily interface to digital filtering necessary for oversampling. See Figure 9 for timing information in this mode. In this mode, the generates its own internal convert command when the S OUT goes high within ±5ns of S OUT Latch going low; the external convert command may not be used, and pin 9 must be grounded. The timing diagram shows the recommended timing for using this mode. After the S OUT Latch control signal goes low, data from the SA is loaded into the S OUT latch on the next rising edge of the S OUT. This clock edge should occur prior to the next rising edge of the conversion clock (internal or external), since the SA will reset itself prior to the latching Convert Command Out T T T 4 T T 5 T 7 S OUT Data TIMING SPECIFICATIONS T 6 T A = 5 C, V DD = 5V, guaranteed by sample testing; these parameters are not % tested in production. TIME (ns) TIME DESCIPTION MIN TYP MAX T CONVET COMMAND pulse width 5 5 () T Delay from falling edge of CONVET COMMAND to rising edge of CLOCK OUT T Delay from rising edge of CLOCK OUT to rising edge of STATUS 8 T 4 INTENAL CLOCK pulse width T 5 INTENAL CLOCK period T 6 Delay from rising edge of CLOCK OUT to bit data valid 7 5 T 7 Delay from rising edge of 7th clock pulse to falling edge of STATUS 5 NOTE: () When using the internal clock, the clock does not operate until the Convert Command is low. It is therefore possible to keep the convert command high indefinitely, thereby keeping the in a halt mode. The conversion cycle begins on the falling edge of convert command, and convert command must remain low during the entire conversion cycle in order to make the operate properly. FIGUE 6. Conversion Timing when using Internal.

12 Ext T T T T 5 Convert Command T 4 T 6 Out T 7 T 9 S OUT Data TIMING SPECIFICATIONS T 8 T A = 5 C, V DD = 5V, guaranteed by sample testing; these parameters are not % tested in production. TIME (ns) TIME DESCIPTION MIN TYP MAX T EXTENAL CLOCK pulse width 5 5 () T EXTENAL CLOCK period 4 9 () T Delay from falling edge of EXTENAL CLOCK to rising edge of CONVET COMMAND 4 T 4 CONVET COMMAND pulse width 5 T 5 Delay from falling edge of CONVET COMMAND to rising edge of EXTENAL CLOCK 5 4 T 6 Delay from falling edge of CONVET COMMAND to rising edge of CLOCK OUT T 7 Delay from rising edge of CLOCK OUT to rising edge of STATUS 6 T 8 Delay from rising edge of CLOCK OUT to bit data valid 5 7 T 9 Delay from rising edge of 7th clock pulse to falling edge of STATUS 8 NOTE: () The does not contain dynamic digital circuitry, and can be clocked as slowly as the user wishes. In typical applications, the longest clock period may be as long as µs. FIGUE 7. Conversion Timing when using External. if the convert clock rises before the S OUT. This condition is avoided as long as the frequency of S OUT is at least.5 times that of the conversion clock. The internal convert command is generated upon S OUT Latch going low, and its falling edge occurs upon the first falling edge of S OUT after S OUT Latch goes low. S OUT Latch should remain low for at least cycles of S OUT to insure proper latching. In many applications, the S OUT Latch can be the f S signal present in many digital audio systems, typically known as WDCK. Figure includes an example of this application. The data read out on S OUT is from the conversion previously performed, while the data that is present on S OUT is the real time readout of the successive approximation as it occurs. SHOT CYCLE The has the ability to be short cycled to a resolution less than 6 bits. This is accomplished by driving the Short Cycle pin (pin 8) low when the conversion is to be terminated, and holding it low until the next convert command is given. The circuit in Figure will accomplish this function. 5V Sample (Convert) (Ext) D C D C Convert Command D (Ext) Sample (Convert) Convert Command FIGUE 8. Convert Command Timing Circuit for Use with External.

13 S OUT Ext T T T 4 T S OUT Latch Data (n ) Data n S OUT Data MSB MSB Data Sample n Data (n ) S OUT Data MSB MSB T A = 5 C, V CC = 5V, guaranteed by sample testing; these parameters are not % tested in production. TIME (ns) TIME DESCIPTION MIN TYP MAX T S OUT Latch pulse width 5 T S OUT Cycle 4 T Delay from rising edge of CLOCK OUT to bit data valid T 4 Delay from rising edge of S OUT to rising edge of Ext 5 5 FIGUE 9. Timing when using S OUT Latch. WDCK (S OUT Latch) (f S) Ext 8f ( S ) Word Word A s Serial Data Serial Out MSB MSB S OUT 8 f ( S ) Word A's Serial Data Serial Out MSB MSB FIGUE. Application Example of S OUT Operation. B Word A s Serial Data 5V LS Out P Convert Command 9 A A 4 B CL 5 C 6 A D E CL LS9 5V Jumper 4 5 kω x 4 LS () 8 Short Cycle NO OF BITS JUMPE X X X X 4 X X X X X X X X X X 9 X X X 8 X X X X: Off : On FIGUE. Short Cycle Circuit. CC 4 Short Cycle Conversion Time FIGUE. Short Cycle Operation Timing.

14 If Short Cycle is not held low until the next convert command is issued, the line will go high in synchronization with Short Cycle. This is because the operation of the line becomes invalid after Short Cycle is asserted. An example of the Short Cycle operation is shown in Figure. In those systems where a user may not be using a continuous external clock, it is necessary to assure that a falling edge of external clock occurs after short cycle goes low. This is because conversion actually stops on the first falling edge of external clock after Short Cycle goes low. ANALOG CICUIT CONSIDEATIONS Layout Precautions Analog and Digital Common are connected internally in the, and should be connected together as close to the unit as possible, preferably to a large ground plane under the ADC. Low impedance analog and digital common returns are essential for low noise performance. Coupling between analog inputs and digital lines should be minimized by careful layout. The input pin (pin ) and the MSB adjust pin (pin ) are both extremely sensitive to noise; digital lines should be kept away from these pins to avoid coupling digital noise into the sensitive analog circuitry. Contact factory for a recommended PCB layout for the. Power Supply Decoupling The power supplies should be bypassed with tantalum or electrolytic capacitors as shown in Figure to obtain noise free operation. These capacitors should be located as close to the ADC as possible. Bypass the µf electrolytic capacitors with.µf ceramic or polystyrene capacitors for improved high frequency performance. VCC decoupling capacitor should range from.µf to 4.7µF; larger values can cause reference settling problems which may manifest themselves as missing codes. This capacitor should be as close to the as possible, to minimize the potential for coupling noise into the device; with a good board layout it may be best to leave this capacitor out of the circuit altogether, as the extra lead length may only cause more noise in the reference. Pin 7 is a decoupling point to ground, as well as the output of the V reference. This point should not be used to supply reference voltage to external circuitry unless it is buffered. A.µF capacitor is recommended, and the capacitor used here should not exceed 4.7µF. Pin 8, the Speed Up pin, allows a capacitor to be connected to ground to facilitate reference settling. This does not speed up the conversion time, but it does reduce odd order harmonic distortion. As with the decoupling capacitor on pin 5, this may also contribute to noise; if harmonic content is most important in an application, this capacitor (.µf - µf) should be connected. In all other cases, it is best to leave the capacitor out of the circuit. Input Scaling The analog input should be scaled as close to the maximum input signal range as possible in order to utilize the maximum signal resolution of the A/D converter. The DAC inside the has a ±ma range, and the nominal ±V input is scaled by a.5kω resistor. In order to scale to other ranges, see Table I for recommended scaling resistor values, connected as shown in Figure 4. INPUT ANGE ±V 8.kΩ ±5V.kΩ NOTE: values shown assume use of k trim pot to adjust for scale accuracy. TABLE I. Input Scaling esistor Values. µf.µf 4 V DD µf.µf *kω *Use to trim for exact scaling. Use trim pot with temperature coefficient of ppm/ C or better. FIGUE 4. Input Scaling Circuit. µf VCC.µF FIGUE. ecommended Power Supply Decoupling. eference Decoupling and Speed Up In order to assure the lowest noise operation of the, the reference may be bypassed by three different capacitors. Pin 5 is a decoupling point for the reference to V CC. The INPUT IMPEDANCE The input signal to the should come from a low impedance source, such as the output of an op amp, to avoid any errors due to the dynamic input impedance that a successive-approximation converter presents to the outside world because of the changing currents in this circuit during conversion as the converter steps through its approximations. If the driving circuit output impedance is not low, a buffer amplifier should be added between the input signal and the direct input to the as shown in Figure 5. 4

15 V IN SOUT Clk Out D Clk OPA67 FIGUE 5. Buffer Amplifier for Input. P 5V 5V D S 5V D S TMSC5/C FS MSB Adjustment Differential Linearity errors at bipolar zero and THD are guaranteed to meet data sheet specifications without any external adjustment. However, a provision has been made for an optional adjustment of the MSB linearity point which makes it possible to eliminate DLE error at BPZ. This is important when the signal level is very low, because zero crossing noise (DLE at BPZ) becomes very significant when compared to the small codes changes occurring in the portion of the converter. The is laser trimmed for best performance at the factory without the MSB adjust circuitry installed; if better performance can be obtained it would be by the addition of the MSB adjust circuitry shown in Figure 6. The best method of adjusting the MSB is by using a real time FFT routine to monitor the levels of odd order harmonics when a sine-wave is being digitized by the. Adjusting the potentiometer in Figure 6 will allow the user to reduce the magnitude of odd-order harmonics. An alternate method is to reconstruct the data out of the through a DAC, and measure THDN on a conventional distortion analyzer. Adjust the potentiometer for minimum THDN. SOUT Clk Out P 5V Clk 5V D S Clk Clk 5V 5V D S Clk 5V XD XC DSP56 FS NOTE: FSM = Bit Mode FIGUE 8. Interface to Motorola DSP56 DSP Processor. NOTE: FSM = FIGUE 7. Interface to TMSC5/C DSP Processors. V CC kω kω V POT 4 SOUT Clk Out Data In ICK MSB ADJ MΩ P 5V DSPC FIGUE 6. MSB Adjust Circuit. APPLICATIONS INFOMATION A typical digitization circuit, used on the demonstration board available for the, is shown in Figure. The connections and part values shown in this circuit have been optimized for the best THDN performance at a khz sample rate. The may be interfaced to many popular digital signal processors, such as the TMS, DSP56, and the DSP. Suggested interface circuits for these processors are shown in Figures 7-9. D S Clk D S Clk 5V ILD NOTE: Set for 6-Bit external ILD, ICK MSB bit first FIGUE 9. Interface to AT&T DSP6 & DSPC Processors. 5

16 Analog Input J kω 5 5 C C C.µF.µF.µF kω 4 C IN448 IN448 SHC5 U µF 7.kΩ JP7 4 JP8 5 V k V kω Ω 9 C pf kω JP JP 5 5 C 7 C 8 V 5.µF 5.µF 4 4.µF ANALOG In Out POT MSB Adj Serial Out 5 7 EF Out MSB 7 TP 8 5 Speed Up EF DCPL 6 Comparator Common EXT CLK S OUT Latch S OUT 9 6 TP TP6 Short Cycle 8 8 BOB/BTC SEL C C 7 9 S OUT 6 TP4 5 Convert Command J INT External HCT4 4 U4 CLK.µF 5 4.µF.µF 7 5 CLK 8 6 PCM56 DATA 5 C 6 7 U 74HCT LE U5 5 V OUT F SJ I OUT Trim MSB ADJ.µF C 7.µF J econstructed Output U4 U4 U4 U4 U4 HCT4 HCT4 HCT4 HCT4 HCT4 S OUT SCK SE CK.µF U6 74HC U7 74HC GND 5 GND DV B6 B5 B4 B B B B B9 B8 B7 B6 B5 B4 B B 5 B 5 GND 4 pf 6.5kΩ Ω 7.kΩ 9.kΩ 4 kω k C U8 5 U8 7 C HCT5 HCT5 4 pf 5 U8 5 4 HCT5.µF 4 C pf JP C.µF JP C C 5 7 C 8 C 9 C 5 C C 5 A B C D E F G H H 4 8 SCK SE.µF 6 A B C D E F G H P P 5.k 7 Ω.k.k 6 Ω 5 Ω FIGUE. Schematic for Demonstration Board (DEM). CK 6

17 PACKAGE DAWING 7