Influences of Switching Jitter on the Operational Performances of Linear Transformer Drivers-Based Drivers

Transcription

1 Influences of Switching Jitter on the Operational Performances of Linear Transformer Drivers-Based Drivers LIU Peng ( ) 1, SUN Fengju ( ) 2, WEI Hao ( ) 2, WANG Zhiguo ( ) 2, YIN Jiahui ( ) 2, QIU Aici ( ) 1 1 School of Electrical Engineering, Xi an Jiaotong University, Xi an , China 2 Northwest Institute of Nuclear Technology, Xi an , China Abstract A whole circuit model of a linear transformer drivers (LTD) module composed of 60 cavities in series was developed in the software PSPICE to study the influence of switching jitter on the operational performances of LTDs. In the model, each brick in each cavity is capable of operating with jitter in its switch. Additionally, the manner of triggering cables entering into cavities was considered. The performances of the LTD module operating with three typical cavity-triggering sequences were simulated and the simulation results indicate that switching jitter affects slightly the peak and starting time of the output current pulse. However, the enhancement in switching jitter would significantly lengthen the rise time of the output current pulse. Without considering other factors, a jitter lower than 10 ns may be necessary for the switches in the LTD module to provide output current parameters with an acceptable deviation. Keywords: linear transformer drivers (LTDs), circuit model, pulsed power, transmission line, jitter, trigger delay PACS: p, Lq, Bg DOI: / /14/4/15 1 Introduction Predominant technical advantages make linear transformer drivers (LTDs) a candidate to build up future high current z-pinch drivers and high voltage radiographic drivers [1 22]. Several conceptual designs were proposed [1,10,16,17]. Although so far much work has been carried out, there are still several important issues to be addressed. One is related to the synchronization of the array of gas switches, since thousands of switches may be necessary to build an operationally realistic LTD. Switching jitter, defined as the deviation of the breakdown delay, is an inherent property for gas spark switches. In recent years, much effort has been made to improve the operating performance of gas spark switches, especially to improve the operational reliability and reduce the jitter [18 22]. In general, low jitter can be obtained by increasing the ratio of the charging voltage to the self-break voltage, or by improving trigger parameters. However, the increase in the ratio of the charging voltage to the self-break voltage encounters the challenge in the high reliability of gas switches [19]. In addition, excessive requirements for trigger pulse parameters may complicate the trigger system of LTDs. The experimental data obtained from a LTD prototype consisting of 7 small cavities indicated that the output current peak fell in a range of 5%, and the current rise time varied in a range of 6% [9]. However, the jitter of their switches did not appear. LECKBEE J J et al. completed the conceptual design of a LTD for flash-radiography, which consists of 48 small cavities connected in series, with 12 fast discharging bricks and 6 peaking capacitors contained for each [16]. Simulation results indicated that the jitter of 10 ns caused a decrease of about 4% in the output voltage peak, and an increase of 13% in the rise time of 0.1 to 0.9. However, the principle about the effect of switching jitter on the operating characteristics of LTDs is not clear. Hence, the influence of switching jitter is worthy of further investigation. STYGAR et al. proposed a 1000 TW accelerator, driven by 210 LTD modules in parallel [1], where, each module consists of 60 cavities of 1 MA. To search for appropriate principles for selecting the operational points and trigger parameters for the LTD switches, in this paper the effect of switching jitter on the operating characteristics of an LTD module of the 1000 TW accelerator mentioned above is studied. The circuit model of the LTD module was built up in the context of the software PSPICE, where each brick in each cavity could operate with its switching jitter. 2 Modeling the whole circuit of the LTD module 2.1 Equivalent circuit model The circuit model based on transmission lines has been validated and utilized to simulate the performance supported partly by National Natural Science Foundation of China (Nos , ), and partly by the State Key Laboratory of Electrical Insulation and Power Equipment of Xi an Jiaotong University of China (EIPE 09207)

2 of different LTDs [1,2,7,16,17]. However, it was found that such models have encountered unconquerable challenges in dealing with the behavior of each brick in each cavity. Another circuit model for the LTD module was built up in PSPICE, where the internal transmission line segment driven by a single cavity is replaced by several Γ -type circuit elements. Each Γ -type circuit element consists of a series inductance and a shunt capacitance. The electric scheme of a single cavity is shown in Fig. 1, with R C the resistance describing the magnetic core loss and L EX the exciting inductance of the magnetic core. L S, C S, and R S are the equivalent overall inductance, capacitance, and resistance for each brick. The turn-on resistance of a switch is described by R G. To give the main circuit a potential reference, R I with a high-enough value is appended. The quantities L N and C N are the series inductance and shunt capacitance of a Γ -type circuit element. Their values can be estimated as follows, L N = Z N τ C /m, (1) C N = τ C /(mz N ), (2) where Z N is the characteristic impedance of the internal transmission line segment driven by the N th cavity, m is the number of Γ -type circuit elements connected in series to replace the internal transmission line segment, and τ C is the time for an electromagnetic pulse propagating in the axial length of a single cavity. Here, the internal water-insulated transmission line is adopted in the LTD module. According to the dimension of the present cavity of 1 MA, the length of a single cavity is 0.22 m, and the estimation of τ C is 6.6 ns [1,4]. The empirical formula proposed by VIZIR and KIM is used to estimate the value of R C R C = k ρs δ 2 l, (3) where ρ is the specific resistivity of the electric steel and Ω m in our case; S is the total cross section of the magnetic cores in a single cavity, 56 cm 2 ; l is the length of the core, 6.28 m; and δ is the thickness of a single tape to fabricate the cores, 50 µm. The value of k is found to be 8 [23,24]. According to Eq. (3), R C is estimated approximately to be 1.5 Ω. Given the relative permeability of electric steel to be 1000, the estimate of L EX is about 2 µh. Other parameters of a discharging brick are listed in Table 1. The internal transmission line is configured with a rough matched state as follows, Z N = NZ 1, (4) where Z 1 is the characteristic impedance of the internal transmission line segment driven by the first cavity, which is equal to the internal driving impedance of a cavity, and is 0.1 Ω in the present case. A resistive load driven by the LTD module is matched to the internal transmission line segment driven by the final cavity downstream. To validate the circuit model proposed in this paper, the output current of the LTD module was simulated by using two kinds of circuit models when the switching jitter is not considered. One kind is the circuit model developed from Γ -type circuit elements, while another is developed from transmission lines. In the latter model, the 40 bricks in a cavity are simplified and treated as an equivalent circuit. In the simulation, the circuit models with different numbers of Γ -type circuit elements to replace the transmission line segment driven by a cavity were utilized. Simulation results indicate that the circuit model with 8 Γ -type circuit elements in a cavity is competent enough to generate output current pulses in a good agreement with those obtained from the model with transmission lines. The current shape generated by the LTD module operating with three cavity-triggering sequences is given in Fig. 2. The baselines of the current shape generated by the sequences B and C were shifted to 200 ka. The three sequences are described as follows, t N+1 t N = τ C, (5) t N+1 t N = 0, (6) t N+1 t N = τ C, (7) where t N is the time to close the switches in the N th cavity. In this paper, the sequences described by Eqs. (5) (7) are labeled as A, B and C, respectively. Table 1. Parameters of one discharging brick Quality Symbol Value Series resistance R S 0.4 Ω Series inductance L S 320 nh Storage capacitance C S 20 nf Closed resistance of R G 0.2 Ω the gas switch Fig.1 Circuit model of a single cavity with Γ -type circuit elements 348

3 LIU Peng et al.: Influences of Switching Jitter on the Operational Performances of LTDs-Based Drivers Fig.2 Shape of output current generated by two different circuit models Fig.3 cavity Layout of the trigger cables and the switches in a 2.2 Generation of the breakdown delay of switches A special circuit was designed to generate automatically the closing time for switches with their jitter considered. Such a circuit is shown in the right of Fig. 1. The capacitor C 1 is charged by the step current source I 1 with a constant current of I S. Before the simulation, the capacitance tolerance of C 1 was configured according to the normal distribution. It is easy to calculate the following two temporal parameters, T OFF = T D + V OFF C 1 /I S, (8) T ON = T D + V ON C 1 /I S, (9) where V OFF and V ON are two inherent parameters for the voltage-controlled switch S 1, and T D is the starting delay of the current I S. T OFF is related to the time to initiate the transit process from off-state to on-state, and T ON is the time when this process is completed. If the voltage V OFF and the current I S were both kept constant, T OFF would depend linearly upon the capacitance of C 1. Given the capacitance and tolerance of C 1, the jitter of the switch S 1 would obey a normal distribution function related to the capacitance tolerance of C 1. The transit time of the switch, which is the difference between T OFF and T ON, can be expressed as T TRAN = (V ON V OFF )C 1 /I S. (10) If V ON is only a little higher than V OFF, the influence of the tolerance of C 1 on the variation of T TRAN would be small enough to be ignored. The delay of the switch S 1 is the sum of the charging time of capacitor C 1 and the starting delay of current I S. In this paper, current I S and capacitance C 1 are assumed to be 1 A and 100 nf, respectively. The values of V OFF and V ON are equal to 1.0 V and 1.01 V, respectively. As a result, the central value of the delay caused by the charging of C 1 is a constant of 100 ns, and the estimation of T TRAN is 1 ns. After such a conversion, the jitter of all switches could be easily adjusted by altering the tolerance of capacitance C 1 in each brick. The cavitytriggering sequence could be configured by altering the starting delay of the step current source I 1. 3 Entering manner of trigger cables into cavities Due to its influence on the time of trigger pulses arriving at the switches, the layout of several trigger cables entering the same cavity should be considered. A sketch of the half layout of trigger cables and switches in the same cavity is shown in Fig. 3. To trigger the 40 switches in a single cavity of 1 MA, a metal wire loop is utilized. Four cables from one trigger generator are connected to this metal wire loop [4]. According to the arrival time of their trigger pulses, the 40 switches could be divided into three groups, as marked with numerals in Fig. 3. The perimeter of the metal wire loop for the trigger is approximately 8 m, and the delay taken by an electromagnetic wave to propagate through this loop in oil is about 40 ns. Taking the time for the trigger pulse to arrive at the metal loop as the baseline, the triggering intervals of the switches marked 1 to 3 are 0 ns, 2 ns and 4 ns, respectively. In the following simulations, the expected time to close a specific switch is the sum of its triggering interval and the time for the trigger pulse to arrive at its cavity. A cavity-triggering sequence is a series of time for different trigger pulses to arrive at corresponding cavities in the LTD module. 4 Results and discussion The jitters of gas switches developed for LTDs are below 10 ns [19 22]. Considering the inherent jitter of the trigger system, the overall closing delay jitter for a switch would be a little higher. As a result, the range of the switching jitter studied in this paper was set from 0 ns to 30 ns. The operational performances of the LTD module were simulated and analyzed on the condition that the three triggering sequences described in section 2 are adopted. 4.1 Peak of the output current pulses The dependence of output current peak on the switching jitter, when the LTD module operates with different cavity-triggering sequences, is shown in Fig. 4. These current peak were normalized by using that 349

4 generated by their corresponding cavity-triggering sequences without consideration of switching jitter. The current peaks generated by the triggering sequences A, B and C are 984 ka, 531 ka and 327 ka, respectively. The error bars in Fig. 4 represent the standard deviation (1 δ) of ten simulation data for each operational point, indicated by the right y-coordinate. Fig.5 Rise time of output current as a function of the switching jitter 4.3 Starting time of the output current pulse Fig.4 Peak of output current as a function of the switching jitter As is shown in Fig. 4, the current peak decreases with the increase in switching jitter, which is in accordance with known experience [16]. However, the normalized current peak generated by the triggering sequence A is the most sensitive to switching jitter. The triggering sequence C generated the largest absolute deviation in the current peak. In summary, an overall switching jitter of 15 ns may be allowable, which would generate output currents with their peaks decreased by less than 2% as LTD works in all three cavity-triggering sequences. 4.2 Rise time of the output current pulse The normalized rise time of the output current pulses generated by the three cavity-triggering sequences is shown in Fig. 5. The rise times generated by the three triggering sequences without consideration of switching jitter are 55.8 ns, ns and ns, respectively. The increase in switching jitter is inevitable to lengthen the rise time, which agrees with the known conclusion [16]. However, the relation between the rise time and the switching jitter is approximately a quadratic function rather than a linear function, specifically for those generated by the triggering sequence A. The jitter exhibits a more important effect on the deviations other than the averages of the output current rise times generated by the triggering sequences B and C. Hence, the switching jitter should be severely limited based on the condition that the rise time of the output pulse affected critically the performances of the loads. The switching jitter of 10 ns would increase the output current rise time by 8.7%, from 55.8 ns to 60.7 ns with a standard deviation of 0.5 ns, when the LTD module operates with triggering sequence A. The variation in the starting time of the output current shapes caused by the switching jitter is studied in this sub-section. Here, the starting time is defined as the time interval from an assumed time in the simulation to the time when the current rises to 10% of its peak. The dependence of the starting time upon the jitter is shown in Fig. 6. The starting times of the output current pulses generated by the three triggering sequences without consideration of jitter were assumed to be 100 ns. For the results related to these three triggering sequences, the dependences of the starting time upon the switching jitter are approximately in agreement with each other. With the effect of the switching jitter, the starting time, at which the LTD module generates the output current pulse, would be earlier than the expected time. However, the standard deviation of the starting time is worthy of further investigation because it serves as the output jitter of the power pulse generated by each module when several LTD modules operate in parallel. As shown in Fig. 6, the standard deviation of the starting time is only 0.6 ns when LTD operates with triggering sequence A in response to a jitter of 15 ns, whereas such a jitter would generate the largest deviation of about 3 ns when the LTD module operates with the triggering sequence C. Such a low Fig.6 Dependence of the starting time of output current upon the switching jitter 350

5 LIU Peng et al.: Influences of Switching Jitter on the Operational Performances of LTDs-Based Drivers deviation in the starting time may be negligible in practical applications of the LTD modules operating in parallel. 4.4 Discussion In the above simulations, all switches were assumed to have an identical breakdown delay, which would not be altered by any other factors. This may be different from the actual operational characteristics of gas switches. The voltages across the switches in the same cavity when LTD operates with a jitter of 10 ns are shown in Fig. 7. Under the influence of the output currents generated by the switches closed earlier, the average electric field across the switches closed later decreased dynamically. According to the empirical formula proposed by MARTIN [25], the breakdown delay of a gas switch is highly dependent on its average electric field. As a result, the delays of the switches closed later are likely to be prolonged. Hence, the condition of the LTD switches operated in parallel is worthy of further experimental investigation. Fig.7 Distribution of the switching time of the 40 switches in the same cavity 5 Conclusion A novel circuit model capable of dealing with one LTD module composed of 60 cavities of 1 MA was established and validated by using the PSPICE software. In the circuit model, 40 discharging bricks located in each cavity are able to independently operate with consideration of their switching jitter. For three typical cavity-triggering sequences, the operational characteristics of the LTD module were simulated and analyzed with the jitter varying from 0 ns to 30 ns. From simulation results, it is concluded that the current rise time is most susceptible to the switching jitter. Operating with the triggering sequence A and a jitter of 10 ns, LTD would generate an output current pulse with its rise time increased by 8.7% and its peak decreased by about 1%. However, the starting time of the output current pulse would have only a standard deviation of 2 ns or less when the triggering sequence C and a jitter of 10 ns are considered. Without considering other factors, a jitter below 10 ns may be necessary for the switches in the LTD module to generate the output current parameters with an acceptable deviation. References 1 Stygar W A, Cuneo M E, Headley D I, et al. 2007, Physical Review Special Topics- Accelerator and Beams, 10: Stygar W A, Fowler W E, LeChien K R, et al. Beams, 12: Mazarakis M G, Fowler W E, Kim A A, et al. Beams, 12: Kim A A, Mazarakis M G, Sinebryukhov V A, et al. Beams, 12: Kovalchuk B M, Kim A A, Kumpjak E V, et al. 2001, Ten-stage LTD for E-beam diode. Presented at the Proc. of the 13th IEEE Int. Pulsed Power Conf. (Las Vegas, NV, USA, 2001) IEEE, New York. p Kim A A, Bastrikov A N, Volkov S N, et al. 2003, 1-MV ultra-fast LTD generator. Presented at the Proc. of the 14th IEEE Int. Pulsed Power Conf. Dallas, Texas, USA. IEEE, New York. p Leckbee J, Maenchen J, Portillo S, et al. 2005, Circuit simulation of a 1-MV LTD. in the Proc. of the 15th IEEE Int. Pulsed Power Conf. Monterey, California, USA. IEEE, New York. p Rogowski S T, Fowler W E, Mazarakis M, et al. 2005, Operation and performance of the first high current LTD at Sandia National Laboratories. Presented at the Proc. of the 15th IEEE Int. Pulsed Power Conf. Monterey, California, USA. IEEE, New York. p Leckbee J, Maenchen J, Portillo S, el al. 2005, Reliability assessment of a 1-MV LTD. Presented at the Proc. of the 15th IEEE Int. Pulsed Power Conf. Monterey, California, USA. IEEE, New York. p Mazarakis M G, Fowler W E, Long F W, el al. 2005, High current fast 100-ns LTD driver development in Sandia National Laboratory. Presented at the Proc. of the 15th IEEE Int. Pulsed Power Conf. Monterey, California, USA. IEEE, New York. p Mazarakis M G, Fowler W E, McDaniel D H, et al. 2007, High current linear transformer driver (LTD) experiments. Presented at the Proc. of the 16th IEEE Pulsed Power Conf. Albuquerque, NM, USA. IEEE, New York. p Kim A A, Sinebryukhov V A, Kovalchuk B M, et al. 2007, Design and first tests of five 10-GW fast LTD cavities driving an E-beam load. Presented at the Proc. of the 16th IEEE Int. Pulsed Power Conf. Albuquerque, NM, USA. IEEE, New York. p Kim A A, Sinebryukhov V A, Kovalchuk B M, et al. 2007, Super fast 75 ns LTD stage. Presented at the Proc. of the 16th IEEE Int. Pulsed Power Conf. Albuquerque, NM, USA. IEEE New York. p LeChien K R, Mazarakis M G, Fowler W E, et al. 2007, A 1-MV, 1-MA, 0.1 Hz linear transformer driver utilizing an internal water transmission line. Presented 351

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