ALTIUM LIVE 2018: PRACTICAL HIGH-SPEED DESIGN CONSTRAINTS. Randy Clemmons CID+ San Diego PCB October 5, 2018

Transcription

1 ALTIUM LIVE 2018: PRACTICAL HIGH-SPEED DESIGN CONSTRAINTS Randy Clemmons CID+ San Diego PCB October 5, 2018

2 Technology Boom Cycle Virtual Reality Artificial Intelligence Internet of Things Drones Driverless Cars Robotics Hyperloop Big Data Medical Devices What do they have in common? Highspeed data processing?

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4 Practical High Speed Design Constraints Transition Propagation Delay (Tpd) and Velocity of electromagnetic fields in circuit boards. Should high-speed designers consider the propagation delay of signals?

5 Velocity of electromagnetic waves in a typical circuit boards is approximately 60% the speed of light. Electromagnetic waves travel through dielectric materials guided by copper features in the signal and return paths.

6 Propagation Delay is the Reciprocal of Velocity Where: Er = Effective Er (Dk) = Keff c = Speed of light (300,000,00 m/s) 186,000miles/hour Vp = Velocity Tpd = Transistion Propagation Delay

7 Source:

8 For FR4 materials the dielectric constant known as Er or Dk can vary greatly from ~3.8 to 4.7. And the Dk number in the datasheet for the material is the neat resin number. The neat resin number is the epoxy only Dk, before factoring in the fiberglass woven material

9 370HR Dk ~ 4 (Resin Only) E-Glass Dk ~

10 Fabricators rarely provide the effective dielectric constant.

11 Typical Propagation Delay (Tpd) Signals travel faster on outer layers Tpd expressed in Pico Seconds per inch.

12 Equations for Tpd, Keff, Co, Lo, Zo

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14 Using Saturn PCB Design Toolkit to find Keff and Tpd Effective Dielecric (Keff) = Air + Soldermask + Dielectric

15 Using Saturn PCB Design Toolkit to find Tpd for Stripline Stripline is approximately 20pSec per inch slower than Microstrip Effective Er (Keff) approximately equals Dk in Stripline.

16 Simple Example Design 1GBIT DDR2 SDRAM Top Layer Routing

17 Layer 1 SIG Layer 2 GND

18 Layer 3 SIG Layer 4 VREF

19 Vias NOT included in Length Matching (copper track length) Before xsignals and Net length data which includes vias

20 Vias included in Length Matching (copper track length) After xsignals and Net length data which includes vias

21 Vias included in Length Matching (Flight Time psec/inch) Flight Time Calculated using Tpd per inch

22 Chuy s Trailer Park Calafia (Rosarito) Mexico Winter 1998 Timing is Critical!

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24 Critical trace length for a signal with 1nS Risetime is ~ 1.5 inches Enter Er Eff, Risetime as the Period Set Wavelength Divide to 1/4

25 Critical 50 Ohm path?

26 Path length 486mils

27 Enter dielectric thickness before length matching Length of Vias defined by the Stackup

28 Clean Tracks! (No Net Antennas or Extra bits of Copper

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30 90 Degree Corners Designers have been lead to believe that routes with square corners are a bad thing and they assume all square corners should be eliminated from a design. I have some bad news for the no square corners camp. Every surface mount resistor placed on the board will introduce four sharp 90 degree turns in the signal path. I suggest they figure out how to design their boards without using resistors :)

31 Source: Altium Blog

32 Google for Experts: Ask questions: (like exactly what is piece of cake) Together we all know more than anyone of us. (share your knowledge) Eric Bogatin Rick Hartley Ralph Morrison Douglas Brooks Dr. Howard Johnson Lee Richey Henry Ott Terry Fox Bruce Archambeault Barry Onley Robert Feranec Charles Pfeil Happy Holden

33 Thank You ALTIUM LIVE 2018: PRACTICAL HIGH-SPEED DESIGN CONSTRAINTS Randy Clemmons CID+ San Diego PCB October 5, 2018

34 Happy Wife

35 TXLINE 2003 (Best Free CPW)

36 Net Names on Unused Pins