Analog MMICs for microwave and millimeterwave applications based on HEMTs

Transcription

1 Analog MMICs for microwave and millimeterwave applications based on HEMTs Herbert Zirath Microwave Electronics Laboratory Department of Microtechnology and nanoscience 1 Chalmers University of Technology Göteborg, Sweden

2 Outline -PHEMT MMIC-technology Amplifiers -Feedback amplifiers -low noise millimeterwave high gain amplifiers Frequency Multipliers Oscillators Frequency mixers 2

3 The MMIC-technology The D1PH process: Ft=1 GHz, fmax=18 GHz Top view of 2. 5 μm L w HEMT Mushroom gate,.14 μm gatelength 3

4 6 GHz WLAN D1PH MMICs designed & fabricated for 6 GHz WLAN Amplifiers: M=Measured, S=Simulated 3 stage 6 GHz amplifier Lw=2*15 um M/ f=57-6.8ghz, G=17dB, P DC =27mW 3 stage 6 GHz amplifier Lw=4*15 um M/ f=54.3-6ghz, G=17.6dB Pout=15mW P DC =6mW 1 stage 6 GHz amplifier Lw=4*25 um M/ f=35-65.ghz, G>6dB, Pout=4mW 3 stage 6 GHz amplifier Lw=8*4 um M/ f=4-65.ghz, G>14dB, Pout=2mW 2-18 GHz feedback-amplifier, 2-stage M/G=22 db, NF=2.7 db, P DC =1mW 1-2 GHz feedback-amplifier, 1-stage M/G=12 db, NF=2-3 db. Pout=19dBm 1-1 GHz feedback-amplifier, 1-stage M/G=14 db, NF=2-3 db. Pout=21dBm 2-27 GHz feedback-amplifier, 1-stage M/G=9-11 db, NF=2-3 db. Pout=16dBm 1-8 GHz VGA M/G=12 db Gain control=12 db Frequency multipliers: Active GHz doubler+doubler ( ) M/G=-4 db@dbm, P DC =27 mw Active GHz quadrupler (28-34) M/G=-13dB@dBm, P DC =3 mw Resistive doubler 24 to 31 GHz M/G=-1 db@5dbm, P DC = mw Active doubler 25 to 3 GHz (CF) M/G=2 db@5dbm, P DC =275 mw Active doubler 27 GHz (HZ) M/G=4dB@dBm, P DC =66 mw Active doubler GHz (HZ)ED2AH M/G=4.7 db@dbm, P DC =6 mw Active tripler 8-24 GHz D1PH Balanced doublers D1PH 4

5 Mixers: 5-65 GHz single resistive HEMT-mixer P DC = 3-6 GHz balanced wideband resistive HEMT-mixer PLO=9dBm, P DC = 15-3 GHz balanced wideband resistive HEMT-mixer PLO=1dBm, P DC = GHz image reject resistive HEMT-mixer PLO=1dBm, P DC = Oscillators: VCO 7.5 GHz VCO GHz VCO 29-3 GHz VCO GHz SiGe HBT balanced Colpitt Balanced Colpitt oscillators Negative gm-oscillators Pout=6-7dBm, P DC =16 mw Pout=8 dbm, P DC =16 mw Pout=11 dbm, P DC =16 mw Pout=-1 dbm, P DC =16 mw L at 5 GHz, Pout -5dBm, P DC =5 mw 7-7.5, GHz GHz Frequency dividers: Regenerative freq div 14 to 7 ( ) GHz Regenerative freq div 28 to 14 ( ) GHz Pin=5dBm, Put=5dBm, P DC =1mW Pin=5dBm, P DC = 1mW 5

6 Device characteristics I-V D1PH size: 2. 5 μm drain voltage (V) gate voltage (V) I dsmax >7mA/mm g mmax >7mS/mm 6

7 Typical bias points for different circuits: :Frequency multiplier :Low noise amplifier :Power amplifier :switch, resistive mixer drain voltage (V) gate voltage (V) 7

8 Amplifiers: A Low Noise 2-2 GHz Feedback MMIC-Amplifier 1. Introduction It is well known that resistive feedback can simultaneously give flat gain and good input and output match. The relation between transconductance g m, feedback resistance R f, and characteristic impedance Z for the condition that S11=S22= is R = g Z f m 2 R f The gain S 21 of such an amplifier is then S 21 = Z R f Z Ex: gm=1 ms Z=5->Rf=25 S21=-4 V in For a high gain, g m should be high! RFIC symposium, Boston 2 8

9 Circuit diagram of the amplifier Device width=2 μm 1p 4p 1.5n 1p 4p 4p 25 4n 25 4n 2 um 4p 2 um 4p 4p 5 4p 5 9

10 Photo of the feedback amplifier chip size 2*1.5 mm, effective area 1mm 2 1

11 The noise parameters of different HEMT devices were measured and the results were fitted to a 2-temperature noise model which was used in the simulation of the amplifier Data was fitted to T D, K T D = T D cosh J D J 1 J Open symbols Vd=2V solid symbols Vd=1V circles= 1 μm triangles=2 μm J D, ma/mm 11

12 Measured gain and noise figure of the amplifier F min, Gain, db 1 1 Bias: Vd1=Vd2=1.5V Vg1=Vg2=V Frequency, GHz 12

13 Output power versus input power at 1 GHz versus drain bias Pout [dbm] measured Vdd=1.5 V Measured Vdd=2 V measured Vdd=3 V measured Vdd=4 V simulated Vdd=1,5 V simulated Vdd=2 V simulated Vdd=3 V simulated Vdd=4 V Pinp [dbm] 13

14 1 db compression point versus drain bias at 1 GHz dB CP [dbm] Vdd [V] 14

15 Conclusions A 2-2 GHz PHEMT feedback amplifier was designed, analyzed (noise, S-parameters, output power), fabricated and characterized The amplifier show excellent results: -Noise figure below 3dB -Gain of 11dB per stage i e 22 db -Output power of 1 mw (max) -effective circuit area only 1mm 2 -DC-power consumption 125mW (7-18 mw) -Resistive Feedback in addition stabilizes the transistor 15

16 3-stage wideband amplifier with resistive feedback WIN mhemt MP-15 process 16

17 Gain >2 db (5.7 to 48 GHz) S11 < -5 db and S22 < -1 db Measurement on 9 MMICs d B (S (1,1 )) db(kf4_no2_vg4_vd15_id5..s(1,1)) db(kf4_no3_vg4_vd15_id5..s(1,1)) db(kf4_no4_vg4_vd15_id4..s(1,1)) db(kf4_no5_vg4_vd15_id4..s(1,1)) db(kf4_no6_vg4_vd15_id5..s(1,1)) db(kf4_no7_vg4_vd15_id5..s(1,1)) db(kf4_no8_vg4_vd15_id7..s(1,1)) db(kf4_no9 _vg4_vd15_ id7..s(1,1)) freq, GHz d B (S (2,1 )) db(kf4_no2_vg4_vd15_id5..s(2,1)) db(kf4_no3_vg4_vd15_id5..s(2,1)) db(kf4_no4_vg4_vd15_id4..s(2,1)) db(kf4_no5_vg4_vd15_id4..s(2,1)) db(kf4_no6_vg4_vd15_id5..s(2,1)) db(kf4_no7_vg4_vd15_id5..s(2,1)) db(kf4_no8_vg4_vd15_id7..s(2,1)) db(kf4_no9 _vg4_vd15_ id 7..S(2,1)) freq, GHz freq, GHz db (S (1,2)) db(kf4_no2_vg4_vd15_id5..s(1,2)) db(kf4_no3_vg4_vd15_id5..s(1,2)) db(kf4_no4_vg4_vd15_id4..s(1,2)) db(kf4_no5_vg4_vd15_id4..s(1,2)) db(kf4_no6_vg4_vd15_id5..s(1,2)) db(kf4_no7_vg4_vd15_id5..s(1,2)) db(kf4_no8_vg4_vd15_id7..s(1,2)) db(kf4_no9 _vg4_vd15_ id7..s(1,2)) db (S (2,2)) db(kf4_no2_vg4_vd15_id5..s(2,2)) db(kf4_no3_vg4_vd15_id5..s(2,2)) db(kf4_no4_vg4_vd15_id4..s(2,2)) db(kf4_no5_vg4_vd15_id4..s(2,2)) db(kf4_no6_vg4_vd15_id5..s(2,2)) db(kf4_no7_vg4_vd15_id5..s(2,2)) db(kf4_no8_vg4_vd15_id7..s(2,2)) db(kf4_no9 _vg4_vd15_ id7..s(2,2)) freq, GHz 17

18 Noise figure NF min = 4 db = 5 db 18

19 SG_FBA_1 - Feedback amplifier, 4 stage, 2 3μm (IAF device layout), 2..9 mm 2 Process: IAF mhemt 1nm gatelength 19

20 Simulation results 4 Forward Transmission, db 3 2 db(s(4,3)) db(s(2,1)) Blue = IAF meas. Red = CTH SS-model Var Eqn VAR VAR4 Lgw= freq, GHz Gain (blue = IAF meas., red = CTH SS-model) C C36 C=Cpgd ff C C32 C=Cgd ff R R29 R=Rj Ohm - Full EM simulation of the FBA in Momentum - Data from IAF measurements and CTH SSmodel used in simualtions Port P1 Num=1 L L13 L=Lg ph R= C C3 C=3 ff C R C R C29 R3 C33 R R26 C=Cgs f F R=Rds Ohm C=Cds ff R28 R=Rg Ohm R=Rd Ohm Var VAR Eqn C R VCCS VAR1 C31 R25 SRC5 Lg=11 C=3 ff R=Ri G=gm ms Rg=2.6*SC T=1 Cpgd=2 Cgs=87*SC Var Var VAR VAR Ri=2.2/SC Eqn Eqn R VAR2 VAR3 Rs=1.5/SC R27 SC=Lgw/5 C_Ids=23*SC Ls=1.3 R=Rs Ohm gm=175.6*sc Rds=7/SC Cds=*SC L Cgd=2*SC L14 Rj=/SC L=Ls ph Rd=1.7/SC R= Ld=11 L L15 L=Ld ph C C37 R= C=C_Ids ff C C34 C=2.5 f F Port P2 Num=2 C C35 C=2.5 ff 2 Port P3 Num=3 CTH SS-model

21 Noise measurements with gain Gain/NF (db) RF frequency (GHz) Noise (db) Gain (db) 21

22 Q-band (33-5) GHz medium power amplifiers, optimized interstage matching topology for increased bandwidth 3-dB bandwidth typ 5% 2dB Gain Output power >5 mw 3 db noise figure Shorted stubs in drain bias line <λ/4 Output power 6x25 and 8x25, and 8x4 18 Poutcor.dBm (Vg1=-.2V; Vd1=3.2V;Vg23=-.3V;Vd2,3=4.V) Poutcor.dBm (Vg1=.v; Data Vd1=3.5V;Vg23=-.2V;Vd2,3=4.5V) Measured gain db(s(2,1)) Pin, dbm 22-6 freq, GHz

23 Wideband amplifier in WIN PP-15 process Each amplifier stage has a gate-drain parallel feedback stabilization network consisting of an RC network with R=166 Ω and C=21 ff. Each transistor has two gate fingers with a unit width of 5 μm. The drain DC supply resistance is 1 Ω. The simulated small signal gain (S21) is 17 db ±1 db, between 45 and 7 GHz, for VD=3 V and VG=-,2 V. Simulated noise figure is 4,9 db. 3x2 mm 23

24 Measured results, S-parameters Red curve is with extra passivation (BCB) S11 (db) freq, GHz S21 (db) freq, GHz -2-5 S12 (db) -4-6 S22 (db) freq, GHz freq, GHz 24

25 HZMFB1N 1st stage reflection match stage 2-3 resistive FB NF minbp2 = 3 db 25

26 HZMFB2N 1st stage reflection match stage 2-3 resistive FB 24 Gain (db) Noise figure (db) HZMFB2N Vg1=-.3V, Vd1=1.9V, Vg2,3=-.2V, Vd2,3=2.V, Id=84mA NF min = 4.5 db Frequency (GHz) 26

27 HZMFB2N2 Gain (db) Noise figure (db) 1st stage reflection match 2-4 stage resistive FB 3 25 HZMFB2N2 Vg1=-.4V, Vd1=1.8V, Vg2,3,4=-.2V, Vd2,3,4=2.V, Id=92mA Frequency (GHz) NF min = 4 db 27

28 Motivation Frequency multipliers Low-cost LO-chain for 6-GHz WLAN Frequency Multipliers Baseband signal LO X 4 X 2 RX / TX MMIC2 Chalmers University of Technology High conversion efficiency Doubler + Doubler Wideband operation, Small chip area Active input matching circuit + Quadrupler Low power consumption Single-ended Doubler with Buffer Amplifier 28

29 How can we get a frequency multiplication? We investigate an MHEMT, Lw=9 um DC-characteristic id versus vg at Vdd=2V vg I_Probe ig R R1 R=5 Ohm V_DC SRC1 Vdc=Vgg V G S1 D S2 fd1mhonl2 FP2 Wfg=15 um Nfg=6 Vtpcm=VTstat KIdss=KIdstat Lgate=Lgstat Vbrk=VbrkON TINt= I_Probe id Var Eqn V_DC SRC2 Vdc=Vdd V VAR VAR1 pin= Vdd=2 Vgg=-1 infreq=1 DC DC DC1 SweepVar="Vgg" Start=-1 Stop=1 Step=.5 id.i, ma ig.i, ua Vgg Pinch-off saturation

30 Bias for even harmonics, close to pinchoff.7 V Pin=dBm, substantial 2 nd harmonic! Sine-pulse 4.2 ts(id.i), ma mag(id.i) freq, GHz ts(vg), V idvsvg..id.i, A ts(id.i) time, nsec ts(vg) Vgg 3

31 Bias for even harmonics, close to pinchoff.8 V Pin=4 dbm Half-sine waveform.3 ts(id.i), ma mag(id.i) freq, GHz.1 ts(vg), V time, nsec idvsvg..id.i, A ts(id.i) IEEE MMIC seminar Bergen Vgg H Zirath ts(vg) ts(ig.i)

32 Bias for even harmonics, close to pinchoff.7 V Pin=1 dbm, onset of gate conduction current Rectangular waveform!.4 ts(id.i), ma mag(id.i) freq, GHz.2 ts(vg), V time, nsec idvsvg..id.i, A ts(id.i) ts(vg) Vgg ts(ig.i) 32

33 Bias for odd harmonics, max gm-point not-so-large signal dbm input power Not much of 3 rd harmonic.3 ts(id.i), ma mag(id.i) freq, GHz ts(vg), V. -.5 idvsvg..id.i, A ts(id.i) time, nsec ts(vg) Vgg 33

34 Bias for odd harmonics, max gm-point larger signal: 5 dbm input power.4 ts(id.i), ma mag(id.i) freq, GHz.1 ts(vg), V time, nsec idvsvg..id.i, A ts(id.i) ts(vg) Vgg

35 Bias for odd harmonics, max gm-point even larger signal: 1 dbm input power Clear gate conduction, 4 ma peak current, be careful!.4 ts(id.i), ma mag(id.i) freq, GHz.6 ts(vg), V time, nsec idvsvg..id.i, A ts(id.i) ts(vg) Vgg ts(ig.i)

36 drain-current harmonics, input power sweep:.4 mag(id.i[::,4]) mag(id.i[::,3]) mag(id.i[::,2]) mag(id.i[::,1]) st 2 nd Even harmonic optimum Vgg=-.8V pin 3 rd 4 th mag(id.i[::,4]) mag(id.i[::,3]) mag(id.i[::,2]) mag(id.i[::,1]) st 2 nd 3 rd 4 th Odd harmonic optimum Vgg=-.1V pin 36

37 drain-current harmonics, gate bias sweep: mag(id.i[::,4]) mag(id.i[::,3]) mag(id.i[::,2]) mag(id.i[::,1]) st 2 nd Pin=dBm. 3 rd 4 th mag(id.i[::,4]) mag(id.i[::,3]) mag(id.i[::,2]) mag(id.i[::,1]) Vgg Pin=7dBm Vgg 37

38 Fabrication OMMIC D1PH process phemt Lg =.14 µm f T = 95 GHz f max = 18 GHz g m_max =7 ms/mm Ids max =7 ma/mm Spiral Inductor Q = 29 L = 1 28 GHz Harmonics Power (dbm) Wg = 4 x15 µm 5-Ω termination, f1=5 MHz : Meas. : Sim. -1 -,5 VGS (V) P1f P2f P3f P4f 38

39 A GHz Frequency Multiplier Design Goals Input frequency, f in = 16 GHz High rejection of unwanted harmonics Low power consumption 39

40 Circuit Topology 4

41 Layout Chip size 3 1 mm 2 41

42 Simulated Results Conversion gain db Output power dbm Rejection of unwanted harmonics > 2 db P DC 4 mw 3-dB bandwidth > 3 % 42

43 Measurements On-chip measurements using coplanar probing Rejection of unwanted harmonics > 25 db P DC = 4 mw 3-dB bandwidth 25 % 43

44 Output Power Versus Input Power at f in = 16 GHz 44

45 Rejection of Fundamental 5 dbm Input Power 45

46 32GHz Quadrupler(I) - Schematic Doubler + Doubler High Conversion Efficiency Large-area components (L1, TL1) 2 x 1.5 mm 2 chip Design: Herbert Zirath VG1 VD1 VG2 VD2 -.7 V 2 V -.7 V 2 V IN C1 R1 L1 R2 TL1 T1 1st Doubler C2 Coupled Line OUT 46 R3 L2 TL2 R4 T2 2nd Doubler C3

47 32GHz Quadrupler(I) - Measured Results Pdc = 16 mw (@Pin = dbm) Output power (dbm) P1f P2f P3f P4f Output frequency (GHz) Input (dbm) Pin = +3.3 dbm Fout = 32 GHz Output -3dB Bandwidth Conv.Gain max = -3 db = 4 GHz P4f sat = -2 dbm 47 Output power (dbm) P1f P2f P3f P4f

48 32GHz Quadrupler(II) - Concept Conventional IN IN Zin 1 / gm(i DC ) I DC TL Active Matching Circuit gm(i DC ) i S11 (db) -25 Active matching circuit v Input frequency (GHz) = -1 dbm Conventional

49 32GHz Quadrupler(II) - Schematic Common-gate stage + Quadrupler Active Matching Circuit (MC) Wideband matching Small chip-area 2 x 1.5 mm 2 chip VG1 VD1 VG2 VD2 -.4 V 2 V -.4 V 2 V IN C2 R1 TL1 C1 L1 T1 TL2 Active MC L2 C3 Coupled Line OUT 49 R2 R3 T2 Quadrupler

50 32GHz Quadrupler(II) - Measured Results Pdc = 28 mw (@Pin = dbm) P1f P2f P3f P4f P1f P2f P3f P4f Output Power (dbm) Output frequency (GHz) Pin = +3.3 dbm Output -3dB B.W. = 6 GHz Input (dbm) Fout = 32 GHz Conv.Gain max = -13 db P4f sat = -8 dbm 5 Output power (dbm)

51 56 GHz doubler design Doubler+ buffer amplifier DC-power minimized Each device is 4x25 um Design: Herbert Zirath VG1 VD1 VG2 VD2 IN OUT (a) Acitive frequency doubler with an amplifier stage. 51

52 56GHz Doubler - Measured Results Pdc = 66 mw (@Pin = dbm) Conversion gain (db) Output freqency (GHz) Output power / gain (dbm / db) Pout (dbm) Conversion gain (db) Input (dbm) Pin = +1 dbm Fout = 54 GHz Conv.Gain max = 4 db P2f sat = 7 dbm 52

53 MMIC2 Chalmers University of Technology X8 multiplier on WIN phemt PP-15 process Result x4 breakout: Pout 4-th Pout 3-th Pout 2-nd Pout fund Measured output power of the 4th, 3rd, 2nd harmonic and fundamental frequency versus frequency at dbm input power ,5 6 6,5 7 7,5 8 8,5 53 IEEE 9 MMIC seminar Bergen H Zirath Frequency (GHz)