X-Canceling MISR - New Approach for X-Tolerant Output Compaction
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1 X-Canceling MISR - New Approach for X-Tolerant Output Compaction Nur A. Touba Computer Engineering Research Center Dept. of Electrical and Computer Engineering University of Texas at Austin
2 INTRODUCTION Many Sources of Unknown X s in Output Response Uninitialized Memory Elements Bus Contention Floating Tri-States Multi-cycle Paths Etc. Scan Chains X X Conventional Scan Testing Easy to Handle by Masking on Tester X Major Issue for Test Compression and Logic BIST X s Corrupt Final Signature Prevents Observation of Other Scan Cells
3 INTRODUCTION Many Sources of Unknown X s in Output Response Uninitialized Memory Elements Bus Contention Floating Tri-States Multi-cycle Paths Etc. Conventional Scan Testing Easy to Handle by Masking on Tester Scan Chains X X X M I S R Major Issue for Test Compression and Logic BIST X s Corrupt Final Signature Prevents Observation of Other Scan Cells
4 HANDLING X s Schemes for Handling X s X-Bounding Insert DFT to Prevent X s from Propagating to Output X-Masking Mask X s at Input to Compactor Mask Data Required Scan Chain & X-Tolerant Compactor Scan Chain & Scan Chain & M I S R Mask Data
5 X-COMPACT Combinational Compactor [Mitra & Kim, TCAD 4] Tolerates One X per Scan Slice Detects, 2, or Any Odd Errors Corrupted Outputs Masked on Tester Scan Chain Scan Chain Comb. Compactor Scan Chain
6 CONVOLUTIONAL COMPACTOR Convolutional Compactor [Rajski, et al., TCAD 5] Combinational Compactors Feeding Multiple Shift Registers Tradeoff Compaction Ratio with Number of X s Tolerated in Window of Scan Slices Scan Chain Scan Chain Finite Memory Compactor Scan Chain
7 X-CANCELING MISR X-Tolerant MISR Based on Canceling Out X s in Signature Using Information from Symbolic Simulation For m-bit MISR Each Signature Can Compact Up to k X s with Error Coverage Equivalent to m-k Bit MISR without X s Example 256-Bit MISR Can Tolerate up 24 X s Error Coverage Equivalent to 6 Bit MISR without X s
8 M O 3 X 3 X M2 O 4 O 8 O 2 M 3 O 5 O 9 O 3 M 4 O 6 O X 2 M 5 O 7 O O 5 M 6 X 4 O 2 O 6
9 M = X O 3 X 3 M2 = O2 O 4 O 8 M 3 = O 3 O 5 O 9 M 4 = X 2 O 6 O M 5 = O 5 O 7 O M 6 = O 6 X 4 O 2
10 O 3 M = O 2 X 3 O 4 M 2 = O 3 X O 8 O 5 M 3 = X X 2 O 9 O 6 M 4 = O 5 O O 7 M 5 = O 6 X O X 4 M 6 = X O 2
11 M = X O 3 O 8 O 3 M 2 = X O 2 X 2 X 3 O 9 O 4 M 3 = O 2 O 5 X 3 O O 5 M 4 = X O 6 O O 6 M 5 = X O 2 X 3 O 2 O 7 M 6 = O 2 X 3 X 4
12 M = X O 3 O 8 O 3 O 3 X 3 X M2 = X O2 X2 X3 O9 O4 O 4 O 8 O 2 M 3 = O 2 O 5 X 3 O O 5 O 5 O 9 O 3 M 4 = X O 6 O O 6 O 6 O X 2 M 5 = X O 2 X 3 O 2 O 7 O 7 O O 5 M 6 = O 2 X 3 X 4 X 4 O 2 O 6
13 M = X X 3 X M2 = X X2 X3 M 3 = X 3 M 4 = X 2 4 = 6 Valid Signatures in Fault-Free Circuit X 2 M 5 = X X 3 M 6 = X 3 X 4 X 4
14 ALIASING WHEN COMPACTING X s Probability Error Results in Valid Fault-Free Signature Valid Fault-Free Signatures Total Possible Signatures = 2 2 (Number X s) (MISR Bits) Example 256 Bit MISR Compacting 236 X s Probability of Aliasing = = 2 2 Equivalent to Using a 2-Bit MISR without X s
15 LINEARLY DEPENDENT COMBINATIONS Linearly Dependent Combinations of MISR Bits No Dependence on X s Guaranteed to Exist When More MISR Bits Than X s M M M 2 M 3 M 3 M 3 M 6 M M 3 M 5 M M 4 M 3 = X 3 M 4 = X M 5 = X X 3 M 6 = X 3 X 4 M 2 = X X 2 X 3 M = X Gaussian Elimination
16 M M M 2 M 3 M 3 M 3 M 6 M M 3 M 5 = O 3 O 5 O 8 O O 2 O 3 O 5 O 7 M M 4 M 3 = O 2 O 5 X 3 O O 5 M 5 = X O 2 X 3 O 2 O 7 M = X O 3 O 8 O 3 M M 3 M 5
17 M M M 2 M 3 M 3 M 3 M 6 M M 3 M 5 M M 4 = O 3 O 6 O 8 O O 3 O 6 M = X O 3 O 8 O 3 M M 4 M 4 = X O 6 O O 6
18 ERROR COVERAGE Error Coverage = (Checked Combs) X s Tolerated Per Signature = MISR Bits Checked Combs % 75% 87.5% 93.75% 96.88% 98.44% 99.2% 99.6% 99.8% 99.9% 99.95% 99.97% 99.99% % % %
19 ARCHITECTURE m-bit Scan Chain & Scan Chain Phase Shifter M I S R & XOR X-Free M I S R Scan Chain & m-bit Selection
20 m-bit Scan Chain & b Decompressor Scan Chain Phase Shifter M I S R & XOR X-Free M I S R Scan Chain & Cycles = mq b Total X s Num. Signatures = m q b b Selection Reg. Interval Count
21 Num. Signatures = ANALYSIS Total X s m q Total Data = (mq)(num. Signatures) = If q << m Total Data (q)(total X s) (mq)(total X s) m q q Coverage 5% 75% 87.5% 93.75% 96.88% 98.44% 99.2% 99.6% 99.8% 99.9% 99.95% 99.97% 99.99% % % %
22 ANALYSIS Total Data (q)(total X s) Tester Storage Independent of Design Size Scan Architecture Number Scan Chains Scan Length Scan Cells Number Test Vectors Error Coverage Independent of Distribution of X s q Coverage 5% 75% 87.5% 93.75% 96.88% 98.44% 99.2% 99.6% 99.8% 99.9% 99.95% 99.97% 99.99% % % %
23 COMPARISON X-Compact [Mitra & Kim, TCAD 4] Combinational Compactor Tester Channels log 2 (Scan Chains) Tester Storage = 2 (Num. Slices) log 2 (Scan Chains) = 2 (Num. Vectors) (Scan Length) log 2 (Scan Chains) Error Coverage Tolerates One X per Scan Slice Detects, 2, and Odd Errors per Scan Slice
24 794x 794x 39x 39x 79x 43x 3 2.5%.% % 7.9x 7.9x 3.9x 3.9x 2.7x.6x 6 5.%.3% 6 8 % 5.9x 5.9x 27.8x 27.8x 4.6x 2.7x 7 6.%.3% % 79x 79x 39x 39x 2.8x 7.x 9.8%.2% % 59x 59x 278x 278x 23.3x 2.8x.8%.2% % q = % Cov. q = % Cov. Comp. Ratio Outputs Chains X-Canceling MISR X-Compact Slices w/more than One X Scan % X s COMPARISON
25 FAULT COVERAGE 99.4% 99.95% % 99.2% 99.8% 99.97% s % 99.9% % 99.2% 99.8% 99.97% s % 99.9% % 99.2% 99.8% 99.95% 7 9 s % 99.8% % 99.2% 99.8% 99.95% 7 9 s327 Fault Coverage Error Coverage X-Canceled Combinations (q) Circuit
26 CONTINUOUS SCAN SHIFTING m-bit m-bit Scan Chain & Decompressor Scan Chain Phase Shifter M I S R S H A D O W & XOR Scan Chain & Selection Reg.
27 794x 794x 39x 39x 79x 43x 3 2.5%.% % 7.9x 7.9x 3.9x 3.9x 2.7x.6x 6 5.%.3% 6 8 % 5.9x 5.9x 27.8x 27.8x 4.6x 2.7x 7 6.%.3% % 79x 79x 39x 39x 2.8x 7.x 9.8%.2% % 59x 59x 278x 278x 23.3x 2.8x.8%.2% % q = % Cov. q = % Cov. Comp. Ratio Outputs Chains X-Canceling MISR X-Compact Slices w/more than One X Scan % X s COMPARISON
28 For a Particular Pattern i CIRCUIT D D D D s = Minimal Set of Scan Cells for which Observation Detects All Faults Probabilistic Observation High Coverage of All Scan Cells Deterministic Targeting of D s Focus on Detecting D s
29 M O 3 X 3 X M2 O 4 D 8 O 2 M 3 O 5 O 9 O 3 M 4 D 6 O X 2 M 5 O 7 O O 5 M 6 X 4 O 2 O 6
30 M = X O 3 X 3 M2 = O2 O 4 D 8 M 3 = O 3 O 5 O 9 M 4 = X 2 D 6 O M 5 = O 5 O 7 O M 6 = O 6 X 4 O 2
31 O 3 M = O 2 X 3 O 4 M 2 = O 3 X D 8 O 5 M 3 = X X 2 O 9 D 6 M 4 = O 5 O O 7 M 5 = O 6 X O X 4 M 6 = X O 2
32 M = X O 3 D 8 O 3 M 2 = X O 2 X 2 X 3 O 9 O 4 M 3 = O 2 O 5 X 3 O O 5 M 4 = X O 6 O D 6 M 5 = X O 2 X 3 O 2 O 7 M 6 = O 2 X 3 X 4
33 M = X O 3 D 8 O 3 O 3 X 3 X M2 = X O2 X2 X3 O9 O4 O 4 D 8 O 2 M 3 = O 2 O 5 X 3 O O 5 O 5 O 9 O 3 M 4 = X O 6 O D 6 D 6 O X 2 M 5 = X O 2 X 3 O 2 O 7 O 7 O O 5 M 6 = O 2 X 3 X 4 X 4 O 2 O 6
34 X 3 X M = X D 8 M2 = X X2 X3 D 8 M 3 = X 3 M 4 = X D 8 D 6 X 2 M 5 = X X 3 M 6 = X 3 X 4 X 4
35 MISR BIT COMBINATIONS Linearly Dependent Combinations of MISR Bits No Dependence on X s Guaranteed to Exist When More MISR Bits Than X s X X 2 X 3 X 4 D 8 D 6 X X 2 X 3 X 4 D 8 D 6 M = X D 8 M 3 M 5 M 2 = X X 2 X 3 M 3 = X 3 Gaussian Elimination M 2 M 5 M 3 M 4 = X D 6 M 3 M 6 M 5 = X X 3 M M 3 M 5 M 6 = X 3 X 4 M 3 M 4 M 5
36 M M4 M 3 = O 2 X 3 O 5 O O 5 M 4 = X O 6 O O 6 M 5 = X O 2 X 3 O 2 O 7 M 3 M 5 M 2 M 5 M 3 M 3 M 6 M M 3 M 5 = M M 4 = O 3 O 6 D 8 O O 3 D 6 M 3 M 4 M 5
37 ALIASING Checking Only One Combination that Depends on All D s Odd Number of D s Have Errors NO PROBLEM (Error Detected) Even Number of D s Have Errors PROBLEM (All Errors Cancel Out) Solutions Check Multiple Combinations Rather than Just One Use Multiple MISR Design
38 COMPARISON m bit MISR VS m/k bit MISR m/k bit MISR m/k bit MISR Characteristics Multiple Combinations Multiple MISR Number of MISR bit Combinations Checked k combinations from one m bit MISR combination each from k m/k bit MISRs Storage Requirements k*m = km bits k*(m/k) = m bits Error Coverage (-2 -k ) (-2 -k ) * * If D s evenly distributed between MISRs
39 MULTIPLE VS SINGLE MISR Assuming All Error Combinations Equally Likely: Combinations Checked (k)( Error Coverage Bits on Tester for m-bit MISR Bits on Tester for (m/k)-bit( MISRs 5% m m 2 75% 2m m % 3m m % 4m m Issues with Multiple MISRs X s and D s Not Evenly Distributed One of (m/k) Bit MISR Gets Saturated Earlier Multiple MISR Error Coverage Lower than Single MISR
40 DESIGN EXAMPLE m bits on tester m B I T M I S R Checking combination Error Coverage 5%
41 DESIGN EXAMPLE m bits on tester m bits on tester m m/2 B I T M I S R Checking combination bit MISR m/2 bit MISR Checking 2 combinations ( from each) Error Coverage 75% Sensitive to X & D Distribution Error Coverage 5%
42 DESIGN EXAMPLE m B I T M I S R m bits on tester Checking combination Error Coverage 5% SCAN CHAIN SCAN CHAIN 2 SCAN CHAIN 3 SCAN CHAIN 4 SCAN CHAIN 5 SCAN CHAIN 6 SCAN CHAIN 7 SCAN CHAIN 8 SCAN CHAIN SCAN CHAIN 3 SCAN CHAIN 5 SCAN CHAIN 7 SCAN CHAIN 2 SCAN CHAIN 4 SCAN CHAIN 6 SCAN CHAIN 8 m/2 bit MISR m/2 bit MISR m/2 bit MISR m/2 bit MISR Checking 2 combinations ( from each) OR Checking 2 combinations ( from each) m bits on tester ONE selection bit Error Coverage 75% Sensitivity to X & D Distribution REDUCED
43 DESIGN EXAMPLE m m bits on tester m/4 m/4 m/4 m/4 m/4 m/4 Checking 4 combinations ( from each) m6 bits on tester THREE selection bits B I T M I S R Checking combination Error Coverage 5% m/4 m/4 m/4 m/4 m/4 m/4 m/4 m/4 OR Checking 4 combinations ( from each) Error Coverage 93.75% Sensitivity to X & D Distribution FURTHER REDUCED m/4 m/4
44 DESIGN EXAMPLE 64 B I T M I S R 52 bits on tester Checking 8 combinations Error Coverage 99.6% 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit Checking 8 combinations (2 from each) OR Checking 8 combinations (2 from each) 4*(663) 4 bits on tester Error Coverage 99.6% Sensitivity to X & D Distribution FURTHER REDUCED
45 COMPARISON Probabilistic Observation Deterministically Targeting D s MISR Requirement 64-bit MISR 6 6-bit MISRs Dependence on X s YES YES Dependence on D s NO YES X s/d s Tolerated Combinations checked 8 (99.6% error cov.) 8 (99.6% error cov.) Bits on Tester 64*8 = 52 4*(663) = 4 # bits 52/56 = 9.2 per X 4/56 = 2.5 per X or D
46 COMPRESSION ACHIEVED % of X's % of D's % 2% 4% 6% % 2.3x 4.5x 9.x 6.6x 3%.x 9.x 6.6x 5.3x 5% 7.6x 6.6x 5.3x 4.5x 8% 5.3x 4.8x 4.2x 3.7x % 4.5x 4.2x 3.7x 3.3x
47 COMBINING WITH X-MASKING Combining X-Canceling with X-Masking Do Not Need to Mask All X s Target Only Easy-to-Mask X s Do Not Need to Mask All Scan Chains or Scan Slices Containing X s If Masking X Blocks Observation of Fault Let X Pass Through to X-Canceling MISR
48 CONCLUSIONS Tester Storage Requirements O(Total X s) Independent of Scan Architecture Error Coverage Arbitrarily High Independent of Distribution of X s Area Overhead Linear in Size of MISR For X-Bounding Can Use as Safety Feature Handle Unexpected X s
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