CLASS E switching-mode circuits [1] [35] have

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1 JOURNAL OF L A TEX CLASS FILES, VOL. 6, NO. 1, JANUARY 27 1 Design Procedure for Class E Switching Circuits Allowing Implicit Circuit Equations Hiroo Sekiya, Member, IEEE,, Toru Ezawa, and Yuichi Tanji, Member, IEEE. Abstract This paper presents novel design procedures for the class E switching circuits allowing the implicit circuit equations. Because of the allowance, the circuit simulators can be used in the proposed design procedures. Moreover, the proposed design procedures also allow any conditions considered until now. The proposed design algorithms are implemented by using PSpice and OPTIMUS. This paper shows the design examples of two kinds of the class E switching circuits. In particular, the design example of the class E oscillator shows the benefit of the proposed design procedure eminently, that is, it is unnecessary to make an equivalent model of the semiconductor devices for the design. These design examples show the validity and effectiveness of the proposed design procedures. Index Terms class E switching, computer aided design, Newton s method, initial conditions, steady state, PSpice, OPTIMUS. I. INTRODUCTION CLASS E switching-mode circuits [1] [35] have become increasingly valuable building blocks in many applications, e.g., the radio transmitters, the switching-mode dc power supplies, the devices of the medical application, and so on. Because of the class E switching, namely, both zero voltage and zero slope of voltage switching, the class E switching circuits can achieve high power conversion efficiency under high frequency operations. It is, however, quite difficult to design the class E switching circuits since two conditions should satisfy simultaneously, which is the most important problem of the class E switching circuits. Since the introduction of the class E amplifier, many analytical descriptions of this circuit have appeared [1] [16]. Early analyses have assumed an ideal switch, infinite output network Q (i.e., sinusoidal output current), and an RF choke in the dc supply lead (i.e., constant current drive) [1], [2]. Later works have allowed finite output network Q [3] [9], [11], finite dc-feed inductance [5] [9], drain current fall time [1], [11], nonzero active device on-resistance [5], [6] and Manuscript received, Oct. 31, 27, and revised Apr. 17. This research was partially supported by Saneyoshi Scholarship Foundation and Grant-in-Aid for scientific research (No and ) of JSPS. H. Sekiya and T. Ezawa are with the Graduate School of Advanced Integration Science, Chiba University, Chiba, JAPAN sekiya@faculty.chiba-u.jp. H. Sekiya is also with Department of Electrical Engineering, Wright State University, Dayton, Ohio, USA and partially carried out this research as a Research Fellowship, Japan Society for the Promotion of Science (JSPS). Y. Tanji is with the Department of Reliability-based Information Engineering, Kagawa University, Kagawa, JAPAN. Copyright (c) 28 IEEE. Personal use of this material is permitted. However, permission to use this material for any other purposes must be obtained from the IEEE by sending an to pubs-permissions@ieee.org. nonlinear parasitic capacitance on the active device [13] [16]. If the design values are expressed as the functions of the design specifications, it is fast to derive the design values. The accuracy of the design values is, however, not so high since it is necessary to idealize the circuit model for the analysis. Moreover, many efforts are needed to analyze it. In [5] and [12], the design values are derived numerically from the analytical waveform equations. These design procedures also need to solve the circuit equations analytically. In [9], the design values are expressed as the functions of the design parameters that are fitted into the sample data of the design values. This procedure provides fast and accurate design if the design functions can be derived. The sample data of the design values, however, should be derived by using other design procedures. Therefore, the processes to derive the design equations should be repeated if the topologies of the circuits are varied. The design procedures in [17] and [18] present the design procedure from numerical approaches. These procedures require only the circuit equations and the other processes of the design are carried out with an aid of computer. Therefore, the design of the class E switching circuits can be accomplished with few efforts. The design scheme in [18], however, requires that circuit equations have to be piecewise linear expressions since the explicit waveform equations should be derived. On the other hand, the scheme in [17] allows any expressions of circuit equations. By the way, many designers request to use the circuit simulators, e.g., Spice in order to design the class E switching circuits since it is spiny to formulate the circuit equations, especially, for high dimensional circuits [23], [32] [35]. Moreover, the circuit simulators have rich element models, namely, the MOSFETs, the diodes, and so on. It is a common knowledge for the designers that the effects of the parasitic resistance [5], [6], the output capacitance and its nonlinearities [13] [16], and the drain current fall time [1], [11] are quite important and should be taken into account for the design of the class E switching circuits. From this point of view, it is recognized that the device models in the circuit simulators are powerful and helpful. Any design procedures presented until now, however, never allow using the circuit simulators. This is because all the design procedures until now require the explicit circuit equations. If a design procedure allows the implicit circuit equations, the designers can use the circuit simulators for the design of the class E switching circuits. This paper presents novel design procedures for the class E switching circuits allowing the implicit circuit equations. Because of the allowance, the circuit simulators can be

2 JOURNAL OF L A TEX CLASS FILES, VOL. 6, NO. 1, JANUARY 27 2 applied to design the class E switching circuits. Moreover, the proposed procedures require only the waveform data and has no relationship with the conditions to derive the waveform. Therefore, the proposed design procedures allow any conditions, namely, any output Q, finite dc-feed inductance, drain current fall time, nonzero active device on-resistance, nonlinear parasitic output capacitance, and so on. The proposed design algorithms are implemented by using PSpice 1 [36] and OPTIMUS 2 [37]. This paper shows the design examples of two kinds of the class E switching circuits, namely, the class E amplifier and the class E oscillator. Both the circuits can be designed with high accuracy. In particular, the design example of the class E oscillator shows the benefit of the proposed design procedure eminently, that is, it is unnecessary to make a model of the semiconductor device for the design. These design examples show the validity and effectiveness of the proposed design procedures. II. FORMULATION OF THE PROBLEM In this section, the problem to derive the design values of the class E switching circuits are formulated. The design problem resolves itself into the solution of the algebraic equations. A. Circuit Description Let us consider a dynamic circuit described by a set of differential equations : dx = f(t, x, λ), (1) dt where t R, x R n, and λ R m denote the time, a n-dimensional state, and a m-dimensional system parameter, respectively. In this paper, For simplicity, f : R R n R m R n (t, x, λ) f(t, x, λ) is assumed as C mapping and is periodic in t with period t T : f(t + t T, x, λ) = f(t, x, λ). (3) We also assume that (1) has a solution x(t) = ϕ(t, x, λ) defined on < t < with every initial condition x R n and every λ R m : x() = ϕ(, x, λ) = x. B. Steady-state Conditions By the periodic hypothesis (3), we can naturally define a C diffeomorphism T from state space R n into itself : T : R n R n x T (x, λ) = ϕ(t T, x, λ). The mapping T is often called the Poincaré mapping. If a solution x(t) = ϕ(t, p, λ) is periodic with period t T, the point p R n is a fixed point of T : (2) (4) T (p, λ) = p. (5) If p = x, (5) corresponds to the boundary conditions for a steady state. The numerical derivation of the boundary conditions from (5) is called as shooting method, in which generally the Newton s method is used to solve (5). 1 Cadence Design Systems Inc. 2 Noesis Solutions NV. C. Other Conditions For the designs of the class E switching circuits, we should consider the class E switching conditions, a specified output power, and so on. If the number of conditions is N( m), the conditions that consist of each condition g k at t = t ck are expressed as G(x, λ) = g 1 (t c1, x, λ) g 2 (t c2, x, λ). g N (t cn, x, λ) =, RN. (6) In this case, we can find N design parameters. Therefore, the other (m N) parameters must be given as the design specifications. We recognize that the design of the class E switching circuits boils down to solving the algebraic equations (5) and (6). III. THE PREVIOUS DESIGN PROCEDURE[17] In this section, the algorithm proposed in [17] is summarized and the weaknesses of it is pointed out. Now, (5) and (6) are rewritten as follows: [ ] T (x, λ) x F 1 (x, λ) = =, R n+n (7) G(x, λ) where, T (x, λ), x, and λ are expressed as T (x, λ) = [T 1 (x, λ), T 2 (x, λ),, T n (x, λ)] T, x = x() = [x 1 (), x 2 (),, x n ()] T, and λ = [λ 1, λ 2, λ m ] T. Moreover, we define λ u R N as λ u = {λ u1, λ u2,, λ un λ uk (k = 1, 2,, N) are unknown design parameters in λ.} (7) are solved by using Newton s method that is a general algorithm to solve algebraic equations. Since the unknown values of (7) are expressed as u R n+n : u = [x T, λ u T ] T, the computations u k+1 = u k F 1(u k ) F 1 (uk ) are iterated for u k+1 u k < δ in order to find the unknown values, where F 1 R (n+n) (n+n) means Jacobian matrix of F 1, that is, F 1(u k ) T 1 (u k ) x 1 () 1 T 1 x 2 () T 2 (u k ) x 1 (). = T n (u k ) T n x 1 () x 2 () g 1 (t c1, u k ) g 1 x 1 () x 2 (). g N (t cn, u k ) g N x 1 () x 2 () (8) (9) T 1 T 1 T 1 x n () λ u1 λ un T 2 T 2 λ u1 λ un T n x n () 1 T n T n λ u1 λ un g 1 g 1 g 1 x n () λ u1 λ un g N g N g N x n () λ u1 λ un (1) T 2 x 2 () 1 T 2 x n (),

3 JOURNAL OF L A TEX CLASS FILES, VOL. 6, NO. 1, JANUARY 27 3 k is an iteration number and δ 1. Then u k+1 is a solution of (7). The elements of Jacobian matrix F 1(u k ) of (1) can be determined by solving the first-order variational equations d ϕ = df ϕ ϕ, with t= = I, dt x dx x x d ϕ = df ϕ dt λ dx λ + f (11) ϕ, with λ λ t= =. It can be regarded that (11) is the differential equations about ϕ(t, u k )/ x and ϕ(t, u k )/ λ. Therefore, our solving (11), the Newton s method of (9) is iterated numerically. From above computations, the unknown parameters u can be obtained, and the design values, that is, λ u are determined. Not only the procedure in [17] but other procedures presented until now require the explicit circuit equations f. This is the reason why the circuit simulator cannot be used for the design of the class E switching circuits. Generally, it is difficult to acquire the explicit circuit equations from the circuit simulators. In the procedure of [17], the circuit equations f are used to derive the first-order variational equations. Moreover, the conditions g k must be expressed by the circuit responses at t = t ck since the elements of Jacobian matrix is calculated from the variational equations of (11). IV. PROPOSED DESIGN PROCEDURE In this section, the design procedures allowing the implicit circuit equations are proposed. We apply the numerical approximations in order to calculate the partial differentials of Jacobian matrix (1). In this paper, two design algorithms are presented. They are classified whether initial condition x can be given arbitrarily or not for the derivations of F 1 (x, λ) in (9). A. Algorithm 1 First, it is assumed that the rigorous initial condition x is given arbitrarily. Figure 1 shows a flowchart of Algorithm 1. The difference between the proposed procedure and the previous one in [17] is only the way to the calculations of the partial differentials in (1). When a new vector u εi is defined as u εi = [u 1, u 2,, u i + ε,, u n+n ], (12) the approximate values of the partial differentials in F 1(u k ) are calculated by using the following approximation T j (u k ) = T j(u k εi ) T j (u k ), u i ε g l (u k ) = g l(u k εi ) g l (u k (13) ). u i ε In (13), i = 1, 2,, n+n, j = 1, 2,, n, l = 1, 2,, N, and ε 1 means a minute variation. Moreover, T j (u k εi ) and g l (u k εi ) can be derived only by substituting u εi for u from the derivation of F 1 (u). The proposed procedure uses the numerical approximation of (13) instead of solving the first variational equation of (11). This slight difference produces a significant improvement of the design tool. The most important point is that the k=k+1 k= Determination of u Simulation and derivation of ϕ for < t < t T with uk and derivation of F 1 (u k ) in (7) i= Determination of u εi k in (12) Simulation and derivation of ϕ for < t < t T with u εi k and derivation of T j (u εi k) and g l (u εi k) i>=n Yes Derivation of F 1 '(u k ) at (1) with calculation of (13) Derivation of uk+1 with calculation of (9) No uk+1-uk < δ Yes No i=i+1 Derivation of λu, namely, design values Fig. 1. Flowchart of Algorithm 1. The derivation of Jacobian matrix (The difference from the previous paper) circuit equations f are unnecessary in (13). This means that the implicit circuit equations are allowed in the proposed procedure though they are not allowed in the previous ones. Therefore, we can use the circuit simulators like PSpice in the design process. B. Algorithm 2 Most of all circuit simulators may be accept the rigorous initial values x. There are, however, the cases that it is difficult to give them to the circuit simulator. The flowchart of Algorithm 2 is shown in Fig. 2. Instead of the shooting method, Algorithm 2 apply the transient analyses for a long interval to (1) in order to obtain the waveforms in the steady state. Now, the transient analysis is carried out for t Mt T, where M is a natural number that is large enough to be ϕ(mt T ) ϕ((m 1)t T ). (14) Moreover, it is assumed that all the conditions in (6) are acquired from the steady state waveforms. Then, the design values can be calculated by solving only (6) that is rewritten as g 1 (λ) g 2 (λ) F 2 (λ) = G(λ) =. g N (λ) =, RN. (15) Note that g k is a function of only λ, not x. We define λ u R N that is the same as (8). The equations (15) are solved by using Newton s method with the iterative computations λ u k+1 = λ u k F 2(λ u k ) F 2 (λ u k ), (16)

4 JOURNAL OF L A TEX CLASS FILES, VOL. 6, NO. 1, JANUARY 27 4 k=k+1 k= Determination of λu VD LC ic L C Transient simulation of ϕ for < t < Mt T with λu k and derivation of F 2 (λu k ) in (16) i= Determination of λuεi k in (17) Transient simulation of ϕ for < t < Mt T with λuεi k and derivation of g(λuεi k ) and T(λuεi k ) i>=n Yes Derivation of F 2 '(λuk) with calculation of (13) Derivation of λu k+1 with calculation of (16) No λu k+1 -λu k < δ Yes No i=i+1 Derivation of λu, namely, design values Fig. 2. Flowchart of Algorithm 2. The derivation of Jacobian matrix (The difference from the previous paper) VD S Dr S rs vs LC ic vs ics io v Cs R vo L C ics io v R vo Cs Fig. 3. Circuit topology of the class E amplifier. Circuit topology using a MOSFET model. Equivalent circuit model using an ideal switch. for λ u k+1 λ u k < δ. Jacobian matrix F 2 is given by the same procedure in Algorithm 1. In Fig. 2, the vector λ uεi is defined as λ uεi = [λ u1, λ u2,, λ ui + ε,, λ n+n ]. (17) V. DESIGN EXAMPLES USING PSPICE The proposed algorithms are implemented by using PSpice [36] and OPTIMUS [37]. PSpice is well known as one of the most popular circuit simulators and provides the numerical data of waveforms. By using Orcad Capture [38], the circuit configuration is given to a computer graphically. OPTIMUS is used as a interface between the PSpice and the proposed algorithms. This means that the unknown parameters x and/or λ u are given from our algorithms to PSpice via OPTIMUS. Oppositely, the numerical data of the waveforms ϕ is given from PSpice to our algorithms via OPTIMUS. In this paper, we show the design examples of two kinds of the class E switching circuits by using the developed design tool. These circuits are the class E amplifier and the class E oscillator. The class E amplifier is known as a typical class E switching circuit. It is operated by a forced driving signal. On the other hand, the class E oscillator generates an autonomous oscillation with the feedback network. A. The Design of Class E Amplifier Two design examples of the class E amplifiers are shown in this section, which are the class E amplifiers with an ideal switch model and with a MOSFET model. PSpice does not allow users to give the rigorous initial conditions when semiconductor devices are included in the circuit Dr ic vs io ON OFF 2 θ θ 2 θ 2 2 θ ic v f vs io V th ON OFF 2 θ θ 2 θ 2 Fig. 4. Examples of nominal waveforms. Class E amplifier. Class E oscillator. configurations. This means that PSpice has an automatic function of Finding bias point. If semiconductor devices are replaced by ideal models, e.g., an ideal switch model, the initial conditions can be given arbitrarily to PSpice. Figure 3 depicts the circuit topology of the class E amplifier. It consists of a dc supply voltage V D, a dc-feed inductance L C, a switch S, a shunt capacitance C S, a series resonant circuit L C, and an output resistor R. An example of the waveforms of the class E amplifier is shown in Fig. 4 when the switch on duty ratio is 5%. The switch is driven by a driving pattern of D r. While the switch is off, the current through the shunt capacitor produces the voltage v S across the switch. Since the switching loss is reduced to 2 θ

5 JOURNAL OF L A TEX CLASS FILES, VOL. 6, NO. 1, JANUARY 27 5 zero by the operating requirements of zero and zero slope of switch voltage (v S = and dv S /dt = ) at the turn on transition, called class E switching conditions, the theoretical efficiency of class E amplifier is 1%. If the loaded quality factor Q = ωl/r is high, the output current is sinusoidal, where ω = f/(2) is an angular frequency for the operating frequency. Moreover, when the dc-feed inductance is high enough to work as RF choke, the input current i C is constant as shown in Fig. 4. 1) Ideal Switch Model: First, the class E amplifier is designed using the ideal switch model. The equivalent circuit of the class E amplifier with the ideal switch model is shown in Fig. 3. Compared with Fig. 3, the MOSFET is replaced by the ideal switch, the equivalent series resistance r S, and the parasitic capacitance which is included in C S. This model has no semiconductor devices, so the Algorithm 1 can be applied to the derivation of the design values. The design specifications are as follows; the operating frequency f = 1.MHz, the dc supply voltage V D = 5.V, the output resistor R = 5.Ω, the switch on duty ratio D =.5, Q = 1 and the ratio of the resonant inductance to the dc-feed one is L /L C =.1. This design specifications means high Q and high L C. Moreover, the switch-on resistance r S =.16Ω that follows the data sheet of IRF53 MOSFET. From these specifications, the resonant and the dc-feed one are obtained as L = 7.96µH and L C = 7.96mH, respectively. Therefore, the unknown parameters λ u are set as λ u = [C, C S ]. Here, the conditions for the design are determined. First, the boundary conditions are given as follows; T (x, λ) x = i C (t T ) i C () v S (t T ) v S () i o (t T ) i o () v(t T ) v() = (18) where t T means the period of the operation, that is, t T = 1/f = 1 6 sec. Moreover, we define that the switch turns on at t =. Next, the class E switching conditions should be considered for the design of the class E amplifier, namely, [ ] vs (t G(x, λ) = T ) = (19) i CS (t T ) because of i CS = C S dv S /dt. As a result, the design equations for the class E amplifier modeled in Fig. 3, given as; F 1 (x, λ) = i c (t T ) i C () v S (t T ) v S () i o (t T ) i o () v(t T ) v() v S (t T ) i CS (t T ) =. (2) Following Algorithm 1, the unknown parameters λ u are derived as C = 3.65nF and C S = 6.1nF. The waveforms from PSpice are shown in Fig. 5. From the waveforms of v S and i CS in Fig. 5, the class E switching conditions are achieved. (A) ics (A) vs (V) (V) c i Dr (V) vo TABLE I SPICE MODEL OF IRF53 MOSFET. T ox 1 n P b.8 U o M j.5 P hi.6 F c.5 Rs.16 C gso p K p 2.73 µ C gdo p W.68 R g 4.63 L 2 µ I s p V to N 1. R d m T t 125 n R ds K R b Time (ms) (A) ics (A) vs (V) (V) c i Dr vo (V) Time (ms) Fig. 5. Nominal waveform of the class E amplifier from PSpice simulation. Ideal switch model with the design procedure for Algorithm 1. MOSFET model with the design procedure for Algorithm 2 2) MOSFET Model: Next, the design of the class E amplifier with a MOSFET as shown in Fig. 3 is carried out. In this case, Algorithm 2 should be applied to this design. In this paper, we use a power MOSFET Spice model Level 3. Table I shows the specifications of the MOSFET in our simulations, namely, the model of IRF53 MOSFET. The design specifications are almost same as those for the class E amplifier with the ideal switch model, except switch on resistance. The switch on resistance is included in the model of IRF53 MOSFET. It is assumed that 5 periods are long enough for the responses of the amplifier to be in the steady state, namely M = 5 is given. For the determination of M, several transient analyses for different parameters are carried out. From these results, it seems that the waveforms need at least M = 25 to be in the steady state. The smaller the number of the period M is, the shorter the total computation time is. However, if the interval of the transient analysis is not long enough for the waveforms to be in the steady state, Newton s method diverges. In this case, we need to calculate

6 JOURNAL OF L A TEX CLASS FILES, VOL. 6, NO. 1, JANUARY 27 6 TABLE II THE DESIGN VALUES OF THE CLASS E AMPLIFIER FOR f = 1.MHZ, V D = 5.V, Q = 1., D =.5 AND L /L C =.1. Model Ideal switch Ideal switch Ideal switch MOSFET Procedure [17] Algorithm 1 Algorithm 2 Algorithm 2 C 3.63 nf 3.65 nf 3.65 nf 3.64 nf C S 6.19 nf 6.1 nf 6.1 nf 5.59 nf Computation time 12 s 97 s 99 s again after a new M is set, which generates much time loss. Therefore, we set M about twice as large as the minimum of the results at pre-tests. As a result, the design conditions for the design are given as; [ ] vs (Mt F 2 (λ) = T ) =. (21) i CS (Mt T ) Following Algorithm 2, the design values are obtained as C = 3.64nF and C S = 5.59nF. The waveforms from PSpice are shown in Fig. 5. From the waveforms of v S and i CS in this figure, it is also confirmed that the class E switching conditions satisfy. Compared with Figs. 5 and, the waveforms are almost identical though the switching device is changed from the ideal model to the MOSFET. In the simulations, an ideal square voltage as shown in Fig. 5 is used as a driving signal. Moreover, IRF 53 MOSFET realizes the fast switching in 1MHz operation. They are reasons why the waveforms with MOSFET are almost same as those with the ideal switch. Table II shows the design values from the design procedure in [17] and the proposed algorithms for the identical specifications. In this table, we add the design values when Algorithm 2 is applied to the design of the class E amplifier with the ideal switch. There is about 5pF difference of C S between the ideal switch model and the MOSFET model. The value of 5pF is obtained as the drain-source capacitance from the data sheet of IRF53 MOSFET. From this result, it is clarified that the design values reflect the built-in parameters of the MOSFET. Table II also shows the examples of computation time for the identical initial values. The computations are carried out on the computer whose specifications are; CPU: AMD Athlon(tm) 64 X2 Dual Core Processor GHz, Memory: 2GB, and Operating System: Windows XP Professional Ver. 22 Service Pack 2. Please note that the computation time depends on the number of conditions, the initial values, the step time of PSpice, and M. In these examples, the computation times of Algorithm 2 are about 8 times as long as Algorithm 1. This difference appears due to the transient analyses, which is, however, not so large in spite of M = 5. This is because that the start-up and shut-down time of PSpice is dominant in the computation time. B. The Design of Class E Oscillator Figure 6 shows the circuit topology of the class E oscillator [19]-[21]. The class E oscillator consists of the same topology as the class E amplifier and the feedback network C 1, TABLE III DESIGN AND EXPERIMENTAL RESULTS OF THE CLASS E OSCILLATOR. Calculated Measured Difference L C 2.6mH 2.6mH.% L 7.96µH 7.96µH.% L f 5.28µH 5.24µH.76% C S 1.12nF 1.12nF.% C 962pF 944pF 1.87% C 1 962pF 956pF.62% C nF 9.62nF.% R 1.2Ω 1.2Ω.% R d1 75kΩ 75kΩ.% R d2 248kΩ 248kΩ.% r LC.5Ω.5Ω.% r L.27Ω.27Ω.% r Lf.Ω.23Ω V D 12.V 12.V.% V o 7.V 7.2V.29% P o 4.79W 4.82W.57% f 2.MHz 1.95MHz 2.5% η 91.1% 89.2% 2.9% C 2, and L f. R d1 and R d2 are resistors for supplying the bias voltage to the MOSFET and they are large enough to neglect the current through them. Figure 6 shows the equivalent circuit of the class E oscillator. In this figure, C g and r g are the equivalent series capacitance and the resistance between the gate and the source of the MOSFET, respectively. The nominal waveforms of the class E oscillator are shown in Fig. 4. It is, however, driven by the feedback voltage v f, which is different from the operation of the class E amplifier. When the feedback voltage v f is larger than the threshold voltage V th of the MOSFET, the MOSFET is in on state. Oppositely, in case of v f < V th, the MOSFET is in off state. The feedback voltage v f is sinusoidal as shown in Fig. 4 because of L f C g resonance circuit. This means that the modeling of the MOSFET is quite important for the design of the class E oscillator, but it is difficult. In this paper, we design the class E oscillator without modeling of the MOSFET. The design specifications are given as follows; the operating frequency f nom = 2MHz, the input voltage V D = 12V, the load resistance R = 1Ω, the loaded quality factor Q = 1, and L /L C =.3. From Q and L /L C, the inductances L and L C is determined as L = 7.95µH and L C = 2.65mH, respectively. In this design, we use IRF53 MOSFET whose threshold voltage is V th = 3.19V as shown in Tab. I. From V D = 12V and V th = 3.19V, R d1 = 75kΩ and R d2 = 25kΩ are given. We prepare the discrete components and use the measured values of R, L, L C, R d1, and R d2 for the calculations. Moreover, the parasitic resistances of L and L C that are defined as r L and r LC are measured and used for the design. Finally, we set the relation among C, C 1 to C 2 as C /C 1 = 1 and C 1 /C 2 =.1. Unknown parameters λ are defined as λ u = [C, C S, L f ]. For the computations by Algorithm 2, the time interval of 25µs is given for the transient analysis, which is determined from the same process as the class E amplifier with MOSFET. From the waveform data of PSpice, we can acquire the self-oscillating frequency f data. Therefore, f data f nom = (22)

7 JOURNAL OF L A TEX CLASS FILES, VOL. 6, NO. 1, JANUARY V D ic (A).5 i C R d1 R d2 V D L C r LC i c L C r LC S v f L f i f L C L C v s i v C1 v 1 C S C 2 v 2 r Lf r L r L C 1 L f r Lf R v o R d1 vo (V) vs (V) vf (V) Time (ms) Fig. 7. Waveforms of the class E oscillator for f = 2 MHz and Q = 1. Waveforms from PSpice. Experimental waveforms. Vertical: i c :.5A/div, v f, v S and v o :2V/div. Horizontal:.2µs/div. S r s v s i v i f v g C g v 2 C S R v 1 v o C 2 r g v f R d2 Fig. 6. Circuit topology of the class E oscillator. Circuit topology. Equivalent circuit model. is given as a specified condition. The class E oscillator should achieve the class E switching conditions; v S (t s ) = i CS (t s ) =. (23) Here, t s means the time of turn-on transition of the MOSFET, namely, the relations v f (t s ) = V th and dv f /dt t=ts > satisfy simultaneously. Consequently, the conditions for the design can be given as F 2 (λ) = v S (t s ) i CS (t s ) f data f nom =. (24) Following Algorithm 2, the unknown parameters are determined as C = 962pF, C S = 1.12nF, L f = 5.28µH, C 1 = 962pF, and C 2 = 9.62nF. Figure 7 shows the PSpice and the experimental waveforms of the class E oscillator. Table III shows the calculated values and measured ones. In this table, Calculated means the values applied to or obtained from the proposed algorithm, and Measured does the values measured from the circuit experiments. All the element values including parasitic resistances and measured by the impedance meter of HP4284A. The input voltage V D and the input current I D are obtained from the digital multimeter of Iwatsu VOAC7532. The output voltage V o and the frequency f are from the digital multimeter of Agilent 3458A. Moreover, the output power P o and the power conversion efficiency η are calculated as P o = V o 2 R, η = P o = V o 2, (25) P I RV D I D where the output voltage V o and the input current I D are calculated as ts V o = f data vo(t)dt, 2 t s 1/f data ts (26) I D = f data i 2 C(t)dt. t s 1/f data From Fig. 7 and Tab. III, both the waveforms are satisfied with the class E switching conditions and the specified frequency. Moreover, the experimental results are good agreement with PSpice ones quantitatively. These show the validity of the proposed design procedure. Note that the derived design values reflect the capacitance and the resistance between the gate and the source of the MOSFET, and the capacitance between drain and source. The laboratory measurement achieves 89.2% efficiency under the 4.82W and 1.95MHz output. VI. DISCUSSIONS A. Advantages of the proposed design procedure We think that the advantages of the proposed algorithms are as follows. 1) If the circuit equations are implicitly formulated by using the circuit simulator, all the steps of the designs are carried out with an aid of computer like the development tool. Hence, the process to set up the explicit circuit equations by hand is left out compared with the method in [17]. Note that the proposed algorithms can be used when the explicit circuit equations are given.

8 JOURNAL OF L A TEX CLASS FILES, VOL. 6, NO. 1, JANUARY ) Since it is unnecessary to derive the variational equations, the conditions g k do not have to be expressed by the circuit responses at t = t ck, namely ϕ(t ck ). If only the conditions are observed from the responses of the circuit, any constraint conditions are allowed. The proposed design procedure allows not only the class E switching conditions but the statistic conditions, e.g., average, maximum, and minimum current/voltage. The conditions of the frequency in the design of the class E oscillator are also a good example of this advantage. 3) The accuracy of the design values are determined by δ that is a stop condition of Newton s method. Therefore, the derived design parameters are identical to those from the procedure in [17] if the same circuit equations and δ are given. Note ε in (13) is independent on the accuracy of the design values. As a result, the sufficient accuracy is achieved as shown in Tabs. II and III. 4) This design procedure can take into account all the conditions considered until now for the designs. 5) The proposed design procedure requires only waveform data ϕ to the simulator. Therefore, the proposed algorithm can be added to any kinds of circuit simulators in principle. Each simulator has advantages and disadvantages. For example, Spice is 1 to 1 times as slow as HEPA-PLUS to obtain the steady-state waveform, but is very useful for understanding the gate-drive problem[31]. The proposed algorithms are also implemented on the simulation part of HEPA-PLUS. The designers can select the simulator according to their policy. B. Features of the developed design tool In this paper, the proposed algorithm is implemented as a design tool using PSpice and OPTIMUS. The developed tool has the following features. 1) It is unnecessary to make a model of the semiconductor device as shown in the design of the class E oscillator. We recognize that the type of the semiconductor device, its driving signals, and their combinations affect the waveforms of class E switching circuit [31]. The proposed design procedure can reflect the effects of them on the design values without modeling of the semiconductor devices. 2) It is unnecessary to modify the source programs when the circuit topology is changed. By using the developed design tool, all the class E switching circuits in [1] [35] can be designed for any specifications. 3) Since OPTIMUS has a function of Graphic User Interface (GUI), the specified conditions can be also given to a computer graphically. As a result, all the design processes are carried out with the aid of the computer dialogically by using the developed design tool. C. Disadvantage of the proposed design procedures There are some disadvantages in the proposed design algorithms. We think, however, these are resolvable problems. 1) The transient analyses for a long interval in Algorithm 2 generate much computation cost. One of the solutions of this problem is using the circuit simulator that is specialized to derive the steady state waveforms quickly. 2) In the proposed algorithms, Newton s method is applied to obtain the design parameters, which requires the approximate solution for its convergence. We recognize that this is a drawback of the proposed algorithm. In this paper, the approximate solutions are derived with our experiences. Here, we would like to emphasize that the approximate solutions are not obtained by try-and-error efforts. There are several techniques to derive the approximate solutions, but we have not implemented them on the software yet. VII. CONCLUSION This paper has presented novel design procedures for the class E circuits allowing the implicit circuit equations. By using the proposed design procedures, all the class E switching circuits for any specifications can be designed with high accuracy even if the circuit equations are implicit. The design examples show the validity and effectiveness of the proposed design procedure. It is expected that the proposed design procedures improve an efficiency of the design of the class E switching circuits dramatically. ACKNOWLEDGMENTS The authors special thanks to Cybernet Inc., Japan and Noesis Solutions NV., Belgium, for their kind help about this research. REFERENCES [1] N. O. Sokal and A. D. Sokal, Class E A new class of high-efficiency tuned single-ended switching power amplifiers, IEEE J. of solid-state circuits, vol. SC-1, no. 3 pp , June [2] F. H. Raab, Idealized operation of the class E tuned power amplifier, IEEE Trans. Circuits Syst.-I, vol. CAS-24, no. 12 pp , Dec [3] M. K. Kazimierczuk and K. Puczko, Exact Analysis of class E tuned power amplifier at any Q and switch duty cycle, IEEE Trans. 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9 JOURNAL OF LATEX CLASS FILES, VOL. 6, NO. 1, JANUARY 27 [14] P. Alinikula, K. Choi, and S. I. Long, Design of class E power amplifier with nonlinear parasitic output capacitance, IEEE Trans. Circuits and Syst.-II, vol. 46, no. 2, pp , Feb [15] A. Mediano P. Molina-Gaud, and C. Bernal, Design of class E amplifier with nonlinear and linear shunt capacitances for any duty cycle, IEEE Trans. Microwave Theory and Techniques, vol. 55, no. 3, pp , Apr. 24 [16] T. Suetsugu and M. K. Kazimierczuk, Analysis and design of class E amplifier with shunt capacitance composed of nonlinear and linear capacitance, IEEE Trans. Circuits Syst-I, vol.51, no.7, pp , July 24. [17] H. Sekiya, I. Sasase and S. Mori, Computation of design values for class E amplifiers without using waveform equations, IEEE Trans. Circuits Syst.-I, vol. 49, no. 7, pp , July 22. [18] P. Reynaert, K. L. R. Mertens and M. S. J. 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Lu, and T. Yahagi, Phase control for resonant dc/dc converter with class DE inverter and class E rectifier, IEEE Trans. Circuits Syst.-I, vol. 53, no. 1, pp , Feb. 26. [35] H. Hase, H. Sekiya, J. Lu, and T. Yahagi, Resonant dc/dc converter with class E oscillator, IEEE Trans. Circuits Syst.-I, vol. 53, no. 9, pp , Sep. 26 [36] Cadence Design Systems Inc. ; /pspice a d/index.aspx [37] Noesis Solutions NV ; /products&doc=optimus [38] Cadence Design Systems Inc. ; /orcad capture/index.aspx 9 Hiroo Sekiya (S 97 - M 1) was born in Tokyo, Japan, on July 5, He received the B.E., M.E., and Ph. D. degrees in electrical engineering from Keio University, Yokohama, Japan, in 1996, 1998, and 21 respectively. Since April 21, he has been with Chiba University and now he is an Assistant Professor at Graduate School of Advanced Integration Science, Chiba University, Chiba, Japan. Since Feb. 28, he has been also with Electrical Engineering, Wright State University, Ohio, USA as a visitng scholar. His research interests include high-frequency high-efficiency tuned power amplifiers, resonant dc/dc power converters, dc/ac inverters, and digital signal processing for wireless communication. Dr. Sekiya is a member of the Institute of Electronics, Information and Communication Engineers (IEICE) of Japan, Information Processing Society of Japan (IPSJ), Society Information Theory and its Application (SITA), Japan, and Research Institute of Signal Processing (RISP), Japan. Toru Ezawa was born in Chiba, Japan, on Jan. 5, He received the B.E. and M.E. degrees in information science from Chiba University, 26 and 28 respectively. Since April 28, he has been Toshiba Corp., Japan. When he was a student, his interests were high-frequency high-efficiency oscillators, dc/ac inverters, and their design tools. Mr. Ezawa is a member of the Institute of Electronics, Information and Communication Engineers (IEICE) of Japan. Yuichi Tanji (S 96 - A 98) received the B.E., M.E., and Ph.D. degrees from Tokushima University, Tokushima, Japan, in 1993, 1995 and 1998, respectively. After graduation, he held Research Associate positions at Sophia University and Kagawa University, and is currently an Associste Professor of the Department of Reliability-based Information Systems Engineering at Kagawa University. His research interests are in circuit simulation, artificial neural networks, and image and signal processing. Dr. Tanji is a member of the Institute of Electronics, Information and Communication Engineers (IEICE) of Japan.