Class D Series Resonant Converter Controlled with FPGA-Based Delta-Sigma Modulator

Transcription

1 Class D Series Resonant Converter Controlled with FPGA-Based Delta-Sigma Modulator Hirotaka Koizumi Department of Electrical Engineering Tokyo University of Science Chiyoda-ku, Tokyo JAPAN littlespring@ieee.org PEDS2009 Abstract A 1st order 1-bit delta-sigma modulator to control a Class D series resonant converter is built with an FPGA. The target reference and the feedback gain are freely chosen. A Class D series resonant converter designed at an operating frequency of 200 [khz] was built and driven by the FPGA-based delta-sigma modulator. Maintaining zero-current switching (ZCS) operation, the output voltage and power were changed from [V], 89.1 [mw] to 8.22 [V], 6.75 [W] in the circuit experiments fed by 20.0 [V] dc-voltage source. The measured power conversion efficiency was from 71.8 [%] to 83.0 [%]. These performances have also been confirmed with MATLAB simulink simulator. In the frequency domain, no specific component was found except the switching frequency and its 2nd harmonic in the observed output voltage. Keywords Class D; resonant converter; delta-sigma modulation. I. INTRODUCTION In series resonant converters, the zero-current switching (ZCS) or the zero-voltage switching (ZVS) can be maintained when the switching frequency is equal to the resonant frequency [1]-[5]. Therefore, the periodical 1-bit output signal of a 1-bit delta-sigma modulator is suitable for regulating the output power/voltage. These days, integrated circuits (ICs) of delta-sigma modulators, which are designed for digital audio amplifiers or switching power converters, are widely in the market [6][7]. For instance, a 1-bit delta-sigma modulator PCM4202[6] is applied to the Class D series resonant converter[5]. However, all the inner parameters of a readymade IC are not always opened. Therefore one has to use an IC as a black box without knowing the primary characteristics. To make it clear the effect of the feedback gain and the order of delta-sigma modulation on the Class D series resonant converter, a 1-bit delta-sigma modulator with adjustable function of the inner parameters is required. In this study, a 1st order 1-bit delta-sigma modulator to control a Class D series resonant converter is built with an FPGA (Cyclone EP1C6T144C8N). The target reference and the feedback gain are freely chosen. The 1-bit output signal is generated to drive a Class D series resonant converter. An experimental circuit was designed and built at the operating frequency of 200 [khz], which was driven by the FPGA-based This study is supported by Japan Society for the Promotion of Science Grant-in-Aid for Scientific Research C II VI Fig. 1. Class D ZCS series resonant inverter vs1 vs2 S1 S2 L is1 is2 vl vc C io vo - Full-wave rectifier S3 S5 Cf S4 Vo RLS6 Delta-sigma modulated Class D series resonant converter. delta-sigma modulator. Maintaining ZCS operation, the output voltage and power were changed from [V], 89.1 [mw] to 8.22 [V], 6.75 [W] in the circuit experiments fed by a 20.0 [V] dc-voltage source, where the measured power conversion efficiency was from 71.8 [%] to 83.0 [%]. These performances have also been confirmed with MATLAB simulink simulator. In the frequency domain, no specific component was found except the switching frequency and its 2nd harmonic in the output voltage observed with the FFT function equipped with the digital oscilloscope. The other components are generally less than -20 [dbv]. II. CIRCUIT DESCRIPTION A Class D series resonant converter is shown in Fig. 1, which is composed of a Class D ZCS series resonant inverter and a full-wave rectifier[1]. Two active switches S 1 and S 2 are alternatively turned on and off; thus the switch voltages v S1 and alternatively take zero and the input voltage V i by a half period as shown in Fig. 2. The square voltage waveform of is given for the L C series resonant circuit. Assuming a high loaded quality factor Q L of the series resonant circuit, the 1443

2 Input - x1 Integrator Z -1 PEDS2009 Quantizer Output x2 x3 x4 G Z -1 Fig. 3. A block diagram of a 1st order delta-sigma modulator. Fig. 2. Waveforms in Class D ZCS series resonant inverter. current becomes sinusoidal. When the resonant frequency is designed to be equal to the switching frequency, ZCS is achieved. Besides, in the case when the switching frequency is higher than the resonant frequency, ZVS is achieved with the intrinsic body diode of the MOSFET, which leads to high efficient power conversion with low switching noise [1]. As shown in Fig. 2, the current flows through S 1 and S 2 as i S1 and i S2 by a half period. The switching transition occurs at the zero current instant. When the inverter is loaded with a full-wave rectifier, the load resistance R L performs as an equivalent resistance R i =8R L /π 2 [1]. Through the diodes S 3 to S 6, a dc-output voltage is obtained, which is approximately 0.5V i [1]. III. REGULATION METHOD As a regulation method, pulse density modulation (PDM) has been getting more popular as the digital control has been spreading. In PDM the switch-on term and the switch-off term is periodically changed at the fixed switching frequency. Therefore, switching condition (ZCS/ZVS) is maintained [2]- [4] when PDM is applied to resonant power converters which satisfy the condition that the resonant frequency is equal to the switching frequency. Two drawbacks of PDM are the subharmonics and the discontinuity of the output power/voltage, which are caused by predetermined switching patterns. The delta-sigma modulation [7], which doesn t need any switching patterns, is effective for these problems. Fig. 3 shows a block diagram of a 1st order 1 bit delta-sigma modulator [7]. A reference x 1 is given as an input signal. The signal x 2 to the integrator takes x 1 G to x 1 G, because the output value of the quantizer x 4 is -1 for a negative value, 1 for zero or a positive value. While x 4 is 1, the switches S 1 and S 2 of the converter shown in Fig.1 periodically repeat normal switching. While x 4 is -1, S 1 stays off, and S 2 stays on, then the amplitude of the current is getting smaller during this term. The output power/voltage can be controlled with the damping phenomenon almost continuously with low subharmonics [5]. This is obvious by Fig. 3, x 4 is affected by the structure of the delta-sigma modulator and the feedback gain G, which are not always opened when one uses a ready-made delta-sigma modulation IC. To make it clear how the inner parameters and the structure of a delta-sigma modulator affects the performance of a resonant converter controlled with the deltasigma modulator, an FPGA-based delta-sigma modulator is needed. In this study, a 1st order 1-bit delta-sigma modulator is built with an FPGA. A screen copy of a designed file of the 1st order 1-bit delta-sigma modulator with Altera Quartus II is shown in Fig. 4. The fundamental structure is modelled after the block diagram in Fig. 3. For the parameters x 1 to x 3,andGx 4, 12-bit integers are assigned, where the 1st bit shows plus/minus. The output signal x 4 has 1 bit. This time, the input reference x 1 is numerically given as an integer. Different from the model of Fig. 3, x 4 takes 0 for a negative value of x 3, otherwise 1. Then, Gx 4 takes G for x 4 =1otherwise G. Whenx 1 = G, x 4 keeps 1. When x 1 = G, x 4 keeps 0. Between G and G, the reference x 1 can be freely chosen. The larger G leads to finelytuned regulation. The fundamental clock 200 [khz], which is equal to the switching frequency of the resonant converter, is made from 30 [MHz] from the original clock of the FPGA. A small delay is given between the clocks for each block. Considering the calculation time, the gate driving signals for S 1 and S 2 are given through an AND gate from x 4 and a delayed clock signal. IV. EXPERIMENTAL RESULTS A Class D series resonant converter is designed at the switching frequency f s = 200 [khz]. The followings are given as a circuit design; the input voltage V i = 20.0 [V], the load resistance R L =10[Ω], the loaded quality factor Q L = 5, and the switching frequency f s = 200 [khz] which is equal to the resonant frequency. The resonant inductance L and capacitance C are calculated by L = Q L R i /ω s, and C =1/ωsL 2 =1/ω s Q L R i,whereω s =2πf s is a switching angular frequency, and R i =0.81R L is an equivalent resistance of the rectifier [1]. The designed and measured values of 1444

3 x 1 x 2 x 3 x 4 Gx 4 Fig. 4. A designed block diagram of the FPGA-based 1st order 1-bit output delta-sigma modulator. TABLE I THE DESIGNED AND MEASURED VALUES OF THE CIRCUIT ELEMENTS. L [µh] C [nf] R L [Ω] Designed Measured ESR[mΩ] Output voltage [V] the circuit elements are shown in Table I, where ESR means the measured equivalent series resistance. A 470 [μf] filter capacitor is used for C f. Its measured values were 430 [μf] with ESR of 185 [mω] at 200 [Hz] and 4.48 [μf] with ESR of 126 [mω] at 200 [khz]. MOSFET s IRF510 are used for the switches S 1 and S 2. Schottky barrier diodes SR340 (Rectron) are used for the switches S 3 to S 6. Using these devices, a Class D series resonant converter was built and tested. The driving signals were given from the FPGA-based delta-sigma modulator (Cyclone EP1C6T144C8N), where the feed-back gain G = 15 was set. The reference value x 1 was changed from -15 to 15. The relationship between the reference x 1 and the output voltage is shown in Fig. 5. In these tests, the output voltage was changed from [V] at x 1 = -13 to 8.22 [V] at x 1 = 15. At x 1 = -15, was 0. A linear approximation =0.264 x can be drawn in Fig. 5. Corresponding to the output voltage, the output power was changed from 89.1 [mw] to 8.22 [W] at [khz], where the measured power conversion efficiency was 71.8 [%] and 83.0 [%]. The four observed waveforms are shown in Fig. 6, where is the gate driving voltage for S 2.Asshownin Fig. 6, normal switching was repeated for x 1 = 15. Figs. 6 to were respectively observed when x 1 =7,0,and -7 were given. While the complex driving patterns generated by the delta-sigma modulator were observed in Fig. 6 and, a periodical driving pattern was also observed as shown in Fig. 6. In Fig. 6 the current flowing through the resonant circuit crosses over zero at the switching instant for Fig Reference value 15 The relation ship between the reference value and the output voltage each waveform. A delta-sigma modulator and the Class D series resonant converter was built with MATLAB Simulink under the same designed conditions to the circuit experiments. Giving the same feed-back gain G and the reference x 1, the current,the output voltage, and the switch voltage were calculated as shown in Fig. 7. Judging from, the same driving patterns to the FPGA-based delta-sigma modulator were generated, which mean that the FPGA-based deltasigma modulator operated as intended. The other calculated waveforms are also in accordance with the experimental results. In each waveform, the current crosses over zero at the switching instant. In the circuit experiments, the output voltage was also observed with the FFT function equipped with the digital oscilloscope. Fig. 8 shows the spectra corresponding to Fig. 6 to. In Fig. 8 and, the observed spectra are 1445

4 lower than the spectrum in Fig. 8. In Fig. 8 which is corresponding to Fig. 6 and Fig. 7, more spectra are observed than the other three. However each amplitude is not higher than the spectrum observed in Fig. 8. Common to all spectra, no specific component was found except for the switching frequency f s at 200 [khz] and its 2nd harmonic. The other components are generally less than -20 [dbv]. V. CONCLUSION A 1st order 1-bit delta-sigma modulator to control a Class D series resonant converter has been built with an FPGA. The reference value and the feedback gain are freely chosen, which are important for the future research for evaluating the performance of resonant converters controlled with a deltasigma modulator. A Class D series resonant converter designed at operating frequency of 200 [khz] was designed, built, and driven by the FPGA-based delta-sigma modulator. With a maintaining ZCS, high-efficiency and wide-range dc/dc power conversion have been confirmed in circuit experiments. These performances have been also confirmed in the simulation with MATLAB simulink simulator. In the frequency domain, no specific component was found, except for the switching frequency and its 2nd harmonic in the observed output voltage. REFERENCES [1] M. K. Kazimierczuk, D. Czarkowski, Resonant Power Converters, Willey-Interscience, N.Y [2] H. Fujita, and H. Akagi, Pulse-density-modulated power control of a 4 kw, 450kHz voltage-source inverter for induction melting application, IEEE Trans. Ind. Appl., vol. 32, no. 2 pp , Mar./Apr [3] H. Koizumi, K. Kurokawa, and S. Mori, Analysis of Class D inverter with irregular driving patterns, 1-bit delta-sigma modulator to control IEEE Trans. on Circuits and Syst., Part-I: Regular Papers, vol. 53, no. 3, pp , Mar [4] Nam-Ju Park, Dong-Yun Lee, Dong-Seok Hyun, A power-control scheme with constant switching frequency in Class-D inverter for induction-heating jar application, IEEE Trans. Ind. Elec., vol. 54, no. 3 pp , June [5] H. Koizumi, Delta-sigma modulated Class D series resonant converter, in Proc. IEEE Power Electronics Specialists Conference, 2008, pp , June [6] Texas Instruments Incorporated, PCM4202EVM User s Guide, [Online]. Available: [7] K. Masuda, T. Hayase, S. Satoh, 1 bit audio, Sharp Tech. Report, vol. 77, pp , Aug (in Japanese). Fig. 6. Observed waveforms: x 1 = 15, x 1 =7,x 1 =0,and x 1 = -7. Vertical 10 V/div for,20v/divfor, 2 A/div for in and, 1 A/div for in and, 10 V/div for in and, and 5 V/div for in and ; horizontal: 5 µsec/div in, 25 µsec/div in to. 1446

5 Fig. 7. Calculated waveforms with MATLAB Simulink simulation; from the top, inverter current, output voltage, and switch voltage,x 1 = 15, x 1 =7,x 1 =0,andx 1 =-7. Fig. 8. Spectra of the output voltage waveforms observed in frequency domain with the FFT function of the digital oscilloscope: vertical 20 dbv/div, horizontal: 500 khz/div. x 1 = 15, x 1 =7,x 1 =0,andx 1 =