Analysis and design of Class-E power amplifiers at any duty ratio in frequency domain

Transcription

1 Analog Integr Circ Sig Process () 67:49 56 OI.7/s Analysis and design of Class-E power amplifiers at any duty ratio in frequency domain Tianliang Yang Junrui Liang Chunyu Zhao ayue Chen Received: 8 January 9 / Revised: 4 October / Accepted: November / Published online: 7 ecember Ó Springer Science+Business Media, LLC Abstract This paper presents a design method for Class- E power amplifiers based on the analysis of the load impedance in the frequency domain. The analytical expressions of the design parameters are derived as functions of the duty ratio and angular frequency x of the gate driven voltage of the switch. According to the analysis, for an optimal Class-E amplifier that meets both the zero-voltage switching (ZVS) and the zero-derivative switching (ZS) conditions, the increase of the duty ratio results in the decrease of the C input resistance, and this consequently increases the input power and decreases the total efficiency. Two design procedures for different design purposes are discussed under three cases with different duty ratios, i.e. =.5,.5 and.75. The simulation and experimental results of these cases agree well with the theoretical ones. Keywords Class-E power amplifier Zero-voltage switching (ZVS) Zero-derivative switching (ZS) Introduction The Class-E power amplifier introduced by N.O. Sokal and A.. Sokal [] is widely used in the applications of C AC, C C power conversion [] and RF field [3] due to its high efficiency and simple circuit topologies. However, it is a difficult task to calculate the accurate T. Yang J. Liang C. Zhao. Chen (&) epartment of Instrument Science and Engineering, School of Electronics, Information and Electrical Engineering, Shanghai Jiao Tong University, Shanghai 4, People s Republic of China dychen@sjtu.edu.cn parameters of a Class-E power amplifier through solving the a binary quadratic differential governing equations directly, that some reasonable assumptions, i.e. high value of the load quality factor Q and large value of the choke coil, are normally included in the design analysis. Under these assumptions, a number of design methods of the Class-E amplifier have been developed [4 6]. Kazimierczuk and Puczko [5] presented their design tables on some circuit parameters as functions of Q by Laplacetransform and numerical solution. N.O. Sokal [6] proposed a numerical table, which is similar to that in [5], and concluded some fitted expressions of each component with respect to Q. It is applicable to design a Class-E amplifier according to the tables provided in [5, 6]. However, these tables cannot intuitively explain the characteristics of the Class-E amplifier, e.g. the phase difference between the output voltage and the driving square wave. Suetsugu [7] used the single parameter of / (the initial phase of the load current) to analyze the off-nominal Class-E at 5% duty ratio, and extented his work by analyzing a design case at any duty ratio [8]. Their researches indicate that the main circuit parameters are determined by /, not by Q. In this paper we present a frequency-domain method for the analysis and design of the Class-E amplifier at any duty ratio. In this method, with the same preliminary assumptions as [5], the steady-state current and voltage waveforms of the Class-E amplifier can be determined by the zerovoltage switching (ZVS) and zero-derivative switching (ZS) conditions. By analyzing the steady-state switch voltage and output current, the load impedance Z is expressed as a function of the duty ratio and angular frequency x of the gate voltage. In addition, the C input resistance, the minimum loaded quality and the power loss on the switch-on resistance can be expressed as functions of. Based on these analyses, two design procedures

2 5 Analog Integr Circ Sig Process () 67:49 56 for different purposes with =.5,.5 and.75 are presented. (a) i o θ X θ X i o I I θ k θ k Voltage and current waveforms The circuit topology of a basic Class-E amplifier is shown in Fig., with the following assumptions [5, 7]. () The choke inductor L RFC is lossless and its inductance is large enough to neglect its ripple current. () The MOSFET is an ideal switch component (turning on and off instantly), so that it has zero on-resistance and infinite off-resistance. (3) The loaded quality factor Q of the output resonant network is high enough so that the output current can be regarded as a pure sinusoid. If the sinusoidal output current i o and the gate voltage v g in the circuit are determined, under the required conditions of ZVS and ZS, the waveforms of the current and voltage at any point may be obtained with the following analyses. According to the Assumption 3, the steady-state output current i o is a sinusoid, as shown in Fig. (a), which can be described as i o ðhþ ¼ I m sin h ðþ where I m is the current amplitude and h = x t is the phase angle with the angular frequency x. The analyses of the circuit are confined in any one cycle k of i o (h), h [ [( k - )p, (k? )p). Considering the ZVS condition, at the switch-off duration, the shunt capacitance C should be charged and then discharged to achieve i C = as well as v C = when the switch turns on. In addition, to satisfy the ZS condition, the current through the switch, i S, should be zero when the switch turns on. According to the Kirchhoff s current law, both i C = and i S = can and only can be achieved if the output current i o equals to the supply current I, i.e. i o = I, (see Fig. ). This condition can be satisfied at two phase angles h k (where i o slopes up to cross I ) and h k (where i o slopes down to cross I ), as shown in Fig. (a). Since the shunt capacitance charges (i o \ I ) v g I i S V L RFC C i C + v S _ C L Fig. Basic circuit of the Class-E amplifier R i o + v o _ (b) (c) then discharges (i o [ I ) in a switch-off duration, the switch must turn on at h k due to i o [ I ahead of this turnon point. The angle phase difference between h k and ( k - )p is defined as h X ¼ h k ðk Þp: ðþ From (), the supply current I equaling to i o at h k can be expressed as I ¼ I m sin h k ¼ Im sinðh X Þ: ð3þ The gate driven voltage v g, as shown in Fig. (b), is a periodic square wave with the duty ratio of. Therefore, the phase duration of the switch-on is h ¼ p ð4þ and the phase duration of the switch-off is h F ¼ pð Þ: ð5þ The center radian in the switch-off duration h kc expressed as h kc S i (d) (e) i C v S v gθ A (k ) π kπ ( k + ) π can be ¼ ð k Þp h X þ h : ð6þ When the switch is on, the current through it (see Fig. (c)) can be expressed as i S ðhþ ¼ ½I I m sinðhþšsðhþ ð7þ where sðhþ ¼ h k \h h k þ h h k h F\h h k θ F θ kc A Fig. Steady-state voltages and currents of an ideal Class-E amplifier. a Input and output current. b Gate voltage across the switch. c Current through the switch. d Current through the shunt capacitance. e rain voltage across the switch.

3 Analog Integr Circ Sig Process () 67: When the switch is off, the current through the shunt capacitance, as shown in Fig. (d), can be expressed as i C ðhþ ¼ ði I m sin hþ½ sðhþš: ð8þ According to the ZVS condition, in the switch-off duration, the input charge to the shunt capacitance C, which is proportional to the area of A, and the discharged charge, which is proportional to the area of A, are equal, i.e., A = A, which can determine the relationship between h X and h as follows. As shown in Fig. (d), A is the area under i C (given in (8)) over the duration [h k þ h, h k ]: A ¼ Z h k h k þh ¼ I ðp h X þ h ji I m sin hjdh ÞþI m ½cos h X þ cosðh X h ÞŠ and A is the area above i C over the duration [h k, h k ] A ¼ Z h k h k ji I m sin hjdh ¼ I m cos h X I ðp h X Þ: ð9þ ðþ Thus, comparing (9) and () with their equivalent relationship, the difference on the angle phase h X can be expressed as a function of the angle phase of switch on h : h X ¼ tan cos h : p h þ sin h ðþ According to (), the relationship between the ratio of I /I m = sin h X (from (3)) and the switch duty ratio = h /p (from (4)) can be obtained and shown in Fig. 3. From Fig. 3, as increases, it is obvious that I /I m increases. This results in the decrease of the output current amplitude I m for a constant supply current I. Consequently, due to the decrease of I m, the load resistance R increases to sustain the relationship that the output power equals the input power. uring the switch on, the drain voltage of the switch v S keeps zero, while, during the switch off, it increases from zero in the charge process (h k þ h \h h k ) and it falls to zero in the discharge process (h k \h h k ), as shown in Fig. (e). 3 Circuit parameters The load impedance Z, the C input resistance R C, the minimum quality factor of the load branch Q Lmin, the input power P in, the output power P out, and the collect efficiency g c are analyzed in terms of the switch-on interval h as follows. The load branch network consists of a resistance R, a capacitance C and an inductance L. The impedance of the load branch network at the resonant frequency x can be expressed as Zðx Þ ¼ R þ jxðx Þ ðþ where Xðx Þ ¼ x L =x C. Z(x ) can also be calculated from the frequency-domain relationship between the switch voltage v C and the output current i o, which is Zðx Þ ¼ V Cðx Þ ð3þ I o ðx Þ where V C (x ) and I o (x ) are the Fourier coefficients of v C (t) and i o (t) atx. Considering the average of i C in a cycle is zero, V S (jx) is V S ðjx Þ ¼ I CðjxÞ jxc where the Fourier transfer function of i C is ( X sin ph F I C ðjxþ¼i m sinh X e jph kc p p¼ þ sinðp Þh F p e j½ðp Þh kc p Š þ dðx px Þ ðpþþh sin F ½ pþ e j ð Þh kc þp pþ ð4þ ) Š ð5þ where d(x) is the irac delta function, and p is an integer. From (4), let h c = h / - h X, the C component of v C is Fig. 3 Ratio of I /I m with respect to the duty ratio V S ðþ ¼ where I m px C a ð6þ

4 5 Analog Integr Circ Sig Process () 67:49 56 a ¼ h F h c sin h X þh c sin h sin h c þ h F cos h þ sin h cos h c : ð7þ And the Fourier coefficients of v C at the fundamental frequencies x and -x are V S ðx Þ¼ I m px C jsinh X sin h e jh c þ sinh e jh c þ h F ð8þ ω RC ω X(ω )C and V S ð x Þ¼ I m px C j sin h X sin h ejh c þ sin h ejh c þ h F : ð9þ Since the choke coil L RFC is lossless (Assumption ), the supply voltage V is equal to the C component V S () in (6), which is V ¼ I m px C a: ðþ And the voltage component at x can be expressed as v SF ðþ¼v t S ðx Þe jxt þ V S ð x Þe jxt : ðþ The Fourier coefficient of the output current i o (t) (see ()) is I o ðx Þ¼ I m j : ðþ Substitution of (8) and () into (3) gives the loadbranch impedance Z(x )as Zðx Þ ¼ px C fb þ jcg ð3þ where b ¼ ½sin h X þ sinðh h X ÞŠ ð4þ and c ¼ h F cos h X þ sin h cos h c : ð5þ Comparing the real and imaginary terms in () and (3) respectively, the circuit parameters in the load branch network can be determined: R ¼ px C b ð6þ and Xðx Þ ¼ px C c: ð7þ From (6) and (7), the non-dimensional design parameters x RC and x X(x )C as functions of the duty ratio are calculated and shown in Fig. 4. The maximum..4 value of x RC is.5 at =.35. However, the Class-E amplifier cannot meet both ZVS and ZS conditions if x RC is larger than.5. If x RC is between and.5, there are two duty ratios will satisfy (6) and (7), so the Class-E amplifier can meet both ZVS and ZS conditions at those two duty rations. However, the output power and components except R and C are not equal at these two duty ratios. The C input resistance of the Class-E amplifier, R C,is important to analyze the input current and input power. Combining (3), () and (6) gives R C as R C ¼ V ¼ ar : ð8þ I b sin h X From (8) the relationship between R/R C and can be obtained, as shown in Fig. 5. It can be found that R C decreases as increases, and the main values of equivalent C input resistance R C and the input power P in with respect to duty ratio are shown in Table. The load quality factor Q L is defined as.6.8 Fig. 4 x RC and x X(x )C with respect to the duty ratio R / R C Fig. 5 R/R C with respect to duty ratio

5 Analog Integr Circ Sig Process () 67: Table R C, P in and P out with respect to duty ratio Parameters Q L ¼ x L R : ð9þ Since the parameter of capacitance C is nonnegative, from (6), (7) and (9), the load quality factor Q L is obtained to satisfy the inequality in terms of b and c as Q L [ X ð x Þ ¼ c R b :.5.6 R C?.73R R.5R P in.58p a P a P a P out.58p a P a P a a P = V /R Minimum load factor quality Fig. 6 Minimum load quality factor with respect to the duty ratio ð3þ Figure 6 shows the minimum load quality factor Q Lmin as a function of the duty rate. Q Lmin is a monotone decreasing function of. However, as the assumption of high Q cannot be satisfied, a reasonable error exists between Q Lmin and the actual minimal load quality factor. The minimal quality factor of the load network Q Lmin reflects the practical one. Hence, it needs to set a large load quality factor Q L when the duty ratio is small. The input power and output power are determined by the following derivations. From () and (6), the amplitude of the output current can be expressed as I m ¼ bv ar : ð3þ Combining (3), (), (6) and (3) gives the input power: P in ¼ V I ¼ b sin h X V a R : ð3þ Combining (), (6) and (3) gives the output power: P out R / V P out ¼ I m R ¼ b V a R : ð33þ Figure 7 shows P out R/V with respect to. P out increases as increases. The main values of P out are shown in Table. The collect efficiency is g c ¼ P out b ¼ ¼ : P in a sin h X ð34þ However, the efficiency is not % due to the resistance of every component of the Class-E amplifier. It is a tough work to calculate the accurate component parameters and efficiencies of a Class-E amplifier when the equivalent series resistance (ESR) is considered. It is reasonable to calculate the efficiency according to the results from the ideal analysis. Compared with the equivalent series resistance (ESR) of other components of Class-E amplifier, the on-resistance of the switch r on is the main component contributing to the power loss. According to (3), the average power of r on is P ron ¼ p Fig. 7 P out R/V hz k þh h k with respect to duty ratio i S ðhþr ondh ¼ b R on p a R dv R where d ¼ h þ sin h X þ sin h X ½cos h X cosðh X h ÞŠ ½ 4 sin h X sin ðh X h ÞŠ From (3) and (35), the ratio of P ron to P in is g ron ¼ P r on ¼ bdr on P in pa sin h X R : ð35þ ð36þ ð37þ Figure 8 shows g ron R=r on with respect to the duty ratio. g ron increases as increases. The ratio of power loss

6 54 Analog Integr Circ Sig Process () 67:49 56 η ron R / R on Table Calculated parameters of the Class-E amplifier at =.5,.5 and.75 L (lh) C (nf) L (lh) C (nf) Fig. 8 g ron R=r on with respect to duty ratio in r on over the input power P in increases as increases, consequently, the efficiency decreases. 4 esign procedure Two design procedures are provided with the following design requirements: () The C supply voltage V is required. () The output power P out and the collect efficiency g c are required. In each procedure, the given parameters are the operating frequency f, switch ratio, load resistance R, load quality Q. Steps for the procedure (): () Calculate the phase difference h X by (), and then calculate a, b, c, d with h and h X ; () Calculate L by (9) in terms of the given parameters R, Q, f; (3) Calculate the shunt capacitance C by (6); (4) Calculate C by (7); (5) Calculate choke coil by the formula L RFC = (p / 4? )R/f [9]. (6) Calculate the input power and efficiency with the C supply voltage V by (3) and (37), respectively. Steps for the procedure (): Steps ( 5) are the same as those of the procedure (). (7) Calculate the maximum switch-on resistance of r on with the ratio g ron ¼ g c by (37), and then select a MOSFET with r on smaller than the maximum one. Calculate the supply voltage V by (3) where P in = P out /g c. 5 Simulations and experiments From the design procedure () presented in Part IV, given the circuit parameters f = MHZ, V = 6V,R= X and Q =, the design parameters of the Class-E amplifier at three duty ratios, i.e. =.5,.5 and.75, are calculated and shown in Table. With the three sets of parameters, the circuit shown in Fig. was simulated with PSpice. The MOSFET was substituted by an switch component IRF 5, which was driven by a square wave generated by the component Vpulse. The Vpulse was set to 6 V amplitude, zero rise time, zero fall time and zero delay time. Substituting R = X and r on =.54 X (per data sheet) into (37), the calculated collect efficiencies with respect to were calculated and compared with simulated ones, as shown in Fig. 9. The simulated results agree well with the calculated ones when is between. and.8. However, this agreement cannot be obtained at very small or large. In the simulation the voltage v S and v o take some time from their transient states to their steady states. The voltage waveform in the period between 98 and ls is shown in Fig. (a c). The values of the main parameters in the simulation are shown in Table 3. However, there are some differences due to the switch-on resistance r on. The differences are smaller when duty ratio is.5 than these when is.5 or.75. In the experiment the MOSFET IRF 5 was used as the switch device, and the driving square waves were gained from ATMEGA 6 microcontroller. The choke coil was set η ( % ) Theory Simulation Fig. 9 Comparison of the simulation and theoretical values of the efficiency as function of the duty ratio

7 Analog Integr Circ Sig Process () 67: Fig. Simulated and experimental waveforms of the switch voltage v s and the output voltage v o. a Simulation result at =.5. b Simulation result at =.5. c Simulation result at =.75. d Experimental result at =.5. b Experimental result at =.5. c Experimental result at =.75 v S & v o time (μs) time (μs) time (μs) (a) (b) (c) v S & v o v o t / T (T = μs) (d) t / T (T = μs) (e) t / T (T = μs) (f) Table 3 Calculated, simulated and experimental results of the Class- E amplifier at =.5,.5 and.75 Parameters Calculated Simulation Experimental.5 V S (V) V o (V)..3. I (ma) a g (%) V S (V) V o (V) I (ma) a g (%) V S (V) V o (V) I (ma) a g (%) a Average value of the input current to be 3 lh (approximately two-times larger than the calculated one) to reduce the impulse current through the switch when the power turns on. The equivalent series resistance (ESR) of the inductor L in the loaded branch was.6 X, and the other components were taken as ideal components. The voltage v S and v o in the experiment are shown in Fig. (d f). The values of the main parameters are shown in Table. Considering the ESR of each component, some differences among the experimental, simulation and calculated results will exist. 6 Conclusion This paper presents a frequency-domain method for the analysis and design of Class-E amplifiers at any duty ratio. According to the design analysis, as increases, the C input resistance decreases, and consequently the output power increases while the collect efficiency decreases. Based on these consequences, two design procedures for different purposes are presented with the design examples at =.5,.5 and.75. The simulated and experimental results show that the differences of the switch voltage, output voltage, and the input and out power are less than %. References. Sokal, N. O., & Sokal, A.. (975). Class E, a new class of high efficiency tuned singled-ended switching power amplifiers. IEEE Journal of Solid-state Circuits, SC-(3), Sekiya, H., Nemoto, S., Lu, J. M., & Yahagi, T. (6). Phase control for resonant C-C converter with Class-E inverter and Class-E rectifier. IEEE Transactions on Circuits and System, 53(), Hasani, J. Y., & Kamarei, M. (8). Analysis and optimum design of a Class-E RF power amplifier. IEEE Transactions on Circuits and Systems I-Regular Papers, 55(6), Raab, F. H. (977). Idealized operation of the Class E tuned power amplifier. IEEE Transactions on Circuits and Systems, CAS- 4(),

8 56 Analog Integr Circ Sig Process () 67: Kazimierczuk, M. K., & Puczko, K. (987). Exact analysis of Class E tuned power amplifier at any Q and switch duty cycle. IEEE Transactions on Circuits and Systems, CAS-34(), Sokal, N. O. (). Class-E RF power amplifiers. QEX, Suetsugu, T., & Kazimierczuk, M. K. (6). esign procedure of Class-E amplifier for off-nominal operation at 5% duty ratio. IEEE Transactions on Circuits and Systems, 53(7), Suetsugu, T., & Kazimierczuk, M. K. (7). Off-nominal operation of Class-E amplifier at any duty ratio. IEEE Transactions on Circuits and Systems, 54(6), Kazimierczuk, M. K., & Czarkowski,. (995). Resonant power converters. New York: Wiley. Tianliang Yang received the B.S. degree in Electrical Engineering and M.S. in Mechatronics Engineering from Nanchang Hangkong University, Nanchang, China, in 3 and 6, respectively. Currently he is working toward the Ph.. degree in Electrical Engineering at Shanghai Jiao Tong University. His research interests include power amplifier, dc/ dc converters, wireless power and data transfer, implantable electronics and smart telemetry. Chunyu Zhao received the Ph.. degree from Shanghai Jiao Tong University, Shanghai, China, in. Currently he is an Associate Professor of the epartment of Instrument Science and Engineering at Shanghai Jiao Tong University. His research interests include prosthetic devices, power amplifier, dc/dc converters and inductive links, neural-electronic interfaces and wireless biotelemetry. ayue Chen received the Ph.. degree from Shanghai Jiao Tong University, Shanghai, China, in 989. Currently, Prof. Chen is the irector of Institute of Intelligent Mechatronics Research of Shanghai Jiao Tong University. His research interests include prosthetic devices, neural-electronic interfaces, implantable electronics, inductive link, and smart telemetry. Junrui Liang received the B.S. and M.S. degrees in Instrumentation Engineering from Shanghai Jiao Tong University, Shanghai, China, in 4 and 7, respectively, and the Ph.. degree in Mechanical and Automation Engineering from the Chinese University of Hong Kong, Hong Kong, China, in. His research interests include piezoelectric energy harvesting, Class-E power amplifier, and wireless power transmission.