APPLICATIONS OF MOATS, VOLTAGE REGULATOR MODULES, AND DECOUPLING CAPACITORS TO SUPPRESS DELTA-I NOISE

Transcription

1 APPLICATIONS OF MOATS, VOLTAGE REGULATOR MODULES, AND DECOUPLING CAPACITORS TO SUPPRESS DELTA-I NOISE Chun-Te Wu 1, Kuo-Chiang Hung 2, Ding-Bing Lin 2, and Feng-Nan Wu 2 1 Da-Yeh University (DAYEH), NO.112, Shanjiao Rd., Dacun, Changhua, Taiwan 51591, R.O.C. 2 National Taipei University of Technology (NTUT), No.1, Sec. 3, Jhongsiao E. Rd., Taipei City 106, Taiwan (R.O.C.) TEL:+(886) Ext FAX:+(886) samuel@mail.dyu.edu.tw, HungKuoChiang@gmail.com, dblin@.ntut.edu.tw, s @ntut.edu.tw Abstract-This study presents a novel method for reducing delta-i noise and preventing noise from interfering with the state of an integrated circuit (IC) component when driving signals switch between high and low. Many methods have been utilized to reduce delta-i noise. Some of these markedly increase product cost; some only solve the power integrity to a limited extent. To overcome the shortcomings of these methods, this study presents a novel approach that cuts down the costs and solves power integrity issues. The proposed method improves power integrity by isolating the power/ground plane in combination with few de-caps, instead of using a massive number of capacitors to create a wall around sensitive ICs. Simulation and measurement results demonstrated that the proposed

2 method is easily implemented and effectively improves power integrity issues. Key Words: power integrity, delta-i noise, decoupling capacitor, voltage regulator module I. INTRODUCTION Computer systems have become versatile workstations, creating a need for many different capabilities on printed circuit boards (PCBs), involving both digital and analog circuits. Therefore, the distance between components has decreased, and signal integrity (SI) and power integrity (PI) issues have become increasingly important. Furthermore, the need for low driving voltage and high output power is a typical trend in present-day computer systems. These requirements induce the critical problems of simultaneous switching noise (SSN), ground bounce noise (GBN), and delta-i noise for power integrity (PI) issues. Low-power voltage levels reduce the noise margin of sensitive components. Consequently, the influences on power voltage between power planes and ground planes cannot be neglected. Transient currents in ICs flowing through holes or circuit pins generate delta-i noise between power and ground planes. This noise produces fault states in ICs [1] [5]; thus, the stability of computer systems will be destroyed by delta-i noise. In recent years, many structures have been developed to minimize the effect of delta-i noise and to retain stable power voltage on the power plane [6] [11]. Numerical analyses and measurement results have resulted in many worthy achievements [12] [16]. However, these studies have overlooked the effects of the voltage regulator module (VRM), which can improve the stability of a power voltage level influenced by delta-i noise at low

3 frequencies. Additionally, the position of the VRM affects the resonant frequency caused by the 2D resonators formed by power/ground planes. Consequently this study discusses the impact of the VRM, and the effects of the VRM on suppressing delta-i noise at low frequencies. These effects were confirmed by simulation and measurements. In addition to delta-i noises, the PI quality is adversely affected by the resonant effect. A printed circuit board (PCB) has a parallel-plate waveguide structure formed by the power/ground planes; its resonant frequencies are excited by the switching currents of ICs, which destroys the PI [17]. The most popular method of solving the PI problem is to use many decoupling capacitors (de-caps) on the PCB, forming a capacitor wall around the sensitive component. This method can maintain a steady voltage on the power plane [18] [20]; however, it increases the PCB cost. This study presents a novel structure that reduces the PCB cost by using only a few de-caps and a VRM combined with a moat to attain a quality that is better than that of a capacitor wall. II. GEOMETRIC STRUCTURES AND DELTA-I NOISE ISOLATION A. Structure of the Tested Board Fig. 1(a) presents a simple four-layer test board [21]. A power plane and ground plane are placed in the inner two layers. Two ICs are placed on the top layer with power and ground pins connected to the power and ground planes, respectively. When the switching currents of IC N flow through the vias, these switching currents will excite electric and magnetic fields between the power and ground planes the so-called delta-i noise. Delta-I noise influences the power voltage level on the power plane and destroys the

4 stability of IC N and IC M (Fig. 1(b)). Although a stable power voltage is applied between the power and ground planes, the voltage level is influenced when switching currents surge into the power and ground planes. In terms of frequency, power voltage means the operating frequency is zero, delta-i noise means there is a high frequency signal, and the PI and delta-i will not interfere with each other. However, when the ICs switch on/off, the transient power voltage will not attain a steady state, which means the delta-i noise will influence the power voltage level in the transient state. When analyzing the PI, the first (lowest) resonant of the power and ground planes is the most important factor. If there are any exciting sources with a 3dB spectrum that exceeds the first resonant frequency, the resonant effect will collapse the PI. Thus, the design rule is to shift the first resonant frequency outside the effective operating spectrum. Since digital signals have infinite spectrums, preventing a switching signal from exciting resonant modes is impossible; however, due to the conductor and dielectric losses of the PCB, if the 3dB spectrum of excitation is less than the first resonant mode, the PI will not experience any serious problems. Fig. 2 presents three simplified test boards that were utilized to determine the effects of delta-i noise. The boards are cm and 0.4 mm thick. Their dielectric constant is 4.4. Fig. 2(a) presents the integral power and ground planes of the first board. The top plane represents the power plane and the bottom plane represents the ground plane. Port 1 represents a pair of power and ground pins for IC 1, ports 2 and 3 represent the pins of IC 2 and IC 3, respectively; S21 and S31 represent the noise received at ports 2 and 3 with respect to source drives at port 1. Port 1 is located at (5 cm, 4 cm), port 2 at (2 cm, 4 cm), and port 3 at (8 cm, 6 cm).

5 Fig. 2(b) presents the second board. The delta-i noise inside the inner power island is totally isolated when the high-speed IC switches on, which means the outer plane is not impacted when high-speed circuits operate on the inside island. However, the power voltage is also blocked by this structure; thus, this structure is impractical. However, this case represents the optimal situation for blocking delta-i noise inside the inner plane. In this case, a 4 4 cm island is surrounded by a moat that prevents noise from propagating to ports 2 and 3 when port 1 switch on/off. This moat is 1 mm wide and ports 1, 2, and 3 are placed at the same locations as in case 1. In case 3, all of the parameters are the same as those in case 2 except that a bridge is lifted to supply the power voltage from the outer plane. This bridge is 6 mm wide [26] [31]. B. The Isolation of the Delta-I Noise Measurement and simulation results showed that ports 2 and 3 were markedly affected by port 1 (Fig. 3). Two significant problems must be discussed. First, delta-i noise decreases the quality of the power voltage at a low frequency when no VRM exists on the power/ground planes. Second, when delta-i noise propagates between two-parallel planes, it excites several resonant modes. The fundamental resonant mode of the integral power board is TM 10 (TM 01 ) at GHz. The resonant frequency of the integral board can be derived using Eq. (1). f mn 2 2 c m n = + 2 ε a b r (1) Measurements were conducted by a network analyzer 8720C, and simulation results were obtained using a 3-D simulator (HFSS) and PowerSI.

6 Fig. 3 presents measurement data for the tested board. Experimental data indicate that case 2 suppresses delta-i noise by isolating the power/ground islands. Both S21 and S31 are < 40dB, which means the delta-i noise has little effect on the circuit of the outside plane. However, case 3 is worse than case 1 when no further steps are taken to resolve the PI problem. Although the bridge provides power voltage to the inner island, delta-i noise also propagates through this bridge. Resonance modes occur at 0.43 GHz and GHz for case 3, which are below the first resonant frequency of GHz in case 1 (Fig. 3), indicating that the delta-i noise causes a PI issue when it switches at a frequency lower than the frequency in case 1. C. The Voltage Regulator Module on the Printed Circuit Board Generally, a VRM is used to provide stable DC voltage to the central processing units (CPUs), digital signal processors (DSPs), and large switching chips. The VRM converts one DC voltage to another DC voltage. A VRM must have a low output impedance from 1 Hz to 1 khz; many bulk capacitors can maintain a low output impedance from 1 khz to 1 MHz [12] [16], which means the DC voltage between the power and ground planes will be stable from 1 Hz to 1 MHz. Even when the frequency is >1 GHz, the VRM will maintain its low impedance characteristic. Therefore, the VRM can be modeled as a shorting via when simulating delta-i noise. To identify delta-i noise, the DC voltage is set to zero. III. SUPPRESSING DELTA-I AND LOW FREQUENCY NOISE USING A MOAT AND A VRM

7 A VRM maintains a stable power voltage and suppresses noise propagating in the low frequency range. At a low frequency range, the whole system can be treated as a lumped circuit, so the voltage levels of ports 2 and 3 must equal that of port 1. Therefore, if no VRM existed on the power plane, low frequency noise would influence ports 2 and 3 when port 1 is switched on/off. The VRM was placed at the three positions near the border. Fig. 4 shows the layout of the test positions. Fig. 5 presents the measurement results for the three locations. The VRM was also placed on the integral plane for comparison. Experimental results indicated that all of the first resonant frequencies were roughly 0.22 GHz, suggesting that the location of the VRM had little influence on the first resonant frequency. Although the VRM will decrease the voltage fluctuation on the nearest pin, it is impossible to decrease the fluctuation on the entire plane. Location 2 is a good choice for decreasing the voltage fluctuation as it has a small magnitude on average at the first resonant frequency for all of the pins in the three cases. If the VRM is near the bridge, the noise propagating from the inside island will directly shunt to the ground. IV. IMPROVING THE POWER INTEGRITY WITH DECOUPLING CAPACITORS A. Decoupling Capacitors To suppress the first resonant frequency occurring in the operational frequency range, de-caps were utilized to improve the PI. The influence of different capacitance values is also discussed. Two de-cap types, 47 pf and 470 pf, were placed at the bridge entrance (Fig. 6). A de-cap

8 has an equivalent series inductance (ESL, Le) and equivalent series resistance (ESR) parasitized in the de-cap. Table І in Murata [17] indicates that the resonant frequency of a capacitor can be calculated by f = 1 ESL Capacitance. R When the system is a lumped circuit system, the resonant frequency of the power/ground planes can easily be canceled by choosing de-caps that have a series resonant frequency that is equal to the resonant frequency of the planes. However, with a high frequency, it is not as easy to choose a de-cap. Since the whole system turns into a distribution system, the best choice for stabilizing the PI depends on the values of the de-caps and the positions where they are located. In the following cases, the VRM was placed at Location 2 (77 mm, 50 mm). Table ІІ presents the effects of the de-caps for the three cases. Experimental results demonstrated that 470 pf was better than 47 pf for this structure (Fig. 7). Moreover, the improvement in the PI was increased by using two de-caps, as the ESL of de-caps was decreased when de-caps were in parallel. Notably, if the VRM was close to the bridge and additional capacitors were applied to decrease the ESL, the PI was improved. Fig. 8 shows the position of the VRM on the board. The first resonance frequency was GHz and the amplitude of S 31 was <-25 db (Table ІІІ). B. Comparison of the Proposed Method and Practical Printed Circuit Board Design Practical PCB designs used multiple de-caps to form a wall around sensitive components to isolate noise. This structure adds considerable costs to PCBs. The proposed method was compared with this standard design. A wall of 36 de-caps was utilized to replace the

9 moat surrounding the inner island (Fig. 10). There were four de-cap types 2.7 nf, 3.3 nf, 4.7 nf, and 5.6 nf (Fig. 10). Fig. 11 presents the measurement results. For a frequency <0.8 GHz, the de-cap wall performed better than the current method. However, as the frequency increases to >1.5 GHz, S 31 of the case surrounded by the capacitor wall will increase due to the effect of the ESL. Since the current method uses very few de-caps, the effect of the ESL will not dominate the PI performance. C. Fluctuation of Power Voltage Time domain data can be acquired using the following two methods. The first method constructs a time-domain measurement system, which includes a digital signal generator and a digital oscilloscope (e.g., Time Domain Reflectometry (TDR)) for measurements in the time domain. The other method obtains time domain data by inverse Fourier transformation (IFT) from a frequency domain measurement system (e.g., vector network analyzer (VNA)). Since the calibration and measurement techniques for frequency-domain measurement instruments are superior to those of time-domain measurement instruments, this study used the second method to obtain time domain data. First, a time-domain digital current source (Fig. 12) was generated and then transformed into a frequency domain response by applying the Fourier transform. The frequency domain response for the current was then multiplied by the S-parameter measured by the VNA; the time domain response was then obtained by IFT. The data rate was 1.8 Gbps, the rising time and falling time were ps, and the current swing was 1mA (Fig. 13). Table ІV presents the noise levels for the different methods.

10 The proposed method was clearly better than the method that used a capacitor wall. The noise level for the proposed method was <50% of the level for the capacitor wall and integral power plane at port 2, <20% for the case with a capacitor wall, and <8.33% for the case with an integral plane. Moreover, the number of capacitors in the proposed method was only one-twelfth of that in the capacitor wall. V. CONCLUSION This work presented a novel structure to replace the traditional PCB method of using a large number of capacitors to form a wall around a sensitive IC. This structure improves the PI and is low cost. As demonstrated, the proposed structure suppresses switching noise and performs better than the de-cap wall using only three de-caps. Both the PI and commercial issues can be improved by using the proposed structure. REFERENCE [1] Y. Chen, Z. Wu, A. Agrawal, Y. Liu, and J. Fang, Modeling of Delta-I noise in digital electronics packaging, IEEE Multi-Chip Module Conference, Mar. 1994, pp [2] S.V.D. Berghe, F. Olyslager, D.D. Zutter, J.D. Moerloose, and W. Temmerman, Power plane resonances as a source of delta-i noise and the influence of decoupling capacitors, IEEE International Symposium on Electromagnetic Compatibility, Aug. 1997, pp [3] S. Chun, J. Choi, S. Dalmia, W. Kim, and M. Swaminathan, "Capturing via effects in simultaneous switching noise simulation," IEEE International

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16 (A) (B) FIGURE 1 SCHEMATIC DIAGRAM FOR (A) A FOUR-LAYER STRUCTURE OF COMMONLY USED PRINTED CIRCUIT BOARD AND (B) DISSEMINATION OF THE DELTA-I NOISE FIGURE 2 (A) INTEGRAL POWER BOARD

17 FIGURE 2 (B) ISOLATED BOARD FIGURE 2 (C) BRIDGE BOARD

18 FIGURE 3 SIMULATIONS AND MEASUREMENT RESULTS OF THREE SIMPLIFIED TEST BOARDS (A) S21 FIGURE 3 SIMULATIONS AND MEASUREMENT RESULTS OF THREE SIMPLIFIED TEST BOARDS (B) S31

19 FIGURE 4 THREE LOCATIONS OF VRM TO MEASURE THE INFLUENCE ON POWER INTEGRITY FIGURE 5 THE SIMULATION RESULTS OF VRM AT (A) LOCATION 1 (97 mm, 50 mm)

20 FIGURE 5 THE SIMULATION RESULTS OF VRM AT (B) LOCATION 2 (77 mm, 50 mm) FIGURE 5 THE SIMULATION RESULTS OF VRM AT (C) LOCATION 3 (3 mm, 50 mm)

21 TABLE І FOUR KINDS OF DE-CAPS (USED FOR SIMULATION IN POWER-SI) Capacitor ESL ESR Capacitance F R 47 pf 0.64 nh ohm 47 pf GHz 470 pf 0.6 nh 0.06 ohm 470 pf GHz 560 pf 0.58 nh ohm 560 pf GHz 2.7 nf 0.64 nh 0.53 ohm nf 0.8 GHz 5.6 nf 0.69 nh ohm nf GHz FIGURE 6 (A) ONE DE-CAP IS ADDED AT (69.5 mm, 50 mm) TO IMPROVE THE PI

22 FIGURE 6 (B) TWO DE-CAPS ARE ADDED TO GET THE FURTHER IMPROVEMENT BY DECREASING THE EFFECT OF ESL FIGURE 7 SIMULATION AND MEASUREMENT RESULTS FOR ADDING DE-CAPS (A) S21

23 FIGURE 7 SIMULATION AND MEASUREMENT RESULTS FOR ADDING DE-CAPS (B) S31 TABLE ІІ THE MAGNITUDE OF S 21 AND S 31 FOR THE FIRST RESONANT PEAK Tested structures S 21 (db, GHz) S 31 (db, GHz) One 47pF de-cap (PowerSI) (-12.85, 0.232) (-17.98, 0.232) One 470pF de-cap (PowerSI) (-12.51, 0.218) (-17.77, 0.218) Two 470pF de-caps (PowerSI) (-13.47, 0.201) (-17.92, 0.2) One 47pF de-cap (meas.) (-11.83, 0.23) (-19.6, 0.23) One 470pF de-cap (meas.) (-12.04, 0.23) (-19.69, 0.23) Two 470pF de-caps (meas.) (-17.31, 0.176) (-21.59, 0.176)

24 FIGURE 8 THREE DE-CAPS ARE USED TO GET BETTER IMPROVEMNT FOR PI FIGURE 9 MEASUREMENT RESULTS OF THE STRUCTURE SHOWN IN FIGURE 8 (A) THE MAGNITUDES OF S 21

25 FIGURE 9 MEASUREMENT RESULTS OF THE STRUCTURE SHOWN IN FIGURE 8 (A) THE MAGNITUDES OF S 31 TABLE ІІІ THE FIRST RESONANT FREQUENCY AND THE MAGNITUDES OF S 21 AND S 31 AT FIRST RESONANT FREQUENCY Measure testing boards S 21 (db, GHz) S 31 (db, GHz) Integral power board (-10.1, 0.245) (-14.65, 0.245) Isolated board (-24.59, 0.225) (-35.53, 0.225) Three 560pF de-caps (-29.5, 0.176) (-33.14, 0.167) Three 5.6nF de-caps (-18.09, 0.245) (-27.9, 0.245)

26 FIGURE 10 CAPACITORS WALL TO SURROUND THE SENSITIVE ICs FIGURE 11 THE COMPARISONS OF MEASUREMENT RESULTS AMONG THE CAPACITOR WALL, THE TOTALLY ISOLATED CASE, AND THE PROPOSED STRUCUTRE (A) S 21

27 FIGURE 11 THE COMPARISONS OF MEASUREMENT RESULTS AMONG THE CAPACITOR WALL, THE TOTALLY ISOLATED CASE, AND THE PROPOSED STRUCUTRE (A) S 31 FIGURE 12 INPUT CURRENT SOURCE OF ANALOGY SIGNAL

28 FIGURE 13 (A) FLUCTUATION VOLTAGES AT RECEIVING PORT 2 WHEN THE EXCITING PORT IS LOCATED AT PORT 1 FIGURE 13 (B) FLUCTUATION VOLTAGES AT RECEIVING PORT 3 WHEN THE EXCITING PORT IS LOCATED AT PORT 1

29 TABLE ІV VOLTAGE FLUCTUATION OF THREE CASES Cases Location Fluctuation Voltages Integral power board Capacitor wall The present method by using three 560pF de-caps Port 2 Port 3 Port 2 Port 3 Port 2 Port mv mv mv mv 0.29 mv 0.06 mv