ASIC BASED PROCESSING FOR MINIMUM POWER CONSUMPTION CONCEPT DESCRIPTION FOR PHASE 1

Transcription

1 ASIC BASED PROCESSING FOR MINIMUM POWER CONSUMPTION CONCEPT DESCRIPTION FOR PHASE 1 Document number... WP TD 001 Revision... 1 Author... L D Addario Date Status... Approved for release Name Designation Affiliation Date Signature Additional Authors Submitted by: L D Addario JPL Approved by: W. Turner Signal Processing Domain Specialist SPDO

2 DOCUMENT HISTORY Revision Date Of Issue Engineering Change Number Comments A First draft release for internal review B 2 nd March 2011 Initial release 1 29 th March 2011 First Issue DOCUMENT SOFTWARE Package Version Filename Wordprocessor MsWord Word f wp td asic concept description Block diagrams Other ORGANISATION DETAILS Name Physical/Postal Address SKA Program Development Office Jodrell Bank Centre for Astrophysics Alan Turing Building The University of Manchester Oxford Road Manchester, UK M13 9PL Fax. +44 (0) Website ACKNOWLEDGMENTS The author is with the Jet Propulsion Laboratory, which is operated by California Institute of Technology for NASA. Government sponsorship acknowledged. 2011, California Institute of Technology Page 2 of 13

3 TABLE OF CONTENTS 1 INTRODUCTION REFERENCES CROSS CORRELATION FILTER BANKS STATION BEAMFORMERS FOR AAS RISKS Page 3 of 13

4 LIST OF FIGURES Figure 1 Signal Processing Functional Context Diagram... 6 Figure 2 Block diagram of signal pro[type a quote from the document or the summary of an interesting point. You can position the text box anywhere in the document. Use the Text Box Tools tab to change the formatting of the pull quote text box.] Figure 3 Frequency domain beam forming element LIST OF TABLES Table 1 Correlator Requirements... 8 Table 2 Correlator Properties Page 4 of 13

5 LIST OF ABBREVIATIONS AA... Aperture Array CoDR... Conceptual Design Review DRM... Design Reference Mission EoR... Epoch of Reionisation EX... Example FLOPS... Floating Point Operations per second FoV... Field of View PAF... Phased Array Feed PrepSKA... Preparatory Phase for the SKA RFI... Radio Frequency Interference rms... root mean square SKA... Square Kilometre Array SKADS... SKA Design Studies SPDO... SKA Program Development Office SSFoM... Survey Speed Figure of Merit TBD... To be decided Page 5 of 13

6 1 Introduction This document describes a possible implementation of SKA signal processing for Phase 1, as defined in SKA Memo 130 [3] (with some modifications). The main focus is on the central cross correlators, but some discussion of station beamformers (for the AAs) and of filter banks is included. The correlator implementation is based on use of an ASIC described in [1]. The parameters of the ASIC were chosen to minimize power consumption when it is used to implement phase 2 of SKA mid (N~2000 antennas, B=1 GHz bandwidth), but here I describe use of the same IC to implement correlators for phase 1, including both the reflector antenna (dish) component (N=250, B=1 GHz, 1 beam) and the dipole like (sparse "AA") component (nominally N=50, B=380 MHz, J=480 beams). The ASIC's performance is based on its fabrication in a 90 nm CMOS process. Beamformers and filter banks are each assumed to be implemented with ASICs, but those designs are less well developed. Models for power consumption are described in Appendix A of [1]. Other considerations are described in [2]. Figure 1 shows the logical context for the signal processing system in the SKA telescope. bdd [package] Context [Signal processing context] 0..* Environment Engineer Maintainer Monitoring & Control Operator Simulator Scientist 0..* Digitised RF + RFI «System» Signal Processing Processed Data Receptors Science Computing 0..* 1..* VLBI Power Cooling External Transient Triggers Time Reference Figure 1 Signal Processing Functional Context Diagram 2 References Specific to this report: [1] L. D'Addario, "Low Power Correlator Architecture For the Mid Frequency SKA", SKA Memo xxx. Submitted Page 6 of 13

7 [2] L. D'Addario and S. Simmons, "Signal Processing For a Lunar Array: Minimizing Power Consumption." Presentation at USNC URSI National Radio Science Meeting, Boulder, CO, USA, 2011 January 5. [3] P. Dewdney et al., "SKA Phase 1: Preliminary System Description." SKA Memo 130, November [4] W. Turner, "Two Stage Beamformer Cost Minimization." Unpublished notes of 20 April 2010 (private communication). [5] L. D'Addario and S. Simmons, URSI presentation, Jan [6] B. Richards, N. Nicolici, H. Chen, K. Chao, D. Werthimer, and B. Nikolić, "A 1.5GS/s 4096 Point Digital Spectrum Analyzer for Space Borne Applications." IEEE Custom Integrated Circuits Conference, September, Available: [7] HP Labs, CACTI memory simulator. General references: [8] SKA Science Case [9] The Square Kilometre Array Design Reference Mission: SKA mid and SKA Lo v 0.4 [10] Science Operations Plan [11] System Interfaces [12] Environmental requirements (natural and induced) [13] SKA strategies and philosophies [14] Risk Register [15] Requirements Traceability [16] Logistic Engineering Management Plan (LEMP) [17] Risk Management Plan (RMP) [18] Document Handling Procedure [19] Project Dictionary [20] Strategy to proceed to the next phase [21] WP3 SKA array configuration report [22] WP3 SKA site RFI environment report [23] WP3 Troposphere measurement campaign report [24] SKA Science Technology Trade off Process (WP MP 004) [25] A. Faulkner, et al., Aperture Arrays for the SKA: the SKADS White Paper, January [26] E. de Lera Acedo et al., System Noise Analysis of an Ultra Wide Band Aperture Array: SKADS Memo T28. [27] SKA Monitoring and Control Strategy WP R 001 Issue Draft E [28] The Square Kilometre Array, Peter E. Dewdney, Peter J. Hall, Richard T. Schilizzi, and T. Joseph L. W. Lazio, Proceedings of the IEEE Vol. 97,No. 8, August 2009 [29] Thompson, A. R., Moran, J. M., and Swenson, G. W. Interferometry and Aperture Synthesis in Radio Astronomy (second edition), Wiley, [30] System Engineering Management Plan (SEMP) WP MP 001Reference 3 [31] SKA System Requirement Specification (SRS) [32] SKA IP Policy Document [33] International Technology Roadmap for Semiconductors (ITRS), available at Page 7 of 13

8 3 Cross Correlation WP TD 001 This concept uses the ASIC described in [1] as the best choice for a 2000 antenna array. That IC consists of an square array of 150x150 CMACs and a DRAM input data buffer of MB. The CMAC array can be used to compute visibilities for all baselines of an array where N is any multiple of 75 (150 signals per antenna) 1. The DRAM can be organized in various ways, depending on the number of times that the CMACs must be re used to compute all baselines, and on the integrating time. It can hold (175500)(75/N) = 13,164,500/N samples for each of the 2N signals, which allows integrating for time τ = 13,164,500/(bN) when the channel bandwidth is b. Table 1 gives the principal correlator requirements from [3]. Numbers in parentheses are revised Reflector Antennas Dipole like Elements N, number of antennas/stations 250 (225, 300) 50 (75, 150) B, total bandwidth, MHz b, channel bandwidth, MHz to 0.05 (.01) J, number of station beams (320, 160) τ, integrating time, minimum, s τ, integrating time, maximum, s Table 1 Correlator Requirements values that are used for the concept described here. The number of antennas or stations N is made a multiple of 75 for efficient use of the proposed ASIC. For the dipole array, the number of stations is larger than specified in [3]. Although this makes the correlator larger, the number of elements per station can be reduced while keeping constant either the point source sensitivity (where the total number of elements is unchanged) or the survey speed (where the total number of elements is reduced). This reduces the size of beamformers (see section 5 below), with the net result of lower total power consumption. Since each station is smaller, the station beam is larger, so fewer beams J need to be formed to achieve the same field of view. The channel bandwidth b for the dipole array is assumed to be 10 khz on average. Although b=1 khz is specified in [3], it is noted that this is needed only at the low end of the frequency range (70 MHz). The correlator can accommodate channels of varying bandwidth, so it is assumed that they approach ~50 khz at the high end (450 MHz) and that the average is 10 khz (so that the total number of channels is 38,000). Table 2 gives the results of calculations on use of the ASIC in each of the arrays for a few different parameter values. Consider the column in the lower part of Table 2 labelled "Dishes, N=300, min τ." At the minimum integrating time of τ=0.1 s from [3], the maximum number of frequency channels that can be computed is 550; this is limited by the constraint adopted in [1] that the IC output rate should not exceed 40 Gb/s. Note that the combination of τ=0.1 s and B/b=67,000 required by [3] causes the 1 It can also be used when N is not a multiple of 75 by providing dummy data on some inputs Page 8 of 13

9 total correlator output rate (4.8 Tb/s) to be twice its total input rate (2.4 Tb/s), as shown at the bottom of the table. To compute all channels then requires 121 ICs, consuming a total power of 713 W Page 9 of 13

10 Parameters, fixed Symbol Value Constraints: Sample size (Re+Im), bits w s 4 Input rate per chip less than 40 Gbps STI reg. size (Re+Im), bits w c 32 Output rate per chip less than 40 Gbps LTI reg. size (Re+Im), bits w i 40 Chip power dissipation, max. 75 W Technology Coefficients Chip area leas than 200 mm 2 Gate length, nm g 90 Energy per CMAC, J e 2.45E 12 Energy per I/O bit transferred, J e io 2.12E 12 Area per CMAC, mm 2 a RAM energy/op, J (CACTI) e m 3.75E x 177.5k DRAM [1] RAM area, mm 2 (CACTI) a m x 177.5k DRAM [1] RAM max. speed, Hz (CACTI) 1.27E x 177.5k DRAM [1] RAM static power, W (CACTI) P m x 177.5k DRAM [1] Dishes Dishes Dishes Dipoles Dipoles Dipoles Formula N =300 N =300 N =225 N =150 N =150 N =75 min τ max τ max τ max τ min τ max τ Parameters Number of antennas N Number of station beams J Total bandwidth, Hz B 1.00E E E E E E+08 Channel bandwidth, Hz b 1.50E E E Integration time, short term, s τ Chip level results Channels/chip K CMACs/chip m Chips per subband Re use factor x=n/sqrt(m)[2n /sqrt(m)+1] Clock rate, Hz f=xbk [Note 2] 8.25E E E E E E+07 Input rate, b/s R i = 2NbKw s 1.98E E E E E E+10 Output rate, b/s R o = Kmxw c/τ 3.96E E E E E E+08 Input buffer size, bits 2Nb τ w s 3.60E E E E E E+05 Input buffer width, bits sqrt(m)w s Input buffer depth, words 2Nb τ/sqrt(m) CMAC power, W m e f Input receiver power, W R i e io Input buffer memory power, W 2f e m1 + P m Output transmitter power, W R o e io Chip power, total, W CMAC area, mm 2 m a RAM area, mm 2 a Chip total area, mm System level results Chip count, total in system c=b/(bk) ,842 1,842 1,842 Total input rate, all chips, b/s 2.40E E E E E E+16 Total output rate, all chips, b/s 4.80E E E E E E+14 Total power, all chips, W ,673 12,693 8,863 Notes [1] Using COMM DRAM in CACTI, with 2 read ports and 1 write port. Depth is more than needed; allows smaller area. [2] Number of channels reduced to keep clock rate less than maximum RAM speed. Table 2 Correlator Properties limiting constraint far below constraint requirement not met The next column shows the situation for N=300 at maximum τ. Integrating time is limited by the capacity of the buffer memory, which is full when τ=2.9 s, so that the 4.1 s in Table 1 is not achieved. Longer integrating time reduces the output data rate, so that is no longer a constraint and it would be possible to operate the chip at higher clock rate, computing more channels per chip and requiring Page 10 of 13

11 fewer chips. However, we still need 121 chips to handle the τ=0.1 s case, so the clock rate is not changed. A limitation of the architecture used here is that it is not practical to use different integrating times on different baselines. Even though [3] specifies that the shortest integrating time is needed only on the longest baselines, achieving it requires using the same integrating time on short baselines as well. Of course, multiple integrations could be summed for short baselines in a subsequent stage of processing. The next column shows the situation for N=225. In this case, the maximum integrating time is 3.9 s and all channels can be computed at τ=0.1 s with only 72 ICs dissipating 423 W. The remaining columns are appropriate to the stations with dipole like elements. At N=150, the maximum integrating time is 8.5 s (not achieving the 49 s desired in [3]), but the minimum of τ=1.2 s is easily achieved. The number of channels that can be computed is limited by the adopted constraint on each chip's input data rate of 40 Gb/s. Either case requires 12 ICs dissipating 79 W per beam, but 1,842 ICs dissipating 12.7 kw for all 160 beams. The last column shows that if N=75 then we have enough memory to support an integrating time up to 17 s, but the same total number of ICs is needed. Only half as many ICs are needed per beam, but we must compute twice as many beams. The total power is reduced to 8.9 kw because the clock rate can be reduced. Nevertheless, larger N is preferred (and much larger than the N=50 specified in [3]) because this reduces the size of the station beamformers, as shown in Section 5 below. 4 Filter Banks For the dish array, 2N filter banks are needed to break the bandwidth B into channels of width b. For the AAs, each station needs 2L filter banks, where L is the number of dual polarization antenna elements per station, or 2LN all together. Each filter bank performs (B/2) log 2 (B/b) FFT butterfly operations per second. (A polyphase structure is likely to be used, in which case the FFT is accompanied by an FIR pre filter. But when B/b is large, the pre filter uses far less power and space than the FFT, so we ignore it here.) The total FFT butterfly rate is therefore 4.81x10 12 s 1 for the dish array (using N=300) and 3.24x10 15 s 1 for the AA system. As with the cross correlators, the filter banks are best implemented with ASICs. Richards et al. [6] have described an ASIC in 90 nm CMOS that implements a 4096 channel spectrometer for 750 MHz bandwidth real signals. It uses an length 4 pre filter and a K=8192 complex FFT and supports a sampling rate of 1500 MHz on a 7.8 mm 2 chip (4.0 mm 2 neglecting I/O pads). It consumes 0.71 W, of which 0.1 W is static power. This chip therefore provides 9.75x10 9 FFT butterflies/s at an energy of 62.6 pj/butterfly (see also Appendix A of [1]). Much larger chips could be built, but we would eventually run into a power limit or I/O limit, and there would be no change in system power or system I/O requirements. Since this chip was built in our target 90 nm technology, we use these results without scaling to determine the power and chip count for our concept. We therefore estimate that all filter banks for the dish array can be implemented with 494 chips dissipating 350 W. For the AA system, each station would need 2,214 chips dissipating 1472 W, or 332,050 chips dissipating kw for all 150 stations Page 11 of 13

12 5 Station Beamformers for AAs WP TD 001 An aperture array station consists of L dipole like elements feeding a beam forming processor, which combines L signals to form J station beams (for each polarization). The beam forming processor consists of a large number of elementary units, each of which consists of an adjustable delay and an adder. To implement the entire processor in one stage requires n b = JL of these units per polarization, or 2JL total. However, it is almost always advantageous to break the processing into two stages, as shown in Figure 2. In this scheme, the L elements are partitioned into e2 groups of e1 elements, where each group forms a similar array (and so L=e1e2). Each group feeds a small beam forming processor that produces b1 beams. Each of the b1 beams are then the inputs to a second stage of small beam forming processors, each of which produces b2 beams. We then need b/b2 second stage beam forming processors to produce the desired b beams.. It has been shown [4] that the number of beam former units needed is minimized by choosing e 1 = e 2 = b 2 = SQRT(L), so that b 1 = b/sqrt(l). The total number of elements required is then n b = e 1 b 1 e 2 + e 2 b 2 (b/b 2 ) = 2 b SQRT(L) per polarization. The parameters of [3] call for L = 11,200 elements/station, b = 480 station beams, and N = 50 stations. Using optimum 2 stage beam forming, this requires about n b = 203,200 beam forming units per station, or 10,160,000 for all stations. Consider the alternative proposed in Table 1 where N = 150 stations. If we keep the total number of elements the same (11200x50 = 560,000) to produce the same sensitivity, each station is smaller (L = 3733 elements, but choose L = 3721 = 61 2 ) and therefore produces larger station beams, so we need only 160 beams to produce the same field of view. This leads to n b =39,040 beam forming units per station or 5,856,000 for all stations. Studies reported in [5] and in Appendix A of [1] estimate the energy per operation of one beam forming unit as c b = 12 pj in current technology (90 nm CMOS). The power they require is then c b n b N B = 46.3 kw for the 50 station design of [3] and 26.7 kw for the 150 station alternative. The difference is far more than the total power used by the 150 station correlator (Table 2), so the tradeoff is well worthwhile. As with cross correlation, beam forming is best implemented with ASICs. To estimate how many ASICs might be required, consider frequency domain beam forming, where the beam forming unit has the structure shown in Figure 3. Since it includes a complex multiplier and complex adder, it is similar to a CMAC. It also includes a RAM to store complex coefficients for all frequency channels, representing the current delay and gain, where there are K=B/b channels. Since K=67,000 for the dish array and 38,000 for the AA, the RAM dominates the cell. An 8b x embedded SRAM in 90 nm CMOS requires about 1.15 mm 2 (result from simulation by CACTI [7]). A large but feasible 200 mm 2 chip could then provide 256 beam forming units. The complete beam former for each AA station would then require 153 chips, and we would need 22,950 chips for all stations. 6 Risks The ASIC designs mentioned here are immature. They consist only of top level parameters and no detailed design has been carried out. Therefore there is a risk that some practical limitation or difficulty has not been properly taken into account Page 12 of 13

13 The power estimates are based on models derived partly by scaling, so they may contain significant errors. No significant effort has been made to determine monetary cost; instead, the emphasis has been on power consumption. Development costs (NRE) are very uncertain, as is the development schedule. However, the proposed ASICs are intended to have a flexible architecture, such that they should be usable in multiple instruments besides SKA 1. It is thus possible that development cost and responsibility can be shared with other projects. Figure 2 Block diagram of signal pro[type a quote from the document or the summary of an interesting point. You can position the text box anywhere in the document. Use the Text Box Tools tab to change the formatting of the pull quote text box.] Figure 3 Frequency domain beam forming element Page 13 of 13