FSHDMI04 Wide-Bandwidth Differential Signaling HDMI Switch

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Low power consumption (1µA maximun) Control input: TTL compatible Applications UXGA and 1080p DVI and HDMI video source selection Ordering Information Order Number Package Number General Description

1 Click to see this datasheet in Simplified Chinese! Wide-Bandwidth Differential Signaling HDMI Switch Features 1.65 Gbps throughput 8kV ESD protection -26dB non-adjacent channel crosstalk at 825MHz Isolation ground between channels Low skew - Inter-pair skew <150ps - Intra-pair skew <90ps Fast turn on/off time Low power consumption (1µA maximun) Control input: TTL compatible Applications UXGA and 1080p DVI and HDMI video source selection Ordering Information Order Number Package Number General Description October 2006 The is a wide bandwidth switch for routing HDMI Link Data and Clock signals. This device supports data rates up to 1.65Gbps per channel for UXGA resolution. It can also be used to switch TMDS-based DVI digital video streams. Possible applications include LCD TV, DVD, Set-Top Box, notebook computers and other designs with multiple digital video interfaces. The switch allows the passage of HDMI link signals with low non-adjacent channel crosstalk and superior OFF-Isolation. This performance is critical to minimize ghost images between active video sources in video applications. The wide bandwidth of this switch allows the high speed differential signal to pass through the switch with minimal additive skew and phase jitter. Package Description QSPX MQA48A 48-Lead Quarter Size Very Small Outline Package (QVSOP), JEDEC MO-154, 0.150inches Wide MTDX MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide BQX (Preliminary) MLP56 56-Lead Molded Leadless Package (MLP), 5x7mm Wide Applications Diagram 2:1 Differential Multiplexer TMDS 0+ HDMI Source 1 TMDS 0 TMDS 1+ Video HDTV or Monitor 3 Data + 1 Clock (Differential) TMDS 1 TMDS 2+ HDMI Receiver HDMI Source 2 TMDS 2 Clock + Clock Alternate Audio Source Audio Audio Switch CD4052 Audio Processor and Amplifier Control 3 Data + 1 Clock (Differential) S OE 2005 Fairchild Semiconductor Corporation

2 Pin Assignments Pin Assignments Figure 1. MLP Pin Assignments Truth Table S OE Function X H Disconnected L L 1C n = C n H L 2 C n = C n Pin Descriptions Pin Name OE S 1C n, 2C n, C0 n, C1 n, C2 n, C3 n Description Bus Switch Enable Select Input Data Ports Figure 2. QVSOP and TSSOP Pin Assignments 2005 Fairchild Semiconductor Corporation 2

3 Absolute Maximum Ratings The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table defines the conditions for actual device operation. Symbol Parameter Rating V CC Supple Voltage 0.5V to +4.6V V S DC Switch Voltage 0.5V to V CC V IN DC Input Voltage (1) 0.5V to +4.6V I IK DC Input Diode Current 50 ma I OUT DC Output Sink Current 128 ma T STG Storage Temperature Range 65 C to +150 C ESD, Human Body Model 8,000V Recommended Operating Conditions (2) Symbol Parameter Rating V CC Power Supply Operating 3.0V to 3.6V V IN Control Input Voltage 0V to V CC Switch Input Voltage 0V to V CC T A Operating Temperature 40 C to 85 C DC Electrical Characteristics All typical values are for V CC = 25 C unless otherwise specified. Symbol Parameter Conditions V CC (V) T A = 40 C to +85 C Min. Typ. Max. V IK Clamp Diode Voltage I IN = 18mA V V IH Input Voltage HIGH V V IL Input Voltage LOW V I IN Control Input Leakage V IN = 0 to V CC 3.6 ±1.0 μa I OZ OFF-STATE Leakage 0, C n V CC 3.6 ±1.0 μa R ON Switch On Resistance (3) V IN = V CC 0.6 to V CC, Ω I ON = 10mA R ON(FLAT) Switch On Resistance Flatness (4) V IN = V CC 0.6 to V CC, Ω I ON = 10mA I CC Quiescent Supply Current V IN = 0 or V CC, I OUT = μa Units Notes: 1. The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed. 2. Unused control inputs must be held HIGH or LOW. They may not float. 3. Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the voltages on the two (A or B) pins. 4. Flatness is defined as the difference between the maximum and minimum value on resistance over the specified range of conditions Fairchild Semiconductor Corporation 3

4 AC Electrical Characteristics All typical values are for V CC = 25 C unless otherwise specified. Symbol Parameter Conditions V CC (V) t ON Turn ON Time S, OE-to-Output t OFF Turn OFF Time S, OE-to-Output t BBM Break-Before-Make Time t PD (t PLH, t PHL ) Switch Propagation Delay V IN = V CC 0.5, R PU = 50Ω, C L = 5pF V IN = V CC 0.5, R PU = 50Ω, C L = 5pF V IN = V CC 0.5, R PU = 20Ω, C L = 5pF T A = 40 C to +85 C Min. Typ. Max. Units Figure Number 3.0 to ns Figure 7 Figure to ns Figure 7 Figure to Figure 14 R PU = 50Ω, C L = 5pF 3.0 to ps Figure 7 Figure 13 T JITTER Total Jitter (DJ + RJ) f = 165MHz Clock with 3.0 to ps Figure 7 T RATIO Duty Cycle Ratio 50% Duty Cycle, RPU = 50Ω, C L = 5pF 50.0 % T SK1 Intra-Pair Skew C n + to C n (5) f = 1.65Gbps, PRBS R PU = 50Ω, C L = 5pF 3.0 to ps Figure 7 Figure 13 T SK2 Inter-Pair Skew (5) (Between any two switch paths) f = 1.65Gbps, PRBS R PU = 50Ω, C L = 5pF 3.0 to ps Figure 7 Figure 13 O IRR OFF-Isolation R T = 50Ω, f = 370MHz 3.0 to db Figure 9 R T = 50Ω, f = 825MHz 3.0 to Xtalk Non-Adjacent Channel R T = 50Ω, f = 370MHz 3.0 to db Figure 10 Crosstalk R T = 50Ω, f = 825MHz 3.0 to f MAX Maximum Throughput Gbps Notes: 5. Guaranteed by characteristics and design. Capacitance T A = 40 C to +85 C Symbol Parameter Conditions Min. Typ. Max. Units C IN Control Pin Input Capacitance V CC = 0V 1.1 pf C ON ON Capacitance V CC = 3.3V 6.0 pf C OFF Port C n OFF Capacitance V CC = 3.3V 2.5 pf 2005 Fairchild Semiconductor Corporation 4

5 Typical Characteristics Figure 3. Off- Isolation, V CC = 3.3V Figure 4. Crosstalk, V CC =3.3CV 2005 Fairchild Semiconductor Corporation 5

6 Test Diagrams V ON NC Cn V IN I ON Select V Sel = 0 to V CC R ON = V ON / I ON I Cn(OFF) Figure 5. On Resistance Figure 6. OFF Leakage Generator V Sel 10mA V CC Cn V IN C L * A V IN Select V Sel = 0 to V CC Each switch port is tested separately. R PU V OUT R PU and C L are functions of application environment (see AC/DC Tables for values of C L and R PU ) *C L includes fixture and stray capacitance Figure 7. AC Test Circuit Load 2005 Fairchild Semiconductor Corporation 6

7 Test Diagrams (Continued) t RISE = 2.5ns t FALL = 2.5ns V CC 90% 90% Input V Sel V CC / 2 V CC / 2 10% 10% V Sel V CC Output V OUT V CC % 10% t ON t OFF Figure 8. Turn ON / Turn OFF Waveforms NC VSel R T R T Network Analyzer R S Figure 9. Channel OFF-Isolation V S V OUT R S and R T are functions of the application environment (see AC/DC Tables for values of R T ) OFF-Isolation = 20 Log (V OUT / V IN ) Network Analyzer V IN R S V S R T R S and R T are functions of the application environment (see AC/DC Tables for values of R T ) Crosstalk = 20 Log (V OUT / V IN ) R T V OUT Figure 10. Non-adjacent Channel-to-Channel Crosstalk Capacitance Meter S V Sel = 0 or V CC Capacitance Meter F = 1MHz S V Sel = 0 or V CC F = 1MHz Figure 11. Channel OFF-Capacitance Figure 12. Channel ON-Capacitance 2005 Fairchild Semiconductor Corporation 7

8 Test Diagrams (Continued) Generator t RISE = 240ps +500mV Output V OUT 500mV 0V t PLH t PHL t FALL = 240ps +500mV Input Differential Pair 80% 80% 1C Input V n+, 1C n ; IN 0V 0V 2C, 2C 20% 20% n+ n 500mV T = T SK1 PLH T PHL T SK2 = T PLH/HLmax T PLH/HLmin Ouput Differential Pair C n+, C n V Sel 10mA 10mA Figure 13. Intra- and Inter-Pair Skew, t PD C n C L * V CC R PU V OUT 0V t RISE = 2.5ns V CC Input V Sel V CC 10% Output V OUT Vol Vcc/2 t BBM 90% 10% R PU and C L are functions of application environment (see AC/DC Tables for values of C L and R PU ) *C L includes fixture and stray capacitance Figure 14. Break-Before-Make 2005 Fairchild Semiconductor Corporation 8

9 Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure Lead Quarter Size Very Small Outline Package (QVSOP), JEDEC MO-154, 0.150inches Wide 2005 Fairchild Semiconductor Corporation 9

10 Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 2005 Fairchild Semiconductor Corporation 10

11 Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. 2X 0.10 C TERMINAL # A1 INDEX AREA 0.8 MAX 0.10 C 0.05 C SEATING PLANE 0.65 A10 B TOP VIEW A11 B11 SIDE VIEW A14 B14 A 2X C B X 0.10 C B15 A X X 4.5MAX MAX LAND PATTERN RECOMMENDATION DESIGN ASSUMPTIONS: MMC-LMC IS.050MM PLACEMENT TOLERANCE IS.050MM X SIDES X X X X X SIDES A1 B1 B28 B25 A28 A BOTTOM VIEW NOTES: A. NOT CURRENTLY REGISTERED WITH ANY STANDARDS BODY. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D. PRELIMINARY DRAWING SUBJECT TO REVISION. B24 A x 0.10 CAB 0.05 C X X X 1.17 PCB SOLDERMASK OPENING RECOMMENDATION IPC7351 GUIDELINES USED FOR SOLDER RESIST LAYOUT. MLP56Arev2 Figure Lead Molded Leadless Package (MLP) 5x7mm 2005 Fairchild Semiconductor Corporation 11

12 2005 Fairchild Semiconductor Corporation 12

13 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: ON Semiconductor: QSP

FSUSB45 High-Speed USB2.0 (480Mbps) Switch with Dedicated Charger Port Detect

July 2013 FSUSB45 High-Speed USB2.0 (480Mbps) Switch with Dedicated Charger Port Detect Features Low On Capacitance: 7.0 pf Typical Low On Resistance: 3.9 Ω Typical Low Power Consumption: 1 μa Maximum