Wide-Band Inductorless Low-Noise Transconductance Amplifiers With High Large-Signal Linearity

Transcription

1 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 62, NO. 7, JULY Wide-Band Inductorless Low-Noise Transconductance Amplifiers With High Large-Signal Linearity Hemasundar Mohan Geddada, Member, IEEE, Chang-Tsung Fu, Member, IEEE, Jose Silva-Martinez, Fellow, IEEE, and Stewart S.Taylor, Fellow, IEEE Abstract Two high-linearity inductorless broadband low-noise transconductance amplifiers (LNTAs) employing noise and distortion cancellation techniques are presented. The core design employs a common-gate input stage and a common-source error-amplifier (EA) stage. Stacked PMOS NMOS topology enables large-signal operation while the drain current is reused. The high linearity performance is achieved by the derivative superposition of the pmos and nmos transistors that reduce the third-order distortion due to second-order interaction between input stage and EA stage. Critical design issues are carefully investigated along with the performance tradeoffs. In the fully differential architecture, the first LNTA covers GHz bandwidth and achieves a minimum noise figure (NF) of 3 db, third-order input intercept point (IIP3) of 10 dbm, and a 1-dB compression point of 0 dbm while dissipating 30.2 mw of dc power. The second lower power LNTA with bulk-driven technique achieves a minimum NF of 3.4 db, IIP3 of 11 dbm, GHz bandwidth at 16 mw of power consumption. Each LNTA occupies an active area of 0.06 mm in 45-nm CMOS. Index Terms Distortion cancellation, third-order input intercept point (IIP3), large-signal linearity, low-noise amplifiers (LNAs), low-noise transconductance amplifier (LNTA), noise cancellation, 1-dB compression point (P1 db), radio, RF receiver, wide swing. I. INTRODUCTION F UTURE wireless communication devices are expected to support multiple standards and features on a single chip. Therefore, significant research efforts have been dedicated to develop wideband receivers that can replace the multiple narrowband front-ends [1] [4]. Since wideband receivers have Manuscript received November 17, 2013; revised April 05, 2014; accepted May 01, Date of publication May 22, 2014; date of current version July 01, This work was supported in part by the Semiconductor Research Corporation (SRC) under Grant C H. M. Geddada was with the Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX USA. He is now with the Broadcom Corporation, Irvine, CA USA ( hgeddada@broadcom.com). C.-T. Fu is with the Intel Corporation, Hillsboro, OR USA ( chang-tsung.fu@intel.com). J. Silva-Martinez is with the Department of Electrical Engineering, Texas A&M University, College Station, TX USA ( jsilva@ece.tamu. edu). S. S. Taylor was with the Intel Corporation, Hillsboro, OR USA. He resides in Beaverton, OR USA ( stewt4@frontier.com). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TMTT much less frequency selectivity comparing to narrowband receivers, the front-end circuit amplifies not only the in-band signal, but also the out-of-band (OOB) signals. Strong OOB signals can potentially clip or saturate the front-end low-noise amplifier (LNA), resulting in gain compression and intermodulation, reducing the signal-to-noise ratio (SNR) in the receiver. OOB blockers or jammers may also degrade the SNR by reciprocal mixing with the local oscillator (LO) phase noise [1]. Therefore, linearity in the front-end LNA is very critical to avoid distortion and signal compression, especially in the presence of strong OOB blockers. Inductorless wideband LNAs are becoming popular due to the reduction in the real estate of the silicon [5] [7]. These LNAs significantly reduce cost, area, and power, while enabling simultaneous processing of several channels. However, the absence of inductors removes the inherent on-chip filtering provided by the passive inductors in the RF front-end and thus demands high linearity in the LNA over a wide frequency range to accommodate the different standards. Linearity requirement in wideband systems due to concurrent reception of multiple channels without filtering becomes more challenging, especially with surface acoustic wave (SAW)-less receivers [1] [4]. Another major challenge in the LNA design is achieving a low noise figure (NF) while satisfying impedance-matching requirements over several gigahertz of bandwidth [5] [7]. Many architectural innovations have been reported to develop wideband blocker-resilient receivers [3] and [4]. Mixer-first architectures with good linearity have been reported in [8] and [9]. Since the front-end LNA is missing, these architectures suffer from noise and LO feed through to the antenna. Another relevant work on blocker-resilient receivers is shown in Fig. 1 [1], [2]. This architecture replaces the front-end LNA by an RF low-noise transconductance amplifier (LNTA). The LNTA is followed by a current mode passive mixer and a transimpedance amplifier (TIA) combination. In such an approach, the impedance seen by the LNTA is a series combination of mixer switch ON resistance and the up-converted input impedance of the TIA. Thus, low load impedances for the LNTA can be ensured., a function of frequency, can be as small as 5 and can have a peak value of less than 30, depending on and. This architecture offers better performance than both active mixer and voltage-mode mixer implementations in terms of noise, linearity, and power consumption [3] IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See for more information.

2 1496 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 62, NO. 7, JULY 2014 Fig. 1. Blocker tolerant receiver architecture; current mode receiver [1]. In this paper, the proposed inductorless wide-signal wideband LNTAs are targeted for the receiver architecture shown in Fig. 1. Power consumption in this architecture scales down with technology [10]. It has the potential to handle the large signal with less distortion as the information is carried out in current [1], [10]. This architecture also has the advantage of low output impedance for the LNTA and thus reduced output conductance nonlinearity with less signal swings. Large-signal operation and distortion of the LNTA is mostly determined by the nonlinearity of the MOSFET transconductance in the LNTA. This paper deals with the design of two broadband inductorless fully balanced LNTAs with high large-signal linearity. A worst case 1-dB compression point(p1 db) of approximately 0 dbm for broadband operation in an environment of coexisting radios operatingsimultaneouslyincloseproximityisthekeyachievement. The proposed architecturesemploy noiseand distortion cancellation techniques, which make them suitable for broadband applications. Complementary RF characteristics of nmos and pmos transistors are utilized to improve the second-order input intercept point (IIP2) and third-order input intercept point (IIP3). The results shown in this paper have already been published in [7] and here we present detailed mathematicalanalyses. This paper is organized as follows. Section II introduces the proposed LNTA architecture. Section III discusses the design, tradeoffs, and the circuit implementation of the proposed LNTA architectures. Section IV discusses the measurement results and conclusions are drawn in Section V. II. LNTA ARCHITECTURE Blaakmeer et al. proposed noise-cancelling common-gate (CG) common-source (CS) balun LNA in [5], as shown in Fig. 2. The CS stage acts as an error-amplifier (EA) stage to cancel the noise/distortion (errors) of the input CG stage. This topology employed unequal transconductance gains in the CG and CS branches, as well as unequal output impedances to minimize the noise contribution of the CS stage. The unbalanced devices are sensitive to process variations and therefore degrade the differential operation of the entire receiver. Also, the NF degrades if equal s are employed in both branches of this topology under the same input matching constraints. Noise and distortion performance of this LNA is limited by the CS stage. Work reported in [11] improved the linearity of this amplifier topology by linearizing the CS stage with a linearization scheme proposed in [12]. It achieves good linearity, but still Fig. 2. Noise- and distortion-cancelling LNA [5]. Fig. 3. Fully balanced differential LNTA employing noise and distortion cancellation. suffers from high NF due to the use of equal load impedances for CG and CS stages. To improve the large-signal handling, [10] proposes a wide-swing LNTA, but it has lower or gain, thus demanding better noise performance from the following stages in a radio receiver. In this work, a fully balanced differential architecture with low NF and high linearity with large-signal operation is proposed. Fig. 3 shows the simplified schematic ofthe proposed LNTA. The CG transistors realizetheinputstage,whereasthecstransistors and realize the EA stage of the LNTA. A remarkable property of this configuration is that noise and distortion of the CG transistors appear as common-mode signals at the output and are cancelled in the differential output [5]. The input CG stage is employed to obtain wideband input matching and high linearity. The output signals of the CG stage are added with the EA signal through resistive dividers composed by.jussilaand Sivonen [13]usedinductorstocombine thesignals. III. CIRCUIT DESIGN A. Impedance Matching and Gain For the LNTA in Fig. 3, the input impedance is given as (1)

3 GEDDADA et al.: WIDE-BAND INDUCTORLESS LNTAs WITH HIGH LARGE-SIGNAL LINEARITY 1497 (2) (3) where is the input impedance of the next stage, as shown in Fig. 3, and is the intrinsic output impedance of the transistor. For the targeted architecture in Fig. 1,.Thus, ; hence, in (3). As in (2),. Parasitic capacitor at the source node of is moderately large and makes the pole as the dominant one in the system and limits the bandwidth of the LNTA. Major contributors of are given in (2). and are the gate source parasitic capacitors of and, respectively. is the parasitic shunt capacitance of ac coupling capacitor (metal oxide metal (MOM) capacitor), which could be large (15% 20% of ) depending on the lower cutoff frequency of the target bandwidth and the kind of capacitors available in the technology. In practice, a series bond-wire inductance from the package can be used to resonate out this input parasitic capacitance, and improve the LNTA bandwidth and. Simulation results of this effect are discussed in Section IV. Thus, wideband input impedance matching can be guaranteed until the effects of the parasitic capacitors limit the frequency response. B. Noise In order to calculate the noise factor of the LNTA, some simplifications are made to get some insightful results. The transistors are assumed to have infinite output impedance and the bias current source for the CG transistor is assumed to be ideal (final LNTA implementation does not include the bias current source). Only thermal noise from transistors and resistors are accounted. is the noise parameter in MOS transistors and is in the range of 2/3 2 for short channel devices. Noise from the gate resistance ( ) is ignored. The relative noise factor of each noise generating element is obtained as where,,and are the noise contributions from the CG stage, CS stage, and resistors, respectively, and is the effective transconductance from input to output. The topology s noise factor is then obtained as (4) (5) (6) (7) (8) Fig. 4. NF, voltage drop on with 1 ma in CG stage for. From (4), the condition for noise cancellation of the is stage Under this condition, (7) reduces to.inthetargeted receiver architecture, the impedance seen looking into the passive mixer is small compared to.thus,the output current of the EA is divided by the resistors and before reaching the output, as observed in (7). The effective transconductance of the LNTA is computed as ms. Therefore, the EA allows noise optimization and also boosts the architecture s gain from 20 to 40 ms. This helps to reduce some noise burden on the passive mixer and baseband in the receiver chain. AsshowninFig.2andgivenby(4), the noise contribution of the CG transistors results in a common-mode noise and gets cancelled in the differential output. The remaining noise present in the LNTA is due to the EA and the resistors. Using (5) and (6), and assuming that (9) holds, it can be shown that (9) (10) Fig. 4 shows the NF, voltage headroom (large signal linearity), and power tradeoff with respect to and. It can be seen from Fig. 4 that the NF improves with the increase in,but voltage headroom on the load resistance also increases, resulting in headroom issues for the proper operation of the transistors. From (10), while is independent of, decreases with an increase in resulting in less overall NF. Larger increases the voltage-drop on the load resistors,which decreases the linearity, but improves the NF. For a ms is around 1.4 ma for mv in this technology. Using (9) and for the equal in CG and CS transistors,. Total current consumption increases with an increase in. Therefore, increasing provides better noise performance at the cost of an increased power. Thus, an optimum and can be obtained for satisfying NF, voltage headroom, and the power. and are chosen in this design.

4 1498 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 62, NO. 7, JULY 2014 Fig. 6. Characterization setup for stacked PMOS NMOS pair. Fig. 5. Complete schematic of differential LNTA. TABLE I TRANSISTOR SIZES FOR THE SCHEMATIC IN FIG. 5 transistor s soft nonlinear model, the drain current of the nmos transistor is given by where,,and (11) Here, is the linear gain and, are the second- and third-order nonlinearity coefficients, respectively. From Fig. 6, in the present implementation of stacked PMOS NMOS stages, the nonlinear current in the pmos has the same expression, but with opposite polarity for. Thus,. The total output current from the single-ended input CG stage is given by C. Power-Efficient Design The schematic shown in Fig. 3 is transformed to power-efficient and high-linearity architecture keeping the noise and input matching properties unaltered. Fig. 5 shows the final transformed schematic of the LNTA. The core of this LNTA architecture consists of complimentary PMOS NMOS CG and CS stages. The input stage is implemented by a current reuse and combination to reduce the power consumption to improve the circuit linearity and to avoid the biasing inductors or any noise contribution from additional bias circuitry. The PMOS NMOS pair removes the even-order distortion components and third-order distortion due to second-order interaction, whichisdiscussedinthefollowingsection. The EA stage is also transformed to the current reuse PMOS NMOS pair. The source terminals of,,, and are connected together to make a single strong virtual ground as node in Fig. 5. The dc voltage values for the nodes and can be designed to have. Thus, this transformation to PMOS NMOS combination improves the architecture s power and linearity performance. The details are briefly explained in the following few sections. Dimensions of the transistor in Fig. 5 are given in Table I. D. Linearity Since the LNTA is driving a low impedance, the output voltage swing is assumed to be small, and hence, nonlinear effects of the transistor output conductance are negligible. The major source of nonlinearity stems from the transconductance of the LNTA. Using a power series expansion for the (12) where is the th harmonic current in the CG stage and the subscript and corresponds to nmos and pmos, respectively. From (12), PMOS NMOS combination reduces the even-order distortion coefficients. This can be seen from the PMOS NMOS characterization, as shown in Figs. 6 and 7. The current, of the individual transistors, and their combination is shown in Fig. 7(a). It can be seen that the combined is more linear than the individual s. Fig. 7(b) shows the derivative curves and second-order distortion reduction. LNTA output current will have third-order nonlinearity due to the third-order distortion in the CG stage, CS stage, and secondorder interaction between these two stages. Total differential third-order nonlinear current in the LNTA output current is given by (13) (14)

5 GEDDADA et al.: WIDE-BAND INDUCTORLESS LNTAs WITH HIGH LARGE-SIGNAL LINEARITY 1499 Fig. 8. IIP3 and P1 db of LNTA versus the load impedance [input impedance of the next stage (passive mixer TIA)]. Second-order interaction of the CG and CS stages also results in third-order intermodulation (IM3). Fundamental component and the second-order intermodulation (IM2) component (due to ) produced by the input CG stage experience second-order distortion of the CS stage and results in IM3 products [17], as given in (13). This IM3 contribution is alleviated by reducing the second-order distortion in the input CG [7]. As mentioned in [18] and also observed from (12), a PMOS NMOS pair in proper configuration has inherent cancellation, which reduces the second-order distortion. Fig. 7. (a) Current and transconductance of class AB push pull input stage. (b) Derivatives of in PMOS NMOS combination, input stage. where is the second-order distortion due to at node. From (13), three major sources of third-order nonlinearity in the LNTA are: 1) third-order distortion in input CG stage given by the first term; 2) third-order distortion in the CS stage given by the second term; and 3) secondorder interaction of CG and CS stages given by the last term. Third-order intermodulation (IM3) distortion due to third-order nonlinearity in the CG stage gets cancelled in a similar way as the noise (treating as a nonlinear current in Fig. 2) and becomes negligible in (13). Due to the horizontal and vertical electric fields, the mobility of carriers in a MOSFET degrades, resulting in nonlinear current [14, p. 589]. From the Taylor-series expansion of,the low-frequency expression for third-order distortion coefficient is given by (15) where and is the channel mobility degradation factor. Equation (15) assumes mobility degradation is dominated by vertical electric field. Higher s with maximum voltage head room is employed in the CS transistors of the EA to reduce its third-order distortion, in (13). 85% of the total power is consumed in the EA to decrease its noise and improve its linearity. for the CS transistors is also high, ensuring the nonlinearity from the output conductance is negligible. E. Large-Signal Operation The stacked PMOS NMOS input CG stage has wide signal operation capability [10]. Performance of this stage is boosted by employing the noise/distortion cancellation technique [5] by an EA. The employed EA also utilizes the stacked PMOS NMOS stage. Thus, voltage headroom limit on the P1 db is relaxed by maximizing the supply voltage on the stacked PMOS NMOS while meeting the reliability standards [15]. Thus, the proposed architecture inherently achieves high large-signal linearity. Current reuse in this stacked PMOS NMOS stages also reduces power consumption. A simulation showing the dependency of P1 db, IIP3, and power consumption on the load impedance of the LNTA isshowninfig.8.as increases, output voltage signal swing increases, increasing the output nonlinearities. It can be seen from the figure that the IIP3 and P1 db decrease with the increase in.beyond30, the output nonlinearities dominate the distortion products and thus degrade the LNTA linearity. For the current mode architectures, the load impedance can be as small as 5, achieving large IIP3 and P1 db. Even with as high as 30, the proposed architecture can easily achieve more than 0 dbm of P1 db and 11 dbm of IIP3. for the targeted receiver architecture is comprised of the ON resistanceofthepassivemixerswitch in series with the up-converted TIA input impedance. Assuming the major contributor for is, the amount of power consumedbythedriver driving the passive mixer with ON resistance is given by (16) (17)

6 1500 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 62, NO. 7, JULY 2014 Fig. 9. Simulation result showing the effect of nonlinearities on the noise floor in the presence of a large blocker. Switch size increases to decrease. Thus, the power required to drive the switch,, increases [10], which can be seen in Fig. 8. Besides, to have low baseband impedance, see Fig. 1), more power is needed to have high in the TIA. Fig. 9 displays the effect of nonlinearities on the noise floor in the presence of a large blocker for the proposed LNTA. Using a periodic steady-state (PSS) simulation, the noise is measured at 1 GHz in the presence of a large blocker at 1.1 GHz. The load impedance, of 30, is used in this simulation. The reduced output impedance of the PMOS/NMOS transistors when forced into the triode region also increases the noise contribution of the resistors. Due to the nonlinearity in the system, the large blocker up-converts some of the low-frequency noise to the signal band [10]. The system gets more nonlinear with large-signal swings, and thus the NF increases with blocker power. This dynamic simulation also confirms the large-signal capability of the LNTA with db with blocker power of 0 dbm. Beyond 0 dbm, the NF increases rapidly, as can be seen from the figure. The difference in the NF of the input CG stage without the CS stage and the LNTA is due to the noise cancelling. F. Stability and High Supply Voltage Reliability Given the multiple cross-connections in the circuit, the LNTA stability is investigated by means of the stability factor ( )and, which indicates unconditional stability if and for all frequencies [19]. As shown in Fig. 10, the minimum value of is found at low frequencies and increases with frequency, while the peak value of is less than 0.3. Targeting large linearity figures makes the use of higher supply voltages unavoidable [4]. Standard supply voltage for the employed 45-nm technology is 1.1 V, but in this design, in order to have sufficient headroom, a supply voltage of 2.2 V was used. This would assure that the voltage compression happens after the current compression, but proper precautions have to be taken to ensure reliability and chip lifetime. Terminal-to-terminal voltages should not exceed the reliability limits either during startup or normal operation. In Fig. 5, the CS node of the CS transistors in the EA stage is a near virtual ac ground with a dc voltage of V. Thus, each CS Fig. 10. Simulation result showing the effect of nonlinearities on the noise floor in the presence of a large blocker. transistor works under a dc supply voltage of.forthe CG transistors, the signal swing (polarity) at the drain follows that of the source terminal. Thus, the voltage does not go beyond the rated voltage. The signal swings are within the breakdown voltages of the active junctions of the transistors during the normal operation. Thus, no transistor is stressed with the increase in the supply voltage. Although a startup circuit is not explicitly implemented in the current design, a startup circuit similar to the one proposed in [4] can be used to give more reliability during the startup. G. Circuit Implementation and Statistical Behavior To have a lower NF at a moderate power consumption accordingtothenoiseanalysisinsectioniii-b, was chosen in this design. The CG input stage consumes 1 ma and sets ms for input matching. CS transistors in the EA stage consume 5.7 ma to achieve a NF of 2.5 db. of CS transistors is 145 mv to have less than third-order distortion according to (15). A proper ratio-metric design and symmetric layout procedure was followed to get the proper noise/distortion cancellation. Replica biasing is also used to bias the CG and CS transistors to give robustness to cancellation over process, voltage, and temperature (PVT) variations. A bias circuit, as shown in Fig. 11, is employed to bias the stacked PMOS NMOS in the input CG stage. Voltage, obtained through a resistive divider, is applied to the gates of and sets the voltage at in Fig. 5 to be near. A scaled version of the similar bias circuit is employed to bias the CS transistors. The robustness of the design to the PVT variations is investigated through Monte Carlo analysis. Over 400 runs, both process variations and in-wafer device mismatches, were considered. PVT variations are simulated on all LNTA components. Mean and standard deviation of the LNTA metrics are given in Table II. It can be noticed that is small for most of the parameters owing to the ratio metric design, replica biasing. A correlation factor of 0.9 is used for the resistors ( and )in the Monte Carlo simulation pertaining to the symmetric layout. H. Bulk-Driven LNTA Due to the use of higher supply voltage, the associated power consumption in the LNTA is moderately high even

7 GEDDADA et al.: WIDE-BAND INDUCTORLESS LNTAs WITH HIGH LARGE-SIGNAL LINEARITY 1501 Fig. 11. Bias circuit for CG and CS transistors. TABLE II 400-RUN MONTE CARLO STATISTICAL DISTRIBUTIONS Fig. 12. Low-power bulk-driven LNTA. TABLE III TRANSISTOR SIZES FOR THE SCHEMATIC IN FIG. 12 Data is taken at 1-GHz frequency for the LNTA1 though db dbm is achieved. To this end, a low-power technique using bulk-driven circuits [20] is used. As the employed technology is a triple-well process, a low-power bulk-driven LNTA, as shown in Fig. 12, is also designed that gives comparable performance at lower power. As the CS node of the transistors in the EA is a virtual ground and assuming, effective of the in the EA can be obtained from (18), where (18) From the above equation, it can be seen that the effective of in the EA is boosted by a factor. is the ratio of bulk transconductance to that of gate transconductance [14] and is in the order of in 45 nm. The boosting factor is further amplified by a gain factor, which is of the order 2. The gain factor is due to the amplification of the input signal by. Similar bulk-driven gain-boosting factors are associated with the other transistors in the EA. For this circuit, the EA transistor sizes and currents are scaled down to maintain the value of the original. Thus, scaling down the transistors with a bulk-driven boosting technique improves the power savings by 47% compared with the previous design. Dimensions of the transistors in Fig. 12 are given in Table III. Reliability has to be ensured as signal is injected into the bulk. For nmos transistors, as shown in Fig. 13(a), the bulk (P-well) is more negatively biased than its source and drain. From Fig. 12, it can be noticed that for transistors and, the voltage difference between the source and bulk terminals is less than zero. Thus, the diodes never turn on even for the 0-dBm signal as the is negative and large. The drain terminal is more positively biased than the source terminal. The bulk-drain diode is more negatively biased than the bulk-source diode so this diode also does not turn on. Fig. 13(b) shows the operating regions of the diodes (bulk-drain, bulk-source) of an nmos transistor ( or ).Asthebulkismorenegativebiased than the source and drain, the diodes never turn on even with a moderately large signal. On the other side, the diode s breakdown voltage is around 9 V, which is very high compared to the voltage signals associated with a 0-dBm signal. Similarly pmos bulks are connected to achieve high reliability. IV. TEST CHIP AND MEASUREMENT RESULTS The wideband LNTAs are fabricated in 45-nm technology and occupy an active area of 0.06 mm each. The chips are measured by on-wafer probing. Fig. 14 shows the chip micrograph of both LNTAs. No RF specific process options like a metal insulator metal (MIM) capacitor or thick metals are used. For test purposes, the LNTA is loaded with an on-chip output buffer that uses a dedicated power supply, as shown in Fig. 15. It isolates the LNTA output from the testing equipment. The output buffer is a resistive feedback amplifier with programmable gain. The simulated buffer bandwidth is greater than 8 GHz; is programmable in the 5 14-dB range, and db. The buffer operates in two gain modes to facilitate the measurement of the NF and linearity more accurately. The high-gain mode

8 1502 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 62, NO. 7, JULY 2014 Fig. 13. Reliability of bulk-driven LNTA at 0-dBm blocker. (a) Bulk-source and bulk-drain diodes. (b) Bias point of the diodes and voltage across the diodes at 0-dBm blocker. Fig. 16. Measured and for LNTA1. Fig. 14. Micrograph of the two proposed LNTAs occupying 0.06 mm each. Fig. 17. Measured of the LNTA1. with layout parasitics. An input bond wire inductance would improve the matching by resonating out the input parasitic capacitance. A simulation showing this improvement in matching and bandwidth extension with a series inductance of nh isalsoshowninthefigure. Measured and simulated of the LNTA is also shown in this figure. Low of 1.7 db (average) is measured as the LNTA is driving a low impedance 30. The transconductance gain is measured from the -parameters (19) Fig. 15. Tunable output buffer for measurements. is used to measure the NF, while the low-gain mode is used to measure linearity. and db are maintained in the buffer for both modes. The buffer is added for testing purposes only and its performance is de-embedded for reporting the final measurements. A four-port vector network analyzer (VNA) is employed to measure the input matching and gain of the differential circuits providing true differential-mode -parameters. Fig. 16 shows the measured input impedance matching of LNTA1. is better than 10 db up to 1.5 GHz. The measurement result is very close to the post layout simulations result where is the characteristic impedance ( differential) and are the measured differential -parameters. Measured is shown in Fig. 17. The small-signal variation is within 10% in the entire GHz bandwidth. The measured result is slightly less than the post-layout simulation due to the increase in parasitics at the output. Noise and linearity measurements require extra off-chip passive baluns for single-to-differential conversions. The NF is measured with the buffer in the high gain mode. Two external baluns at the input and output are employed and the NF is measured using a noise meter. High gain is required for good accuracy of the NF measurement. It also reduces the influence of any external noise sources at the output. The measured NF is less than 4.6 db in the GHz range and is shown in Fig. 18. Simulations showed that a series inductance of 1.5 nh

9 GEDDADA et al.: WIDE-BAND INDUCTORLESS LNTAs WITH HIGH LARGE-SIGNAL LINEARITY 1503 Fig. 18. Measured NF for LNTA1. Fig. 21. Measured P1 db for LNTA1 with output buffer in low-gain mode. Fig. 22. IIP3 and P1 db compression points at different frequency inputs. Fig. 19. Two-tone test for LNTA1 with input power of 15 dbm each (total 12 dbm) at 1 GHz with 1-MHz spacing. dbc. Fig. 20. IIP3 characterization for LNTA1 showing IIP3 of 10.8 dbm. Fig. 23. Complete test characterization of the low-power bulk-driven LNTA (lines: simulations; markers: measurements, series inductance of 1.5 nh at the input). would further extend the bandwidth and improve the NF by 0.6 db at 2 GHz. Low-frequency NF degradation is attributed to the off-chip baluns with lower cutoff frequency of around 500 MHz. The increase in the measured NF from the simulated is due to the decrease in the measured gain. Linearity is characterized by a two-tone test. To characterize the worst case nonlinearity, an OOB load impedance of is used at the output. For this setup, the result of a two-tone test is shown in Fig. 19. For the two test tones at 1 GHz with 1-MHz spacing and a total 12-dBm input power, the IM3 is found to be more than 47 dbm. A complete IIP3 characterization curve for the LNTA1 is depicted in Fig. 20 in which IIP3 of 10.8 dbm is measured. For most of the existing linearized LNAs in the literature [17], the third-order distortion quickly increases at moderately high power, but in this implementation, this effect is not seen (see Fig. 20). This is due to the targeted receiver architecture (less output nonlinearities) and inherent large-signal capability of the LNTA. Large-signal linearity characterization is done both by employing a VNA and a power meter. For this measurement, the

10 1504 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 62, NO. 7, JULY 2014 TABLE IV PERFORMANCE COMPARISON WITH EXISTING WORKS With (load) ; Internal gain graphically estimated; includes the power of the V-to-I converter; PowerofthecoreLNTA; active area; NF is shown in the GHz frequency band; simulation. output buffer is put in low gain mode with input impedance of 30. Fig. 21 shows the P1 db measurement of the LNTA1 from the VNA. The input power at 1.5 GHz is swept on the -axis and the power gain drops by 1 db when dbm. For accurate measurements, another set of P1 db measurements using a power meter were also recorded giving P1 db of 0 dbm. Remarkable large-signal linearity is demonstrated by the P1 db measurement over 0 dbm. The linearity measurements are taken at various frequency points and the high linearity is consistently achieved at all the in-band frequencies, as shown in Fig. 22. Higher linearity figures can be achieved for at the load as shown by the simulation in Fig. 8. The experimental results for the -boosted LNTA are depicted in Fig. 23. Similar performances were obtained: less than 10 db up to 2.4 GHz, overall is approximately 33 ms. The NF is under 5 db up to 3 GHz, while the P1 db is 0 dbm. Bandwidth is more than the LNTA1 as the devices are scaled down to save power, resulting in reduced parasitics. Table IV summarizes the most relevant inductorless wideband LNAs targeting high linearity. The dominant pole is located at the input. That is why even when the bulk with a large parasitic capacitor is connected at the output, the bandwidth did not decrease. Besides in the low-power bulk-driven prototype, the CS transistors are scaled down to have the same at reduced power consumption. This scaling also reduced the parasitic capacitance from the transistors. V. CONCLUSION The proposed LNTA architectures drastically reduce the noise/distortion contribution of the amplifier input stage to achieve remarkable linearity by employing current-reuse and push pull class-ab biasing while maintaining equal output impedances at the differential LNTA outputs. The proposed architectures achieve P1 db over 0 dbm within the entire GHz frequency band. Since the LNTA output is current, these architectures can be easily coupled to both passive mixers and Gilbert cells. ACKNOWLEDGMENT The authors would like to thank R. Bishop, Y. Tan, and J. Duster for the helpful discussions and support in the chip measurement. REFERENCES [1] D.Murphy,H.Darabi,A.Abidi,A.Hafez,A.Mirzaei,M.Mikhemar, and M.-C. Chang, A blocker-tolerant, noise-cancelling receiver suitable for wideband wireless applications, IEEE J. Solid-State Circuits, vol. 47, no. 12, pp , Dec [2] Z. Ru, N. Moseley, E. Klumperink, and B. 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Niknejad, and R. W. Brodersen, Design of a sub-mw 960-MHz UWB CMOS LNA, IEEE J. Solid-State Circuits, vol. 41, no. 11, pp , Nov [27] M. Mehrpoo and R. B. Staszewski, A highly selective LNTA capable of large-signal handling for RF receiver front-ends, in Proc. IEEE RFIC Symp., Jun. 2013, pp Hemasundar Mohan Geddada (S 11 M 14) received the B.Tech. (Hons.) degree from the Indian Institute of Technology (IIT) Kharagpur, India, in 2007, and the Ph.D. degree from Texas A&M University, College Station, TX, USA, in 2013, both in electrical engineering. During the summers of , he was with the Intel Corporation, Hillsboro, OR, USA, as a Graduate Research Intern involved with RF front-end circuits. His doctoral research was sponsored by the Semiconductor Research Corporation (SRC). He is currently with the Broadcom Corporation, Irvine, CA, USA, as a Staff II Scientist, where he is involved with wideband ADCs. He has authored or coauthored several papers. He holds two patents. His research interests include high-performance ADCs, transceiver systems, and circuit design at RF frequencies. Dr. Geddada was the corecipient of Best Student Paper Award of the 54th IEEE MWSCAS Conference, Seoul, Korea (2011). Chang-Tsung Fu (S 00 GSM 08 M 08) received the M.S. and Ph.D. degrees in electrical engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2001 and 2009, respectively. Since 2008, he has been with the Intel Corporation, Hillsboro, OR, USA, as a Research Scientist, where he is involved with critical circuit path finding for CMOS RF and analog circuits, RF system-on-chip (SoC) integration, and design methodology. He has authored or coauthored 14 conference or journal papers. He holds five issued and pending patents. His research include broadband noise matching theory, CMOS transmit/receive (T/R) switches, and high-linearity LNAs. Jose Silva-Martinez (SM 98 F 10) was born in Tecamachalco, Puebla, México. He received the Ph.D. degree from the Katholieke Univesiteit Leuven, Leuven, Belgium, in In 1992, he pioneered the graduate program on opto-electronics at the Universidad Autónoma de Puebla, Puebla, Mexico. In 1993, he joined the Electronics Department, INAOE, Puebla, Mexico, and from May 1995 to December 1998, he was the Head of the Electronics Department. In 1993, he was a cofounder of the Ph.D. program on electronics, INAOE. He is currently a Professor with the Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX, USA. He is the inaugural Holder of the Texas Instruments Professorship I in Analog Engineering, Texas A&M University ( ). He has authored or coauthored over 106 and 160 journal and conference papers, respectively, and 2 book and 12 book chapters. He currently serves on the Board of Editors of three major journals. He holds one patent. His current field of research is in the design and fabrication of integrated circuits for communication and biomedical applications. Dr. Silva-Martinez is the editor-in-chief of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II, EXPRESS BRIEFS ( ). He is a senior associate editor for the IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS ( ). He is a member of the CASS Distinguish Lecture Program. He is the conference co-chair of MWCAS He was the IEEE CASS vice president Region 9 ( ) and an associate editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: ANALOG AND DIGITAL SIGNAL PROCESSING ( and ). He was an associate editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS ( and ). He was the recipient of the 2005 Outstanding Professor Award of the Electrical and Computer Engineering Department, Texas A&M University. He was corecipient of MWCAS 2011 and RF-IC 2005 Best Student Paper Awards. He was the corecipient of the 1990 European Solid-State Circuits Conference Best Paper Award. Stewart S. Taylor (S 74 M 77 SM 99 F 08) received the B.S. degree in electronic engineering from the California Polytechnic State University, San Luis Obispo, CA, USA, in 1973, and the M.S. and Ph.D. degrees in electrical engineering from the University of California at Berkeley, Berkeley, CA, USA, in 1975 and 1978, respectively. He has developed high-speed analog, data converter, and wireless/rf integrated circuits with the Intel Corporation, Tektronix, TriQuint, and Maxim. He has taught on a part-time basis at Portland State University, Oregon State University, and the Oregon Graduate Institute for 30 years. He has authored or coauthored over publications. He holds 60 patents. Dr. Taylor has served on the Program Committee of the International Solid- State Circuits Conference for ten years. He has chaired the Analog Subcommittee for four years. He was the conference program chair in He was an associate editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS. He was the recipient of the IEEE Third Millennium Medal for Outstanding Achievements and Contributions of the Solid-State Circuits Society.