NCV7342. High Speed Low Power CAN Transceiver

Size: px

Start display at page:

Download "NCV7342. High Speed Low Power CAN Transceiver"

Terence Leonard
5 years ago
Views:

High Speed Low Power CAN Transceiver Description The NCV CAN transceiver is the interface between a controller area network (CAN) protocol controller and the physical bus and may be used in both V

1 High Speed Low Power CAN Transceiver Description The NCV CAN transceiver is the interface between a controller area network (CAN) protocol controller and the physical bus and may be used in both V and V systems. The transceiver provides differential transmit capability to the bus and differential receive capability to the CAN controller. The NCV is an addition to the CAN high speed transceiver family complementing NCVx CAN stand alone transceivers and previous generations such as AMIS, AMIS0x, etc. Due to the wide common mode voltage range of the receiver inputs and other design features, the NCV is able to reach outstanding levels of electromagnetic susceptibility (EMS). Similarly, extremely low electromagnetic emission (EME) is achieved by the excellent matching of the output signals. Features Compatible with the ISO 9, ISO 9 Standards High Speed (up to Mbps) Pin on NCV Version Allowing Direct Interfacing with V to V Microcontrollers V SPLIT Pin on NCV 0 Version for Bus Common Mode Stabilization Very Low Current Consumption in Standby Mode with Wake up via the Bus Excellent Electromagnetic Susceptibility (EMS) Level Over Full Frequency Range. Very Low Electromagnetic Emissions (EME) Low EME Also Without Common Mode (CM) Choke Bus Pins Protected Against > kv System ESD Pulses Transmit Data () Dominant Time out Function Bus Dominant Time out function in Standby Mode Under All Supply Condition the Chip Behaves Predictably No Disturbance of the Bus Lines with an Unpowered Node Thermal Protection Bus Pins Protected Against Transients in an Automotive Environment Bus Pins Short Circuit Proof to Supply Voltage and Ground These are Pb Free Devices Quality NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC Q00 Qualified and PPAP Capable Typical Applications Automotive Industrial Networks SOIC CASE AZ PIN ASSIGNMENT NCVD0RG (Top View) MARKING DIAGRAM NV x ALYW NV x= Specific Device Code x = 0 or A = Assembly Location L = Wafer Lot Y = Year W = Work Week = Pb Free Package (Note: Microdot may be in either location) NV 0 ALYW NV ALYW V SPLIT ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. NCVDRG (Top View) Semiconductor Components Industries, LLC, 0 December, 0 Rev. Publication Order Number: NCV/D

2 Table. KEY TECHNICAL CHARACTERISTICS AND OPERATING RANGES Symbol Parameter Conditions Min Max Unit Power supply voltage.. V V UVDVCC Undervoltage detection voltage on pin (NCV only).. V I CC Supply current Dominant; V = 0 V Recessive; V = 0 ma I CCS Supply current in standby mode including current T J 00 C, (Note ) A V DC voltage at pin 0 < <. V; no time limit 0 +0 V V DC voltage at pin 0 < <. V; no time limit 0 +0 V V,L DC voltage between and pin 0 < <. V 0 +0 V V ESD Electrostatic discharge voltage IEC 000 at pins and kv V O(dif)(bus_dom) Differential bus output voltage in dominant state < R LT <. V CM range Input common mode range for comparator Guaranteed differential receiver threshold and leakage current + V C load Load capacitance on IC outputs pf t pd0 t pd Propagation delay to (NCV 0 version) Propagation delay to (NCV version) See Figure 0 0 ns See Figure 0 0 ns T J Junction temperature 0 0 C. Not tested in production. Guaranteed by design and prototype evaluation.

3 BLOCK DIAGRAMS NCV 0 Timer Thermal Shutdown V SPLIT V SPLIT Mode & Wake up Driver Control Control Wake up Filter COMP COMP RB 009 Figure. NCV 0 Block Diagram

4 NCV Timer Thermal Shutdown Mode & Wake up Driver Control Control Wake up Filter COMP COMP RB 009 Figure. NCV Block Diagram

5 TYPICAL APPLICATION VBAT V reg V reg Micro Controller NCV R LT = 0 C LT =. nf R LT = 0 RB00 CAN BUS Figure. Application Diagram NCV VBAT IN V reg OUT R LT = 0 RB00 Micro Controller NCV 0 V C SPLIT LT =. nf R LT = 0 CAN BUS Figure. Application Diagram NCV 0 Table. PIN FUNCTION DESCRIPTION Pin Name Description Transmit data input; Low input dominant driver; internal pull up current Ground Supply voltage Receive data output; dominant transmitter Low output V SPLIT Input/Output pins supply voltage. On NCV only Common mode stabilization output. On NCV 0 only Low level CAN bus line (Low in dominant mode) High level CAN bus line (High in dominant mode) Standby mode control input

6 FUNCTIONAL DESCRIPTION NCV has two versions which differ from each other only by function of pin. NCV 0: Pin is common mode stabilization output V SPLIT. (see Figure ) This version is full replacement of NCV0. NCV : Pin is pin, which is supply pin for transceiver digital inputs/output (supplying pins,, ) The pin should be connected to microcontroller supply pin. By using supply pin shared with microcontroller, the I/O levels between microcontroller and transceiver are properly adjusted. This adjustment allows communication between V microcontroller and the transceiver. (See Figure ) Operating Modes NCV provides two modes of operation as illustrated in Table. These modes are selectable through pin. Table. OPERATING MODES Pin Mode Low Pin High Low Normal Bus dominant Bus recessive High Standby Wake up request detected No wake up request detected Normal Mode In normal mode, the transceiver is able to communicate via the bus lines. The signals are transmitted and received to the CAN controller via the pins and. The slopes on the bus lines outputs are optimized to give extremely low EME. Standby Mode In standby mode both the transmitter and receiver are disabled and a very low power differential receiver monitors the bus lines for CAN bus activity. The bus lines are terminated to ground and supply current is reduced to a minimum, typically 0 A. When a wake up request is detected by the low power differential receiver, the signal is first filtered and then verified as a valid wake signal after a time period of t dwakerd. The pin is driven Low by the transceiver to inform the controller of the wake up request. Supply Pin The pin (available only on NCV version) should be connected to microcontroller supply pin. By using supply pin shared with microcontroller the I/O levels between microcontroller and transceiver are properly adjusted. See Figure. Pin also provides the internal supply voltage for low power differential receiver of the transceiver. This allows detection of wake up request even when there is no supply voltage on Pin. Split Circuit The V SPLIT pin (available on NCV 0 version) is operational only in normal mode. In standby mode this pin is floating. The V SPLIT can be connected as shown in Figure or, if it s not used, can be left floating. Its purpose is to provide a stabilized DC voltage of 0. to the bus reducing possible steps in the common mode signal, therefore reducing EME. These unwanted steps could be caused by an unpowered node on the network with excessive leakage current from the bus that shifts the recessive voltage from its nominal 0. voltage. Wake up When a valid wake up (dominant state longer than t Wake ) is received during the standby mode, the pin is driven Low after t dwakerd. The wake up detection is not latched: returns to High state after t dwakedr when the bus signal is released back to recessive see Figure. >t Wake <t Wake t dwakerd t dwakedr normal standby RB009 time Figure. NCV Wake up behavior

7 Over temperature Detection A thermal protection circuit protects the IC from damage by switching off the transmitter if the junction temperature exceeds a value of approximately 0 C. Because the transmitter dissipates most of the power, the power dissipation and temperature of the IC is reduced. All other IC functions continue to operate. The transmitter off state resets when the temperature decreases below the shutdown threshold and pin goes High. The thermal protection circuit is particularly needed in case of a bus line failure. Dominant Time out Function A dominant time out timer circuit prevents the bus lines being driven to a permanent dominant state (blocking all network communication), if pin is forced permanently Low by a hardware and/or software application failure. The timer is triggered by a negative edge on pin. If the duration of the low level on pin exceeds the internal timer value t dom(), the transmitter is disabled, driving the bus into a recessive state. The timer is reset by a positive edge on pin. This dominant time out time (t dom() ) limits the minimum possible bit rate to kbps. Bus Dominant Time out Function Bus dominant time out timer is started in the standby mode when CAN bus changes from recessive to dominant state. If the dominant state on the bus is kept for longer time than t dom(bus), the pin is released to High level. The timer is reset when CAN bus changes from dominant to recessive state. This feature prevents generating permanent wake up request by the bus clamped to the dominant level. Fail Safe Features A current limiting circuit protects the transmitter output stage from damage caused by an accidental short circuit to either positive or negative supply voltage, although power dissipation increases during this fault condition. supply dropping below V UVDVCC undervoltage level will force transceiver to switch into the standby mode. The logic level on pin will be ignored as long as undervoltage condition is not recovered. (NCV version only) supply dropping below V UVDVIO undervoltage detection level will cause the transceiver to disengage from the bus (no bus loading) until the voltage recovers. (NCV version only) The pins and are protected against automotive electrical transients (according to ISO ; see Figure ). Pins and are pulled High internally should the input become disconnected. Pins, and will be floating, preventing reverse supply should the supply be removed.

8 ELECTRICAL CHARACTERISTICS Definitions All voltages are referenced to (pin ). Positive currents flow into the IC. Sinking current means the current is flowing into the pin; sourcing current means the current is flowing out of the pin. Table. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Conditions Min Max Unit V SUP Supply voltage, 0. V V DC voltage at pin 0 < <. V; no time limit 0 0 V V DC voltage at pin 0 < <. V; no time limit 0 0 V V,Lmax DC voltage at pin and during load dump condition 0 < <. V; less than one second V V SPLIT DC voltage at V SPLIT pin (On NCV 0 version only) 0 < <. V; no time limit 0 0 V DC voltage at pin,, 0. V V esd Electrostatic discharge voltage at all pins according to EIA JESD Standardized charged device model ESD pulses according to ESD STM Electrostatic discharge voltage at,, V SPLIT pins according to EIA JESD Electrostatic discharge voltage at, pins According to IEC 000 Note kv 0 0 V Note kv Note kv V schaff Transient voltage at, pins, See Figure Note 0 00 V Latch up Static latch up at all pins Note 0 ma T stg Storage temperature +0 C T amb Ambient temperature 0 + C T J Maximum junction temperature 0 +0 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. Standardized human body model electrostatic discharge (ESD) pulses in accordance to EIA JESD. Equivalent to discharging a 00 pf capacitor through a. k resistor.. System human body model electrostatic discharge (ESD) pulses. Equivalent to discharging a 0 pf capacitor through a 0 resistor referenced to. Verified by external test house. Pulses, a,a and b according to ISO part. Verification by external test house.. Static latch up immunity: Static latch up protection level when tested according to EIA/JESD. Table. THERMAL CHARACTERISTICS Symbol Parameter Conditions Value Unit R JA_ Thermal Resistance Junction to Air, S0P PCB (Note ) Free air K/W R JA_ Thermal Resistance Junction to Air, SP PCB (Note ) Free air K/W. Test board according to EIA/JEDEC Standard JESD, signal layer with 0% trace coverage.. Test board according to EIA/JEDEC Standard JESD, signal layers with 0% trace coverage.

9 Table. CHARACTERISTICS =. V to. V; =.V to. V (Note ); T J = 0 to +0 C; R LT = 0 unless specified otherwise. On chip versions without pin reference voltage for all digital inputs and outputs is instead of. Symbol Parameter Conditions Min Typ Max Unit SUPPLY (Pin ) I CC Supply current Dominant; V = 0 V Recessive; V = 0. 0 ma I CCS0 I CCS Supply current in standby mode for NCV 0 Supply current in standby mode for NCV including current into Undervoltage detection voltage on pin (NCV only) T J 00 C (Note 9) A T J 00 C (Note 9) A.. V TRANSMITTER DATA INPUT (Pin ) V IH High level input voltage Output recessive.0 V V IL Low level input voltage Output dominant V I IH High level input current V = 0 A I IL Low level input current V = 0V 00 A C i Input capacitance Not tested 0 pf TRANSMITTER MODE SELECT (Pin ) V IH High level input voltage Standby mode (Note 0) V V IL Low level input voltage Normal mode V I IH High level input current V = 0 A I IL Low level input current V = 0 V 0 A C i Input capacitance Not tested 0 pf RECEIVER DATA OUTPUT (Pin ) I OH High level output current Normal mode V = 0. V ma I OL Low level output current V = 0. V. ma V OH High level output voltage Standby mode I = 00 A V BUS LINES (Pins and ) V o(reces) (norm) Recessive bus voltage on pins and V = ; no load; normal mode.0..0 V V o(reces) (stby) Recessive bus voltage on pins and V = ; no load; standby mode mv I o(reces) () Recessive output current at pin 0 V < V < V; 0 V < <. V.. ma I o(reces) () Recessive output current at pin 0 V < V < V; 0 V < <. V.. ma I LI() Input leakage current to pin 0 < R( to ) < M A I LI() Input leakage current to pin 0 < R( to ) < M V = V = V (Note ) A V o(dom) () Dominant output voltage at pin V = 0 V.0.. V. Only version NCV has supply pin. In NCV 0 this supply is provided from pin. 9. Not tested in production. Guaranteed by design and prototype evaluation. 0.In case >, the limit is + 0. V 9

10 Table. CHARACTERISTICS =. V to. V; =.V to. V (Note ); T J = 0 to +0 C; R LT = 0 unless specified otherwise. On chip versions without pin reference voltage for all digital inputs and outputs is instead of. Symbol Parameter BUS LINES (Pins and ) V o(dom) () Dominant output voltage at pin Conditions Min Typ Max Unit V = 0 V 0... V V o(dif) (bus_dom) Differential bus output voltage (V V ) V = 0 V; dominant; < R LT <...0 V V o(dif) (bus_rec) Differential bus output voltage (V V ) V = ; recessive; no load mv V o(sym) (bus_dom) Bus output voltage symmetry V = 0 V 0.9. V + V I o(sc) () I o(sc) () Short circuit output current at pin Short circuit output current at pin V = 0 V; V = 0 V ma V = V; V = 0 V ma V i(dif) (th) Differential receiver threshold voltage V < V < V; V < V < V; =. V to. V V V ihcm(dif) (th) Differential receiver threshold voltage for high common mode 0 V < V < V; 0 V < V < V; =. V to. V V V i(dif) (th)_stdby Differential receiver threshold voltage in standby mode V < V < V; V < V < V; =. V to. V V R i(cm) () Common mode input resistance at pin k R i(cm) () Common mode input resistance at pin k R i(cm) (m) Matching between pin and pin common mode input resistance V = V % R i(dif) Differential input resistance 0 k C i() Input capacitance at pin V = ; not tested. 0 pf C i() Input capacitance at pin V = ; not tested. 0 pf C i(dif) Differential input capacitance V = ; not tested. 0 pf COMMON MODE STABILIZATION (Pin V SPLIT ) Only for NCV 0 version V SPLIT Reference output voltage at pin V SPLIT Normal mode; 00 A < I SPLIT < 00 A V SPLITo Reference output voltage at pin R loadvsplit > M V SPLIT I SPLIT(i) V SPLIT leakage current Standby mode A I SPLIT(lim) V SPLIT limitation current Normal mode. ma SUPPLY VOLTAGE (Pin ) Only for NCV version Supply voltage on pin.. V I IOS Supply current on pin Standby mode A I IONM Supply current on pin Normal mode Dominant; V = 0 V Recessive; V = ma. Only version NCV has supply pin. In NCV 0 this supply is provided from pin. 9. Not tested in production. Guaranteed by design and prototype evaluation. 0.In case >, the limit is + 0. V 0

11 Table. CHARACTERISTICS =. V to. V; =.V to. V (Note ); T J = 0 to +0 C; R LT = 0 unless specified otherwise. On chip versions without pin reference voltage for all digital inputs and outputs is instead of. Symbol Parameter SUPPLY VOLTAGE (Pin ) Only for NCV version V UVDVIO Undervoltage detection voltage on pin THERMAL SHUTDOWN Conditions Min Typ Max Unit.. V T J(SD) Shutdown junction temperature junction temperature rising C TIMING CHARACTERISTICS (See Figure and ) t d( BUSon) Delay to bus active C i = 00 pf between to t d( BUSoff) Delay to bus inactive C i = 00 pf between to 0 ns 0 ns t d(buson ) Delay bus active to C = pf 0 ns t d(busoff ) Delay bus inactive to C = pf 0 ns t pd_dr Propagation delay to dominant to recessive transition C i = 00 pf between to, C = pf ns t pd_rd Propagation delay to recessive to dominant transition C i = 00 pf between to, C = pf ns t d(stb nm) Delay standby mode to normal mode s t Wake Dominant time for wake up via bus 0. s t dwakerd Delay to flag wake event (recessive to dominant transitions) See Figure Valid bus wake up event, C = pf 0 s t dwakedr Delay to flag end of wake event (dominant to recessive transition) See Figure Valid bus wake up event, C = pf 0. s t dom() dominant time for time out V = 0 V. ms t dom(bus) Bus dominant time out Standby mode. ms. Only version NCV has supply pin. In NCV 0 this supply is provided from pin. 9. Not tested in production. Guaranteed by design and prototype evaluation. 0.In case >, the limit is + 0. V

12 MEASUREMENT SET UPS AND DEFINITIONS + V 00 nf nf NCV Transient Generator nf RB00 pf Figure. Test Circuit for Automotive Transients + V 00 nf uf NCV R L 00 pf RB00 pf Figure. Test Circuit for Timing Characteristics

13 recessive dominant recessive 0% 0% 0.9 V V i(dif) = V V 0. V 0. x * 0. x * t d( BUSon) t d(buson ) t d( BUSoff) t pd_rd *On NCV is replaced by t pd_dr t d(busoff ) RB009 Figure. Transceiver Timing Diagram DEVICE ORDERING INFORMATION NCVD0RG NCVDRG Part Number Description Package Shipping High Speed CAN Transceiver with Standby and V SPLIT pin High Speed CAN Transceiver with Standby and pin (available in 0) SOIC 0 GREEN (Matte Sn, JEDEC MS 0) (Pb Free) 000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD0/D.

14 PACKAGE DIMENSIONS SOIC CASE AZ ISSUE O

15 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box, Denver, Colorado 0 USA Phone: 0 or 00 0 Toll Free USA/Canada Fax: 0 or 00 Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: 00 9 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: 00 ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NCV/D

AMIS High-Speed Low Power CAN Transceiver

AMIS High-Speed Low Power CAN Transceiver AMIS- High-Speed Low Power CAN Transceiver Description The AMIS CAN transceiver is the interface between a controller area network (CAN) protocol controller and the physical bus and may be used in both