PRELIMINARY 1 REF VANA AGND1

Transcription

1 6-Bit Latchup Immune Analog to Digital Converter PRELIMINARY REF VANA AGND CAP 4R 4kohm 2.5V REFERENCE R IN R2 IN R3 IN 2R R 4R SWITCHED CAP ADC SERIAL DATA INTERFACE SYNC BUSY DATACLK DATA AGND2 R = 5kohm V DIG CONTROL LOGIC & INTERNAL CALIBRATION CIRCUITRY CLOCK DGND PWRD R/C CS TAG SB/BTC EXT/INT FUNCTIONAL BLOCK DIAGRAM FEATURES: RAD-PAK radiation-hardened against natural space radiation Total dose hardness: -> krad (Si), depending upon space mission SEL TH > 84 MEV Package: 24 pin RAD-PAK flat package khz min sampling rate ± V and V to 5 V input range DNL: 5-bits No Missing Codes 83 db min SINAD with 2 khz input +5 V supply operation Utilizes internal or eternal reference Serial output Power dissipation: mw ma DESCRIPTION: DDC s 6-bit ksps analog to digital converter features a greater than kilorad (Si) total dose tolerance depending upon space mission. Using DDC s radiation-hardened RAD-PAK packaging technology is SEL Immune. It is a 24 pin, 6-bit sampling analog-todigital converter. The contains a 6-bit capacitor based SAR A/D with S/H, reference, clock, interface for microprocessor use, and serial output drivers. The is specified at a khz sampling rate, and guaranteed over the full temperature range. Laser-trimmed scaling resistors provide various input ranges include ± V and to 5 V, while the innovative design allows operation from a single +5 V supply, with power dissipation of under 32 mw. DDC's patented RAD-PAK packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for bo shielding while providing the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, RAD-PAK provides greater than krad (Si) radiation dose tolerance. This product is available with screening up to DDC's self-defined Class S. It is DDC s policy to mark data sheets Preliminary until all parameter testing is complete to the full space temperature range

2 TABLE. PIN DESCRIPTION PIN SYMBOL DESCRIPTION RIN Analog Input. 2 AGND Analog Ground. Used internally as ground reference point. 3 R2IN Analog Input. 4 R3IN Analog Input. 5 CAP Reference Buffer Capacitor. 2.2 µf tantalum to ground. 6 REF Reference Input/Output. 2.2 µf tantalum capacitor to ground. 7 AGND2 Analog Ground. 8 SB/BTC Select Straight Binary or Binary Two s Complement data output format. If HIGH, data will be output in a Straight Binary format. If LOW, data will be output in a Binary Two s Complement format. 9 EXT/INT Select Eternal or Internal Clock for transmitting data. If HIGH, data will be out- put synchronized to the clock input on DATACLK. If LOW, a convert command will initiate the transmission of the data from the previous conversion, along with 6 clock pulses output on DATACLK. DGND Digital Ground. BITIN Connected to pin 2. 2 BITOUT Connected to pin. 3 VDIG Digital Supply Input. Nominally 5V. 4 VANA Analog Supply Input. Nominally 5V. 5 SYNC Sync Output. If EXT/INT is HIGH, either a rising edge on R/C with CS LOW or a falling edge on CS with R/C HIGH will output a pulse on SYNC synchronized to the eternal DATACLK. 6 DATACLK Either an input or an output depending on the EXT/INT level. Output data will be synchronized to this clock. If EXT/INT is LOW, DATACLK will transmit 6 pulses after each conversion, and then remain LOW between conversions. 7 DATA Serial Data Output. Data will be synchronized to DATACLK, with the format determined by the level of SB/ R/BTC. In the eternal clock mode, after 6-bits of data, the 789LOPO will output the level input of TAG as long as CS is LOW and R/C is HIGH. If EXT/INT is LOW, data will be valid on both the rising and falling edges of DATACLK, and between conversions DATA will stay at the level of the TAG input when the conversion was started. 8 TAG Tag input for use in eternal clock mode. If EXT/INT is HIGH, the digital data input on TAG will be output on DATA with a delay of 6 DATACLK pulses as long as CS is LOW and R/C is HIGH Rev 3 (see items in red) All data sheets are subject to change without notice 2

3 TABLE. PIN DESCRIPTION PIN SYMBOL DESCRIPTION 9 R/C Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sam- ple/hold into the hold state and starts a conversion. When EXT/INT is LOW, this also initiates the transmission of the data results from the previous conversion. If EXT/INT is HIGH, a rising edge on R/C with CS LOW, or a falling edge on CS with R/C HIGH, transmits a pulse on SYNC and initiates the transmission of data from the previous conversion. 2 CS 2 BUSY Chip Select. Internally OR ed with R/C. Busy Output. Falls when a conversion is started, and remains LOW until the conversion is completed and the data is latched into the output shift register. CS or R/C must be HIGH when BUSY rises, or another conversion will start without time for signal acquisition. 22 PWRD Power Down Input. If HIGH, conversions are inhibited and power consumption is significantly reduced. Results from the previous conversions are maintained in the output shift register. 23 VANA Analog Supply. 5V. 24 VDIG Digital Supply. 5V. TABLE 2. ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL MIN MAX UNIT Analog Inputs R IN R2 IN R3 IN CAP REF V ANA AGND2 -.3 Ground Voltage Differences: DGND, AGND V V ANA V DIG V V V V 7 V 7 V V DIG to V ANA -7 7 V Digital Inputs -.3 V DIG +.3 V Weight 7.8 Grams Thermal Resistance T JC 7.3 C/W Operating Temperature 2 T OPE C Storage Temperature T STG C. Indefinite short to AGND2, momentary short to V ANA. 2. Minimum Temperature is -4 C when using with an eternal reference Rev 3 (see items in red) All data sheets are subject to change without notice 3

4 TABLE 3. DC ACCURACY SPECIFICATIONS (SPECIFIED PERFORMANCE: -4 TO +85 C USING EXTERNAL REFERENCE) PARAMETER SUBGROUPS MIN TYP MAX UNIT Integral Linearity Error, 2, 3 ±3 LSB Differential Linearity Error, 2, LSB No Missing Codes 2 5 Bits Transition Noise 3. LSB Full Scale Error 4,5, 2, 3 ±.5 % Full Scale Error 4,5 (using et. 2.5 V ref ), 2, 3 ±.5 % Full Scale Error Drift ±7 ppm/ C Full Scale Error Drift (using et. 2.5 V ref ), 2, 3 ±2 ppm/ C Bipolar Zero Error 4, 2, 3 ± mv Bipolar Zero Error Drift ±2 ppm/ C Unipolar Zero Error 4, 2, 3 ± mv Me mo y Unipolar Zero Error Drift ±2 ppm/ C Recovery to Rated Accuracy after Power Down (2.2 uf Capacitor to CAP) ms Power Supply Sensitivity (V DIG = V ANA = V D ) 4.75 V < V D < 5.2 V, 2, 3 ±8 LSB. LSB stands for Least Significant Bit. One LSB is equal to 35 µv. 2. Not tested. 3. Typical rms noise at worst case transitions and temperatures. 4. Measured with various fied resistors. 5. For bipolar input ranges, full scale error is the worst case of -Full Scale or +Full Scale untrimmed deviation from ideal first and last scale code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. For unipolar input ranges, full scale error is the deviation of the last code transition divided by the transition voltage. It also includes the effect of offset error. TABLE 4. DELTA LIMITS PARAMETER VARIATION I CC +/- % Rev 3 (see items in red) All data sheets are subject to change without notice 4

5 TABLE 5. ANALOG INPUT AND THROUGHPUT SPEED (SPECIFIED PERFORMANCE: -4 TO +85 C USING EXTERNAL REFERENCE) PARAMETER SUBGROUPS MIN TYP MAX UNIT Voltage Ranges, 2, 3 V, V to 5 V, etc. See Table 2. Impedance, 2, 3 Capacitance 4 pf Complete Cycle (Acquire and Convert) 9,, µs Throughput Rate 2 9,, khz. Guaranteed by design. 2. Tested by application of signal. TABLE 6. AC ACCURACY SPECIFICATIONS (SPECIFIED PERFORMANCE: -4 TO +85 C USING EXTERNAL REFERENCE) PARAMETER SUBGROUPS MIN TYP MAX UNIT Spurious-Free Dynamic Range, f IN = 2 khz 4, 5, 6 9 db 2 Total Harmonic Distortion, f IN = 2 khz 4, 5, 6-9 db Signal-to-Noise (Noise + Distorsion) f IN = 2 khz -6 db Input 4, 5, 6 Signal-to-Noise, f IN = 2 khz db Full-Power Bandwidth,3 7 khz. Guaranteed by design (not tested). 2. All specifications in db are referred to a full-scale ± V input. 3. Full-Power Bandwidth defined as Full-Scale input frequency at which Signal-to-Noise (Noise + Distortion) degrades to 6 db db TABLE 7. SAMPLING DYNAMICS (SPECIFIED PERFORMANCE: -4 TO +85 C USING EXTERNAL REFERENCE) PARAMETER SUBGROUPS MIN TYP MAX UNIT Aperture Delay 4 ns Aperture Jitter 9,, Sufficient to meet AC specification Transient Response FS Step Z us Overvoltage Recovery 5 ns. Recovers to specified performance after 2 X FS input overvoltage Rev 3 (see items in red) All data sheets are subject to change without notice 5

6 PARAMETER CONDITIONS MIN TYP MAX UNIT Internal Reference Voltage No Load V Internal Reference Source Current (Must be et. buffer) Eternal Reference Voltage Range for Specified Linearity 2 TABLE 8. REFERENCE (SPECIFIED PERFORMANCE: -4 TO +85 C USING EXTERNAL REFERENCE) µa V Eternal Reference Current Drain Et. 2.5V Ref µa. Tested from -35C to +85C 2. Tested by application of signal. TABLE 9. DIGITAL OUTPUTS (SPECIFIED PERFORMANCE: -4 TO +85 C USING EXTERNAL REFERENCE) PARAMETER SUBGROUPS CONDITIONS MIN TYP MAX UNIT Data Format Data Coding Pipeline Delay Data Clock Internal (Output Only When Transmitting Data) Eternal (Can Run Continually) V OL V OH Leakage Current Serial 6-bits Binary Two s Complement or Straight Binary Conversion results only available after completed conversion Selectable for internal or eternal data clock 9,, EXT/INT Low EXT/INT High, 2, 3 I SINK =.6 ma I SOURCE = 5 µa High-Z State, ±6 µa V OUT = V to V DIG Output Capacitance High-Z State 5 pf. Not tested MHz V TABLE. DIGITAL INPUTS PARAMETER SUBGROUPS MIN TYP MAX UNIT V IL, 2, V V IH 2. V+.3 V I IL - I HL +/- ua Rev 3 (see items in red) All data sheets are subject to change without notice 6

7 TABLE. POWER SUPPLIES (SPECIFIED PERFORMANCE: -4 TO +85 C USING EXTERNAL REFERENCE) PARAMETER SUBGROUPS CONDITIONS MIN TYP MAX UNIT V DIG, 2, 3 Must be < V ANA V V ANA, 2, V I DIG 4 ma I ANA ma Icc, 2, 3 IDIG KHz Power Dissipation PWRD LOW PWRD HIGH, 2, 3 V ANA = V DIG = 5V f s = khz ma mw uw TABLE 2. CONTROL LINE FUNCTIONS FOR READ AND CONVERT SPECIFIC FUNCTION CS R/C BUSY EXT/INT DATACLK PWRD SB/BTC OPERATION Initiate Conversion and Output Data using Internal Clock > > Output Output Initiates conversion n. Data from conversion n- clocked out on DATA synchronized to 6 clock pulses output on DATA- CLK Initiates conversion n. Data from conversion n- clocked out on DATA synchronized to 6 clock pulses output on DATA- CLK Me mo y Rev 3 (see items in red) All data sheets are subject to change without notice 7

8 TABLE 2. CONTROL LINE FUNCTIONS FOR READ AND CONVERT SPECIFIC FUNCTION CS R/C BUSY EXT/INT DATACLK PWRD SB/BTC OPERATION Initiate Conversion and Output Data using Eternal Clock Incorrect Conversions Power Down ) Not Tested Selecting Output Format > > > > > Input Input Input Input Input Initiates conversion n Initiates conversion n Outputs a pulse on SYNC followed by data from conversion n clocked out synchronized to eternal DATACLK. Outputs a pules on SYNC followed by data from conversion n- clocked out synchronized to eternal DATACLK. Conversion n in process. Outputs a pulse on SYNC followed by data from conversion n- clocked out synchronized to eternal DATACLK. Conversion n in process. > CS or R/C must be HIGH or a new conversion will be initiated without time for acquisition Analog circuitry powered. Conversion will be initiated without time for acquisition Analog circuitry disabled. Data from previous conversion maintained in output registers Serial data is output in Binary Two s Complement format. Serial data is output in Straight Binary format.. See Figure 3 for constraints on previous data valid during conversion Rev 3 (see items in red) All data sheets are subject to change without notice 8

9 ANALOG INPUT RANGE TABLE 3. INPUT RANGE CONNECTION CONNECT R IN VIA 2Ω TO CONNECT R2 IN VIA Ω TO CONNECT R3 IN TO IMPEDANCE ±V V IN AGND CAP 22.9 kω ±5V AGND V IN CAP 3.3 kω ±3.3V V IN V IN CAP.7 kω V to V AGND V IN AGND 3.3kΩ V to 5V AGND AGND V IN. kω V to 4V V IN AGND V IN.7 kω TABLE 4. CONVERSION AND DATA TIMING (SPECIFIED PERFORMANCE: -4 TO +85 C USING EXTERNAL REFERENCE) SYMBOL DESCRIPTION SUBGROUPS MIN TYP MAX UNIT t Convert Pulse Width 9,, 5 ns t 2 t 3 t 4 BUSY Delay 9,, 83 ns BUSY LOW 9,, 8. µs BUSY Delay after End of Conversion 9,, 5 ns t 5 Aperture Delay 9,, 4 ns t 6 Conversion Time 9,, µs t 7 Acquisition Time 9,, 2 µs t 6 + t 7 Throughput Time 9,, µs t 8 R/C Low to DATACLK Delay 9,, 35 ns t 9 DATACLK Period 9,, 45 ns t Data Valid Setup Time 9,, ns t Data Valid Hold Time 9,, 2 ns t 2 Eternal DATACLK Period 9,, ns t 3 Eternal DATACLK HIGH 9,, 2 ns t 4 Eternal DATACLK LOW 9,, 3 ns t 5 t 6 R/C to CS EXT. DATACLK Setup Time 9,, 2 t2 + 5 ns R/C to CS Setup Time 9,, ns t 7 Eternal DATACLK to SYNC Delay 9,, 5 66 ns t 8 Eternal DATACLK to DATA Valid Delay 9,, ns t 9 t 2 t 2 t 22 CS to EXT. DATACLK Rising Edge Delay 9,, ns Previous Data Valid after CS, R/C LOW 9,, 7.5 µs BUSY to EXT. DATACLK Setup Time 9,, 5 µs Final EXT. DATACLK to BUSY Rising Edge 9,, 3.5 µs Rev 3 (see items in red) All data sheets are subject to change without notice 9

10 t 23 TAG Valid Setup Time 9,, ns t 24 TAG Valid Hold Time 9,, 2 ns TABLE ALP OUTPUT CODES AND IDEAL INPUT VOLTAGES DIGITAL OUTPUT DESCRIPTION ANALOG INPUT BINARY TWO S COMPLEMENT (SB/BTC LOW) STRAI=GHT BINARY (SB/BTC HIGH) BINARY CODE HEX CODE BINARY CODE HEX CODE Full Scale Range Least Significant Bit (LSB) + Full Scale (FS - LSB) ± ±5 ±3.33V V to V V to 5V V to 4V 35 µv 53 µv 2 µv 53 µv 76 µv 6 µv V V V V V V Midscale V V V 5V 2.5V 2V One LSB Below Midscale -35 µv -53 µv -2 µv V -Full Scale -V -5V V V V V V V 7FFF FFFF 8 FFFF 8 7FFF Rev 3 (see items in red) All data sheets are subject to change without notice

11 CONVERSION CONTROL The AD977 is controlled by two signals: R/C and CS. When R/C is brought low, with CS low, for a minimum of 5 ns, the input signal will be held on the internal capacitor array and a conversion n will begin. Once the conversion process does begin, the BUSY signal will go low until the conversion is complete. Internally, the signals R/C and CS are OR d together and there is no requirement on which signal is taken low first when initiating a conversion. The only requirement is that there be at least ns of delay between the two signals being taken low. After the conversion is complete the BUSY signal will return high and the AD977 will again resume tracking the input signal. Under certain conditions the CS pin can be tied Low and R/C will be used to determine whether you are initiating a conversion or reading data. On the first conversion, after the AD977 is powered up, the DATA output will be indeterminate. Conversion results can be clocked serially out of the AD977 using either an internal clock, generated by the AD977, or by using an eternal clock. The AD977 is configured for the internal data clock mode by pulling the EXT/INT pin low. It is configured for the eternal clock mode by pulling the EXT/INT pin high. CS, R/C t INTERNAL DATA CLOCK MODE The AD977 is configured to generate and provide the data clock when the EXT/INT pin is held low. Typically CS will be tied low and R/C will be used to initiate a conversion n. During the conversion the AD977 will output 6 bits of data, MSB first, from conversion n- on the DATA pin. This data will be synchronized with 6 clock pulses provided on the DATACLK pin. The output data will be valid on both the rising and falling edge of the data clock as shown in Figure 2. After the LSB has been presented, the DATA pin will assume whatever state the TAG input was at during the start of conversion, and the DATACLK pin will stay low until another conversion is initiated. EXTERNAL DATA CLOCK MODE The AD977 is configured to accept an eternally supplied data clock when the EXT/INT pin is held high. This mode of operation provides several methods by which conversion results can be read from the AD977. The output data from conversion n- can be read during conversion n, or the output data from conversion n can be read after the conversion is complete. The eternal clock can be either a continuous or discontinuous clock. A discontinuous clock can be either Me mo y t 3 BUSY t 2 t 5 t 4 MODE ACQUIRE CONVERT ACQUIRE CONVERT t 6 t 7 Figure. Basic Conversion Timing t 8 R/C t t 9 DATACLK t t DATA MSB VALID BIT 4 BIT 3 VALID VALID BIT VALID LSB VALID t 2 t 6 BUSY Figure 2. Serial Data Timing for Reading Previous Conversion Results with Internal Clock (CS, EXT/ INT and TAG Set to Logic Low) Rev 3 (see items in red) All data sheets are subject to change without notice

12 normally low or normally high when inactive. In the case of the discontinuous clock, the AD977 can be configured to either generate or not generate a SYNC output (with a continuous clock a SYNC output will always be produced). Each of the methods will be described in the following sections and are illustrated in Figures 4 through 9. It should be noted that all timing diagrams assume that the receiving device is latching data on the rising edge of the eternal clock. If the falling edge of DATACLK is used then, in the case of a discontinuous clock, one less clock pulse is required than shown in Figures 4 through 7 to latch in a 6-bit word. Note that data is valid on the falling edge of a clock pulse (for t 3 greater than t 8 ) and the rising edge of the net clock pulse. The AD977 provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion cycle. Normally the occurrence of an incorrect bit decision during a conversion cycle is irreversible. This error occurs as a result of noise during the time of the decision or due to insufficient settling time. As the AD977 is performing a conversion it is important that transitions not occur on digital input/output pins or degradation of the conversion result could occur. This is particularly important during the second half of the conversion process. For this reason it is recommended that when an eternal clock is being provided it be a discontinuous clock that is not toggling during the time that BUSY is low or, more importantly, that it does not transition during the latter half of BUSY low. EXTERNAL DISCONTINUOUS CLOCK DATA READ AFTER CONVERSION NO SYNC OUTPUT GENERATED Figure 3 illustrates the method by which data from conversion n can be read after the conversion is complete using a discontinuous eternal clock without the generation of a SYNC output. After a conversion is complete, indicated by BUSY returning high, the result of that conversion can be read while CS is Low and R/C is high. In this mode CS can be tied low. The MSB will be valid on the first falling edge and the second rising edge of DATACLK. The LSB will be valid on the 6th falling edge and the 7th rising edge of DATACLK. A minimum of 6 clock pulses are required for DATACLK if the receiving device will be latching data on the falling edge of DATACLK. A minimum of 7 clock pulses are required for DATACLK if the receiving device will be latching data on the rising edge of DATACLK. Approimately 4 ns after the 7th rising edge of DATACLK (if provided) the DATA output pin will reflect the state of the TAG input pin during the first rising edge of DATACLK. The advantage of this method of reading data is that it is not being clocked out during a conversion and therefore conversion performance is not degraded. When reading data after the conversion is complete, with the highest frequency permitted for DATACLK (5.5 MHz). For details on use of the TAG input with this mode see the Use of the Tag Feature section. t 3 t 2 t 4 EXT DATACLK t R/C t 2 BUSY t 2 SYNC t 8 t 8 DATA BIT 5 (MSB) BIT 4 BIT 3 BIT BIT (LSB) TAG TAG t 23 t 24 TAG TAG TAG TAG 2 TAG 3 TAG 5 TAG 6 TAG 7 TAG 8 Figure 3. Conversion and Read Timing Using an Eternal Discontinuous Data Clock (EXT/ INT Set to Logic High, CS Set to Logic Low) Rev 3 (see items in red) All data sheets are subject to change without notice 2

13 EXTERNAL DISCONTINUOUS CLOCK DATA READ DURING CONVERSION NO SYNC OUTPUT GENERATED Figure 4 illustrates the method by which data from conversion n- can be read during conversion n while using a discontinuous eternal clock, without the generation of a SYNC output. After a conversion is initiated, indicated by BUSY going low, the result of the previous conversion can be read while CS is low and R/C is high. In this mode CS can be tied low. The MSB will be valid on the st falling edge and the 2nd rising edge of DATACLK. The LSB will be valid on the 6th falling edge and the 7th rising edge of DATACLK. A minimum of 6 clock pulses are required for DATACLK if the receiving device will be latching data on the falling edge of DATACLK. A minimum of 7 clock pulses are required for DATACLK if the receiving device will be latching data on the rising edge of DATACLK. Approimately 4 ns after the 7th rising edge of DATACLK (if provided) the DATA output pin will reflect the state of the TAG input pin during the first rising edge of DATACLK. The data should be clocked out during the first half of BUSY so not to degrade conversion performance. This requires use of a 4.8 MHz DATACLK or greater with data being read out as soon as the conversion process begins. It is not recommended that data be shifted through the TAG input in this mode as it will certainly result in clocking of data during the second half of the conversion. EXTERNAL DISCONTINUOUS CLOCK DATA READ AFTER CONVERSION WITH SYNC OUTPUT GENERATED Figure 5 illustrates the method by which data from conversion n can be read after the conversion is complete using a discontinuous eternal clock, with the generation of a SYNC output. What permits the generation of a SYNC output is a transition of DATACLK while either CS is high or while both CS and R/C are low. After a conversion is complete, indicated by BUSY returning high, the result of that conversion can be read while CS is Low and R/C is high. In this mode CS can be tied low. In Figure 5 clock pulse # is used to enable the generation of a SYNC pulse. The SYNC pulse is actually clocked out approimately 4 ns after the rising edge of clock pulse #. The SYNC pulse will be valid on the falling edge of clock pulse # and the rising edge of clock pulse #2. The MSB will be valid on the falling edge of clock pulse #2 and the rising edge of clock pulse #3. The LSB will be valid on the falling edge of clock pulse #7 and the rising edge of clock pulse #8. Approimately 4 ns after the rising edge of clock pulse #8 the DATA output pin will reflect the state of the TAG input pin during the rising edge of clock pulse #2. The advantage of this method of reading data is that it is not being clocked out during a conversion and therefore conversion performance is not degraded. When reading data after the conversion is complete, with the highest frequency permitted for DATACLK (5.5 MHz), and the maimum possible throughput is approimately 95 khz and not the rated 2 khz. For details on use of the TAG input with this mode see the Use of the TAG Input section. t 3 t 2 t 4 EXT DATACLK t 5 t 22 R/C t t 2 BUSY t 2 t 2 SYNC t 8 t 8 DATA BIT 5 (MSB) BIT 4 BIT (LSB) Figure 4. Conversion and Read Timing for Reading Previous Conversion Results During A Conversion Using Eternal Discontinuous Data Clock (EXT/ INT Set to Logic High, CS Set to Logic Low) Rev 3 (see items in red) All data sheets are subject to change without notice 3

14 t 3 t 2 t4 EXT DATACLK t 5 t 5 t 5 R/C t 2 BUSY t 7 SYNC t 2 t 8 t 8 DATA BIT 5 (MSB) BIT 4 BIT (LSB) TAG TAG TAG 2 t 23 t 24 TAG TAG TAG TAG 2 TAG 6 TAG 7 TAG 8 TAG 9 Figure 5. Conversion and Read Timing Using An Eternal Discontinuous Data Clock (EXT/ INT Set to Logic High, CS Set to Logic Low) EXTERNAL DISCONTINUOUS CLOCK DATA READ DURING CONVERSION WITH SYNC OUTPUT GENERATED Figure 6 illustrates the method by which data from conversion n- can be read during conversion n while using a discontinuous eternal clock, with the generation of a SYNC output. What permits the generation of a SYNC output is a transition of DATACLK while either CS is High or while both CS and R/C are low. In Figure 6 a conversion is initiated by taking R/C low with CS tied low. While this condition eists a transition of DATACLK, clock pulse #, will enable the generation of a SYNC pulse. Less then 83 ns after R/C is taken low the BUSY output will go low to indicate that the conversion process has began. Figure 6 shows R/C then going high and after a delay of greater than 5 ns (t 5 ) clock pulse # can be taken high to request the SYNC output. The SYNC output will appear approimately 4 ns after this rising edge and will be valid on the falling edge of clock pulse # and the rising edge of clock pulse #2. The MSB will be valid approimately 4 ns after the rising edge of clock pulse #2 and can be latched off either the falling edge of clock pulse #2 or the rising edge of clock pulse #3. The LSB will be valid on the falling edge of clock pulse #7 and the rising edge of clock pulse #8. Approimately 4 ns after the rising edge of clock pulse #8, the DATA output pin will reflect the state of the TAG input pin during the rising edge of clock pulse #2. t 3 t 2 t 4 EXT DATACLK t 5 t 5 t 22 R/C t t 2 BUSY t 2 t7 SYNC t 2 t 8 t 8 DATA BIT 5 (MSB) BIT 4 BIT (LSB) TAG Figure 6. Conversion and Read Timing for Reading Previous Conversion Results During a Conversion Using Eternal Discontinuous Data Clock (EXT/ INT Set to Logic High, CS Set to Logic Low) Rev 3 (see items in red) All data sheets are subject to change without notice 4

15 t 23 t 24 6-Bit Latchup Immune Analog to Digital Converter The data should be clocked out during the first half of BUSY so not to degrade conversion performance. This requires use of a 4.8 MHz DATACLK or greater, with data being read out as soon as the conversion process begins.. It is not recommended that data be shifted through the TAG input in this mode as it will certainly result in clocking of data during the second half of the conversion. EXTERNAL CONTINUOUS CLOCK DATA READ AFTER CONVERSION WITH SYNC OUTPUT GENERATED Figure 7 illustrates the method by which data from conversion n can be read after the conversion is complete using a continuous eternal clock, with the generation of a SYNC output. What permits the generation of a SYNC output is a transition of DATACLK while either CS is high or while both CS and R/C are low. With a continuous clock the CS pin cannot be tied low as it could be with a discontinuous clock. Use of a continuous clock, while a conversion is occurring, can increase the DNL and Transition Noise of the AD977. After a conversion is complete, indicated by BUSY returning high, the result of that conversion can be read while CS is low and R/C is high. In Figure 7 clock pulse # is used to enable the generation of a SYNC pulse. The SYNC pulse is actually clocked out approimately 4 ns after the rising edge of clock pulse #. The SYNC pulse will be valid on the falling edge of clock pulse # and the rising edge of clock pulse #2. The MSB will be valid on the falling edge of clock pulse #2 and the rising edge of clock pulse #3. The LSB will be valid on the falling edge of clock pulse #7 and the rising edge of clock pulse #8. Approimately 5 ns after the rising edge of clock pulse #8 the DATA output pin will reflect the state of the TAG input pin during the rising edge of clock pulse #2. For details on use of the TAG input with this mode see the Use of the TAG Input section. t 2 t 4 t 3 EXT DATACLK t t 5 t 9 CS t 6 R/C t 2 t 6 BUSY t 7 SYNC t 2 t 8 t 8 DATA BIT 5 (MSB) BIT 4 BIT (LSB) TAG TAG TAG 2 TAG TAG TAG TAG 2 TAG 6 TAG 7 TAG 8 TAG 9 Figure 7. Conversion and Read Timing Using an Eternal Continuous Data Clock (EXT/ INT Set to Logic High) Rev 3 (see items in red) All data sheets are subject to change without notice 5

16 EXTERNAL CONTINUOUS CLOCK DATA READ DURING CONVERSION WITH SYNC OUTPUT GENERATED Figure 8 illustrates the method by which data from conversion n- can be read during conversion n while using a continuous eternal clock with the generation of a SYNC output. What permits the generation of a SYNC output is a transition of DATACLK while either CS is high or while both CS and R/C are low. With a continuous clock the CS pin cannot be tied low as it could be with a discontinuous clock. Use of a continuous clock while a conversion is occurring can increase the DNL and Transition Noise of the AD977. In Figure 8 a conversion is initiated by taking R/C low with CS held low. While this condition eists a transition of DATACLK, clock pulse #, will enable the generation of a SYNC pulse. Less than 83 ns after R/C is taken low the BUSY output will go low to indicate that the conversion process has begun. Figure 8 shows R/C then going high and after a delay of greater than 5 ns (t 5 ), clock pulse # can be taken high to request the SYNC output. The SYNC output will appear approimately 5 ns after this rising edge and will be valid on the falling edge of clock pulse # and the rising edge of clock pulse #2. The MSB will be valid approimately 4 ns after the rising edge of clock pulse #2 and can be latched off either the falling edge of clock pulse #2 or the rising edge of clock pulse #3. The LSB will be valid on the falling edge of clock pulse #7 and the rising edge of clock pulse #8. Approimately 4 ns after the rising edge of clock pulse #8, the DATA output pin will reflect the state of the TAG input pin during the rising edge of clock pulse #2. The data should be clocked out during the st half of BUSY so as not to degrade conversion performance. This requires use of a 4.8 MHz DATACLK or greater with data being read out as soon as the conversion process begins.. t 2 t 3 t 4 EXT DATACLK t 9 CS t 6 t 5 R/C t t 2 BUSY t 2 t7 SYNC t 2 t 8 t 8 DATA BIT 5 (MSB) BIT (LSB) TAG TAG TAG 2 t 23 t 24 TAG TAG TAG TAG 6 TAG 7 TAG 8 TAG 9 Figure 8. Conversion and Read Timing for Reading Previous Conversion Results During a Conversion Using An Eternal Continuous Data Clock (EXT/ INT Set to Logic High) Rev 3 (see items in red) All data sheets are subject to change without notice 6

17 USE OF THE TAG INPUT The AD977 provides a TAG input pin for cascading multiple converters together. This feature is useful for reducing component count in systems where an isolation barrier must be crossed and is also useful for systems with a limited capacity for interfacing to a large number of converters. The tag feature only works in the eternal clock mode and requires that the DATA output of a upstream device be con- nected to the TAG input of an downstream device. An eample of the concatenation of two devices is shown in Figure 27 and their resultant output is shown in Figure 28. In Figure 27, the paralleled R/C ensures that each AD977 will simultaneously sample their inputs. In Figure 28, a null bit is shown between each 6-bit word associated with each ADC in the serial data output stream. This is the result of a minimum value for Eternal Data Clock to Data Valid Delay (t8) that is greater than the TAG Valid Setup Time (t23). In other words, when you concatenate two or more AD977s the MSB on the downstream device will not be present on thetag input of the upstream device in time to meet the setup time requirement of the TAG input. Figure 27. Two AD977 s Utilizing Tag If the serial data stream is going to a parallel port of a microprocessor that is also providing the serial data clock, then the microprocessor s firmware can be written to throw away the null bit. If the serial data stream is going to a serial port then eternal glue logic will have to be added to make the interface work. If the serial port has a sync input then this can be used to throw away the null bit if the sync input is toggled each time the null bit appears. If the application does not require simultaneous sampling, the null bit can be completely avoided by delaying the R/C signal of each upstream device by one clock cycle with respect to its immediate downstream device. This bit time delay can be accomplished through a D- type flip-flop that delays the R/C signal at its D-input by one cycle of the serial data clock that is at its clock input. Figure 28. TAG Timing Diagram for Two Concatenated AD977s It is not recommended that the TAG feature be used with the read during convert mode because this will require data to be clocked out during the second half of the conversion process. It is recommended that the read after convert mode be used in an application that wants to take advantage of the TAG feature. To improve the data throughput a combination of the two data read methods can be used and is described as follows. If two or more AD977s are to have their data output concatenated together in a single data stream, and if data throughput is to be maimized, a system could be designed such that the upstream device data is read during the first half of its conversion process and the remainder of the downstream devices read during the time between conversions. Assume three AD977s are to have their data concatenated. Assume the further most downstream device is referred to as device # and the further most upstream device as #3. Each device is driven from a com- mon DATACLK and R/C control signal, the CS input of each device is tied to ground. The three BUSY outputs should be OR d together to form a composite BUSY. After the conversion is complete, as indicated by the composite BUSY going high, an eternal, normally low, 5.5 MHz DATACLK can be toggled 34 times to first read the data first from device #3 and then from device #2. When the composite BUSY goes low to indicate the beginning of the conversion process the eternal DATA- CLK can be toggled 7 times to read the data from device # during the first half of the conversion process. Using this technique it would be possible to read in the data from the three devices in approimately 6.4 µs for a throughput of approimately 56 khz The receiving device would have to deal with the null bit between data from device #2 and #3. The receiving device would also have to be capable of starting and stopping the eternal DATACLK at the appropriate times. The TAG input, when unused, should always be tied either high or low and not be allowed to float Rev 3 All data sheets are subject to change without notice 7

18 24-PIN RAD-PAK FLAT PACKAGE Me mo y SYMBOL DIMENSION MIN NOM MAX A b c.6.8. D.6.66 E E.44 E E e.5 BSC L Q S.6.4 N 24 Note: All dimensions in inches Top and Bottom of package internally connected to ground Rev 3 All data sheets are subject to change without notice 8

19 Product Ordering Options Model Number RP F X Feature Option Details Screening Flow Monolithic S = DDC Self-Defined Class S B = DDC Self-Defined Class B I = Industrial -4 C, +25 C, +85 C) E = Engineering +25 C Package F = Flat Pack Radiation Feature RP = RAD-PAK package Base Product Nomenclature 6-Bit Latchup Protected Analog to Digital Converter Products are manufactured and screened to DDC s self-defined Class B and Class S flows Rev 3 All data sheets are subject to change without notice 9

20 6-Bit Latchup Immune Analog to Digital Converter Important Notice: These data sheets are created using the chip manufacturers published specifications. DDC verifies functionality by testing key parameters either by % testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and DDC assumes no responsibility for the use of this information. DDC's products are not authorized for use as critical components in life support devices or systems without epress written approval from DDC. Any claim against DDC must be made within 9 days from the date of shipment from DDC. DDC s liability shall be limited to replacement of defective parts Rev 3 All data sheets are subject to change without notice 2