Practical PDH Higher Order Systems

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June Cunningham
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1 Chapter ractical DH Higher Order ystems. Examples of word interleaving he following diagram shows how four primary CM systems. are multiplexed into one higher order. Mbps. Here one should bear in mind that s are read in primary tributary, in the higher order CM in addition to this s s will be sent. his means for every time slots for four primary tributaries one time slot of s will be made in the higher order CM in addition to all * time slots pertaining to the four primary CM systems. It is easy to visualize this concept that is been deployed word interleaving as explained earlier.

2 M BI FRAME RUCURE (Word Interleaving) Figure:. rimary CM s. Mbps µs Frame ynchronization ynchronization pare XX Note: In Mbps CM there are in µs

3 . Examples of Bit Interleaving Bit interleaving is practically used in the lesiochronous Digital Hierarchical system. When primary tributaries originating from different locations, reaching to a multiplexing location has undergone different technical and path conditions before arriving to the multiplexing location. Also these tributaries can have minute time differences of the clock pulses as well as minute differences of clock speed. All these primary CMs has to be scanned or to be unified to a constant speed of a secondary CM and after demultiplexing the same timing characteristics should be maintained as the output of the demultiplexer. How to analyze the differences of the primary tributary to be placed in the Higher Order CM has to be analyzed for the practical CM systems. his analysis is named as justification.. Justification If f p is the primary tributary speed and the secondary equivalent tributary speed is f s. Ideally f p = f s will result in no loss/addition of s in the higher order CM. his is named as Zero Justification. If f p > f s there is a tendency to scan one primary as secondary s in the higher order. his is named as ositive Justification. In contrary if f p < f s there is a tendency has one primary to be absent in the secondary tributary. his is named as Negative Justification. But due to the introduction of s at the multiplexing point ( f p < f s ) always in the DH systems one can observe only ositive Justification.. Let s assume. Mbps of primary ributary has to be scanned in. Mbps into the secondary tributary (.=./). his may lead to introduce one more into the higher order CM when scanning more s in the primary tributary. In the practical DH systems of to Ms a algorithm is utilized to verify whether is added in the secondary tributary as a false and this will be identified by testing four sets around s each set in s. his is shown as follows. In one tributary take s and analyze whether there is a probability of introduction of an additional due to positive Justification, justification control pertaining to that tributary will be made positive (). hen the second set pertaining to that tributary is again analyzed for positive justification and the probability is noted in the second justification control s either one or zero depending up on the likelihood of introduction of a additional,. A similar exercise will be carried out for the third set of s and accordingly justification control s will be made one or zero. All these Justification Control s resulting in majority of ones will indicate not to consider th (justified timeslots) to be ignored by the de-multiplexer when demultiplexing to the primary tributary. his is illustrated as follows.

4 et F F F F F F F F F F A M th Bit th Bit et G G G G th Bit st Bit st Bit et G G G G nd Bit rd Bit rd Bit et G G G G B B B B th Bit / th Bit / th Bit If we consider one CM th th Hence total of / s will be taken from each CM. Note: Of we start with No., total of or will be taken) st rd th lease note only CM has been indicated in color and other CMs are not shown any color. For CM,, and justification control s and justified s ( th time slot) are indicated in respectively. If set, set, et justification Control s are G respectively then th B Is ignored. Or another example If Justification Control Bits are respectively th will be an actual. Figure:.

5 If the majority of the Justification Control s are Ones the output of de-multiplexer will be sending only s while for another tributary with the majority of justification control s are zero the output of the de-multiplexer will be sending s. o that the speed of the primary tributaries will be maintained after the Higher Order Demultiplexing.

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