Power MOSFET FEATURES BENEFITS. IRFP22N60KPbF SiHFP22N60K-E3 IRFP22N60K SiHFP22N60K

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1 Power MOSFET IRFP22N60K, SiHFP22N60K PRODUT SUMMRY V DS (V) 600 R DS(on) ( ) V GS = V 0.2 Q g (Max.) (n) 150 Q gs (n) 5 Q gd (n) 76 onfiguration Single TO-27 S G D ORDERING INFORMTION Package Lead (Pb)-free SnPb G D S N-hannel MOSFET FETURES Low Gate harge Q g Results in Simple Drive Requirement Improved Gate, valanche and Dynamic dv/dt Ruggedness Fully haracterized apacitance and valanche Voltage and urrent Enhanced Body Diode dv/dt apability ompliant to RoHS Directive 2002/95/E BENEFITS Hard Switching Primary or PFS Switch Switch Mode Power Supply (SMPS) Uninterruptible Power Supply High Speed Power Switching Motor Drive TO-27 IRFP22N60KPbF SiHFP22N60K-E3 IRFP22N60K SiHFP22N60K vailable RoHS* OMPLINT BSOLUTE MXIMUM RTINGS (T = 25, unless otherwise noted) PRMETER SYMBOL LIMIT UNIT Drain-Source Voltage V DS 600 V Gate-Source Voltage V GS ± 30 ontinuous Drain urrent V GS at V T = I D T = 0 1 Pulsed Drain urrent a I DM 88 Linear Derating Factor 2.9 W/ Single Pulse valanche Energy b E S 380 mj Repetitive valanche urrent a I R 22 Repetitive valanche Energy a E R 37 mj Maximum Power Dissipation T = 25 P D 370 W Peak Diode Recovery dv/dt c dv/dt 15 V/ns Operating Junction and Storage Temperature Range T J, T stg - 55 to 150 Soldering Recommendations (Peak Temperature) for s 300 d Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Starting T J = 25, L = 1.5 mh, R g = 25, I S = 22 (see fig. 12). c. I SD 22, di/dt 360 /μs, V DD V DS, T J 150. d. 1.6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: S11-05-Rev. B, 21-Mar-11 1 THE PRODUT DESRIBED HEREIN ND THIS DTSHEET RE SUBJET TO SPEIFI DISLIMERS, SET FORTH T

2 IRFP22N60K, SiHFP22N60K THERML RESISTNE RTINGS PRMETER SYMBOL TYP. MX. UNIT Maximum Junction-to-mbient R thj - 0 ase-to-sink, Flat, Greased Surface R ths /W Maximum Junction-to-ase (Drain) R thj SPEIFITIONS (T J = 25, unless otherwise noted) PRMETER SYMBOL TEST ONDITIONS MIN. TYP. MX. UNIT Static Drain-Source Breakdown Voltage V DS V GS = 0 V, I D = 250 μ V V DS Temperature oefficient V DS /T J Reference to 25, I D = 1 m d V/ Gate-Source Threshold Voltage V GS(th) V DS = V GS, I D = 250 μ V Gate-Source Leakage I GSS V GS = ± 30 V - - ± 0 n V DS = 600 V, V GS = 0 V Zero Gate Voltage Drain urrent I DSS V DS = 80 V, V GS = 0 V, T J = μ Drain-Source On-State Resistance R DS(on) V GS = V I D = 13 b Forward Transconductance g fs V DS = 50 V, I D = 13 b S Dynamic Input apacitance iss V GS = 0 V, Output apacitance oss V DS = 25 V, f = 1.0 MHz, see fig. 5 Reverse Transfer apacitance rss pf V DS = 1.0 V, f = 1.0 MHz Output apacitance oss V GS = 0 V V DS = 80 V, f = 1.0 MHz Effective Output apacitance oss eff. V DS = 0 V to 80 V Total Gate harge Q g Gate-Source harge Q gs I V GS = V D = 22, V DS = 80 V see fig. 6 and 13 b n Gate-Drain harge Q gd Turn-On Delay Time t d(on) Rise Time t r V DD = 300 V, I D = 22, Turn-Off Delay Time t d(off) R g = 6.2, V GS = V, see fig. b ns Fall Time t f Drain-Source Body Diode haracteristics MOSFET symbol D ontinuous Source-Drain Diode urrent I S showing the integral reverse G Pulsed Diode Forward urrent a I SM p - n junction diode Body Diode Voltage V SD T J = 25, I S = 22, V GS = 0 V b V T J = Body Diode Reverse Recovery Time t rr ns T J = 125 I F = 22, T di/dt = 0 /μs b J = Body Diode Reverse Recovery harge Q rr μ T J = Reverse Recovery urrent I RRM T J = Forward Turn-On Time t on Intrinsic turn-on time is negligible (turn-on is dominated by L S and L D ) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width 300 μs; duty cycle 2 %. c. oss eff. is a fixed capacitance that gives the same charging time as oss while V DS is rising from 0 % to 80 % V DS. S Document Number: S11-05-Rev. B, 21-Mar-11 THE PRODUT DESRIBED HEREIN ND THIS DTSHEET RE SUBJET TO SPEIFI DISLIMERS, SET FORTH T

3 I D, Drain-to-Source urrent () I D, Drain-to-Source urrent () I D, Drain-to-Source urrent ( ) IRFP22N60K, SiHFP22N60K TYPIL HRTERISTIS (25, unless otherwise noted) 0 1 VGS TOP 15V 12V V 8.0V 7.0V 6.0V 5.5V BOTTOM 5.0V T J = V 1.00 T J = µs PULSE WIDTH Tj = V DS, Drain-to-Source Voltage (V) Fig. 1 - Typical Output haracteristics 0 V DS = 50V 20µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer haracteristics 0 1 VGS TOP 15V 12V V 8.0V 7.0V 6.0V 5.5V BOTTOM 5.0V 5.0V 20µs PULSE WIDTH Tj = V DS, Drain-to-Source Voltage (V) Fig. 2 - Typical Output haracteristics r, Drain-to-Source On Resistance DS(on) (Normalized) I D = 22 V GS = V T J, Junction Temperature ( ) Fig. - Normalized On-Resistance vs. Temperature Document Number: S11-05-Rev. B, 21-Mar-11 3 THE PRODUT DESRIBED HEREIN ND THIS DTSHEET RE SUBJET TO SPEIFI DISLIMERS, SET FORTH T

4 V GS, Gate-to-Source Voltage (V) I D, Drain-to-Source urrent (), apacitance (pf) IRFP22N60K, SiHFP22N60K 0000 V GS = 0V, f = 1 MHZ iss = gs gd, ds SHORTED 000 rss = gd oss = ds gd iss 00 oss 0 rss V DS, Drain-to-Source Voltage (V) Fig. 5 - Typical apacitance vs. Drain-to-Source Voltage I SD, Reverse Drain urrent () 0.0 T.0 J = T J = 25 V GS = 0V V SD, Source-toDrain Voltage (V) Fig. 7 - Typical Source-Drain Diode Forward Voltage I D = 22 V DS = 80V VDS= 300V VDS= 120V 00 0 OPERTION IN THIS RE LIMITED BY R DS (on) 12 0µsec Q G Total Gate harge (n) 1 Tc = 25 Tj = 150 Single Pulse 1msec msec V DS, Drain-toSource Voltage (V) Fig. 6 - Typical Gate harge vs. Gate-to-Source Voltage Fig. 8 - Maximum Safe Operating rea Document Number: S11-05-Rev. B, 21-Mar-11 THE PRODUT DESRIBED HEREIN ND THIS DTSHEET RE SUBJET TO SPEIFI DISLIMERS, SET FORTH T

5 IRFP22N60K, SiHFP22N60K 25 V DS R D V GS D.U.T. 20 R G - V DD I D, Drain urrent () 15 V Pulse width 1 µs Duty factor % Fig. a - Switching Time Test ircuit 5 V DS 90 % T, ase Temperature ( ) % V GS t d(on) t r t d(off) t f Fig. 9 - Maximum Drain urrent vs. ase Temperature Fig. b - Switching Time Waveforms 1 Thermal Response (Z thj ) 0.01 D = SINGLE PULSE (THERML RESPONSE) P DM t 1 t 2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thj T t 1, Rectangular Pulse Duration (sec) Fig Maximum Effective Transient Thermal Impedance, Junction-to-ase Document Number: S11-05-Rev. B, 21-Mar-11 5 THE PRODUT DESRIBED HEREIN ND THIS DTSHEET RE SUBJET TO SPEIFI DISLIMERS, SET FORTH T

6 IRFP22N60K, SiHFP22N60K V DS 15 V t p V DS L Driver R G 20 V tp D.U.T I S 0.01Ω - V DD I S Fig. 12a - Unclamped Inductive Test ircuit Fig. 12b - Unclamped Inductive Waveforms 800 I D E S, Single Pulse valanche Energy (mj) TOP BOTTOM Starting T J, Junction Temperature Fig. 12c - Maximum valanche Energy vs. Drain urrent urrent regulator Same type as D.U.T. V Q G 12 V 0.2 µf 50 kω 0.3 µf Q GS Q GD D.U.T. V - DS V G V GS harge Fig. 13a - Basic Gate harge Waveform 3 m Fig. 13b - Gate harge Test ircuit I G I D urrent sampling resistors Document Number: S11-05-Rev. B, 21-Mar-11 THE PRODUT DESRIBED HEREIN ND THIS DTSHEET RE SUBJET TO SPEIFI DISLIMERS, SET FORTH T

7 IRFP22N60K, SiHFP22N60K Peak Diode Recovery dv/dt Test ircuit D.U.T. - ircuit layout considerations Low stray inductance Ground plane Low leakage inductance current transformer - - R g dv/dt controlled by R g Driver same type as D.U.T. I SD controlled by duty factor D D.U.T. - device under test - V DD Driver gate drive P.W. Period D = P.W. Period V GS = V a D.U.T. l SD waveform Reverse recovery current Body diode forward current di/dt D.U.T. V DS waveform Diode recovery dv/dt V DD Re-applied voltage Inductor current Body diode forward drop Ripple 5 % I SD Note a. V GS = 5 V for logic level devices Fig. 1 - For N-hannel maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see Document Number: S11-05-Rev. B, 21-Mar-11 7 THE PRODUT DESRIBED HEREIN ND THIS DTSHEET RE SUBJET TO SPEIFI DISLIMERS, SET FORTH T

8 TO-27 (High Voltage) Package Information 3 B R/2 Q E E/2 S 2 7 ØP (Datum B) Ø k M D B M ØP1 D2 2 x R (2) D D D Thermal pad 5 L1 2 x b2 3 x b 0 M M b Lead ssignments 1. Gate 2. Drain 3. Source. Drain 2 x e L See view B 1 DDE (b, b2, b) () Section -, D - D, E - E MILLIMETERS INHES MILLIMETERS INHES DIM. MIN. MX. MIN. MX. DIM. MIN. MX. MIN. MX D E E b e 5.6 BS BS b Ø k b L b L b N 7.62 BS BS b Ø P c Ø P c Q D R D S 5.51 BS BS EN: X13-03-Rev. D, 01-Jul-13 DWG: 5971 Notes 1. Dimensioning and tolerancing per SME Y1.5M ontour of slot optional. 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 27 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body.. Thermal pad contour optional with dimensions D1 and E1. 5. Lead finish uncontrolled in L1. 6. Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (5"). 7. Outline conforms to JEDE outline TO-27 with exception of dimension c. 8. Xian and Mingxin actually photo. E View B Planting (c) E M D B M View - (b1, b3, b5) Base metal c1 Revision: 01-Jul-13 1 Document Number: For technical questions, contact: hvm@vishay.com THIS DOUMENT IS SUBJET TO HNGE WITHOUT NOTIE. THE PRODUTS DESRIBED HEREIN ND THIS DOUMENT RE SUBJET TO SPEIFI DISLIMERS, SET FORTH T

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