APE8937GN2-HF-3TR VIN

Transcription

1 Ultra-Low On-Resistance 4A Load Switch Features Integrated 4A Single Channel Load Switch Input Voltage Range: 0.8V to 5.5V Ultra-low On-Resistance RON=22mΩ at Vin=5V (VBIAS=5V) RON=22mΩ at Vin=1.8V (VBIAS=5V) Low Threshhold Control Input Adjtable Rise Time e Integrated Quick Output Discharge ESD Level: 2kV for HBM, 1kV for CDM RoHS-Compliant, halogen-free Applications Telecom Systems Indtrial Systems Set-Top Boxes Consumer Electronics Handheld Products Ordering Information Description The is a small single load switch with ultra-low RON of 22mΩ and controlled turn-on, ing an N-channel MOSFET that can operate over an input voltage range of 0.8V to 5.5V and support maximum continuo current up to 4A. The switch is controlled by an on/off input (EN), which is capable of interfacing directly with low-voltage control signals. Additional features include a 300Ω on-chip load resistor for output quick discharge when the switch is turned off. In order to avoid inrh current, the rise time is adjtable ing an external ceramic capacitor on the CT pin. The is available in an ultra-small, space-saving 2mmx2mm 8-pin DFN package with a thermal pad. Pin Configuration Top View DFN2x2-8L APE8937GN2-HF-3TR Package Type GN2 : DFN2x2-8L Typical Application Circuit +5V or +3.3V EN V BIAS Exposed Pad GND 5 CT GND VBIAS V IN V OUT C IN 1uF APE8937 C OUT 0.1uF EN CT GND C T V /14

2 Absolute Maximum Ratings (Note 1) at T A = 25 C EN, CT VBIAS I MAX Storage Temperature Range (T ST ) Junction Temperature ( T J ) -0.3V to 6V V -0.3V to 6V V 4A -65 to +150 C 150 C Lead Temperature (Soldering, 10 sec.) 260 C Thermal Resistance from Junction to Ambient, Rth(ja) DFN-8L (2mmX2mm) 100 C/W Thermal Resistance from Junction to Case (thermal pad), Rth(jc) DFN-8L (2mmX2mm) 20 C/W Electrostatic Discharge (ESD) HBM (MIL-STD 883G Method ) CDM (JESD22-C101-C) 2kV 1kV Recommended Operating Conditions VBIAS CIN Junction Temperature (T J ) Operating Temperature Range 0.8V to 5.5V 2.5V to 5.5V (VBIAS > ) 1 >0.1uF 125 C -40 C to +85 C Note 1: Note 2: Note3: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Conditions are conditions under which the device functions but the specifications might not be guaranteed. For guaranteed specifications and test conditions see the Electrical Specifications. The maximum power dissipation is a function of the maximum junction temperature, T Jmax, total thermal resistance, R th(ja) and ambient temperature T A. The maximum allowable power dissipation at any ambient temperature is (T jmax -T A ) / R th(ja). Low duty pulse techniques are ed during test to maintain a junction temperature as close to ambient as possible. THIS PRODUCT IS SENSITIVE TO ELECTROSTATIC DISCHARGE, PLEASE HANDLE WITH CAUTION. USE OF THIS PRODUCT AS A CRITICAL COMPONENT IN LIFE SUPPORT OR OTHER SIMILAR SYSTEMS IS NOT AUTHORIZED. APEC DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. APEC RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. 2/14

3 Electrical Specifications (=0.8V to 5.5V, VBIAS=5V, CIN=1uF, COUT=0.1uF, TA=25 C, unless otherwise specified) PARAMETER SYM TEST CONDITION MIN TYP MAX UNIT Quiescent Current I BIAS V BIAS =V IN =V EN =5V, I OU UT=0A V BIAS =V IN =V EN =2.5V, I OUT =0A ua 50 ua Shutdown Current I SD V EN =GND 1 ua ON Resista nce (Note2) R ON V BIAS =V IN =V EN =5V, I OUT =200mA V BIAS =V IN =V EN =2.5V, I OUT =200mA T A =25 C -40~85 C (N T A =25 C -40~85 C (N NOTE1) NOTE1) mω mω Output Pull Down Resistance R OP D V BIAS =5V, V EN =0V Ω EN Input Leakage Current I ON V EN =5V or GND 1 ua EN Threshold V EN V EN H on L off 1.2 V 0.5 V Note1: Guaranteed by design, not production tested Note2: Make sure VBIAS for optimum RON performance. 3/14

4 Pin Descriptions PIN No. 1, , 8 Exposed pad PIN SYMBOL EN VBIAS GND CT GND Input power supply; bypass this input with a ceramic capacitor to ground. Enable control input, active high. Do not leave floating. Bias voltage. Ground. A capacitor to ground set the rise time of. Switch outpu PIN DESCRIPTION Tie to ground to alleviatee thermal stress. Block Diagram VBIAS Oscillator Charge Pump Control Logic Output Discharge EN GND CT 4/14

5 Timing Specifications V BIAS VBIAS V IN V OUT C IN 1uF APE8937 C OU UT 0.1uF R L V EN EN CT GND C T Fig.1 Test Circuit V EN ton toff 90% 90% 50% 50% V OUT 1% 10% 10% td-on tr t F Fig.2 ON/OFF Waveforms PARAMETER SYM TEST CONDITION MIN TYP MAX UNIT Turn-on Time t ON V BIAS =V EN N=5V, C T =1nF, R L =10Ω V IN =5V V IN =0.8V Turn-off Time t OFF F V BIAS =V EN N=5V, C T =1nF, R L =10Ω V IN =5V V IN =0.8V 1 1 Rise Time t R V BIAS =V EN N=5V, C T =1nF, R L =10Ω V IN =5V V IN =0.8V Fall Time t F V BIAS =V EN N=5V, C T =1nF, R L =10Ω V IN =5V V IN =0.8V Turn-on Delay Time t D-ON V BIAS =V EN N=5V, C T =1nF, R L =10Ω V IN =5V V IN =0.8V /14

6 Typical Performance Characteristics Condition: V BIAS =5V, V EN N=3.3V, CT= =1nF, C IN =1µ F, C OUT =0.1µF, Io=4A, ch1:en, ch2:v OUT, ch4:i IN Fig.3 Start-up Waveform, =0.8V Fig.4 Start-up Waveform, =1.05V Fig.5 Start-up Waveform, =1.8V Fig.6 Start-up Waveform, = =2.5V Fig.7 Start-up Waveform, =3.3V Fig.8 Start-up Waveform, = =5.0V 6/14

7 Typical Performance Characteristics (continued) Condition: V BIAS =V EN =3. 3V, CT=1nF, C IN =1µF, C OUT =0.1µF, Io=4A, ch1:en, ch2:v OUT T, ch4:i IN Fig.9 Start-up Waveform, =0.8V Fig.10 Start-up Waveform, = =1.05V Fig.11 Start-up Waveform, =1.8V Fig.12 Start-up Waveform, = =2.5V Fig.13 Start-up Waveform, =3.3V Fig.14 Start-up Waveform, = =5.0V 7/14

8 Typical Performance Characteristics (continued) Condition: V BIAS =V EN =5V, CT=1nF, C IN =1µF, C OU UT=0.1µF, RL=10Ω, ch1:en, ch2:v OUT Fig.15 Turn-on Response Time, =0.8VV Fig.16 Turn-on Response Time, =1.8V Fig.17 Turn-on Response Time, =3.3VV Fig.18 Turn-on Response Time, =5V Fig.19 Turn-off Response Time, =0.8VV Fig.20 Turn-off Response Time, =1.8V 8/14

9 Typical Performance Characteristics (continued) Condition: V BIAS =V EN =5V, CT=1nF, C IN =1µF, C OU UT=0.1µF, RL=10Ω, ch1:en, ch2:v OUT Fig.21 Turn-off Response Time, =3.3VV Fig.22 Turn-off Response Time, =5V Fig.23 Turn-on Delay Time, =0.8V Fig.24 Turn-on Delay Time, =1.8V Fig.25 Turn-on Delay Time, =3.3V Fig.26 Turn-on Delay Time, =5V 9/14

10 Typical Performance Characteristics (continued) Turn-on Time () Rise Time () Turn-on Delay Time () CT=1nF, Cin=1uF, Cout=0.1uF, RL=10Ω VBIAS=5V VBIAS=3.3V (V) Fig.27 t ON vs. CT=1nF, Cin=1uF, Cout=0.1uF, RL=10Ω VBIAS=5V VBIAS=3.3V (V) Fig.29 t R vs. 400 CT=1nF, Cin=1uF, Cout=0.1uF, RL=10Ω VBIAS=5V 220 VBIAS=3.3V (V) Fig.31 t D-ON vs. Turn-off Time () Fall Time () R ON (mω) 2.0 CT=1nF, Cin=1uF, Cout=0.1uF, RL= 10Ω VBIAS=5V 0.2 VBIAS=3.3V (V) Fig.28 t OFF F vs. 10 CT=1nF, Cin=1uF, Cout=0.1uF, RL=10Ω VBIAS=5V 1 VBIAS=3.3V (V) Fig.30 t F vs. VBIAS=5V VBIAS=3.3V (V) Fig.32 R ON vs. 10/14

11 Typical Performance Characteristics (continued) R ON (mω) VBIAS==5V VBIAS==3.3V T J ( C) V EN (V) T J ( C) VEN-H VEN-L Fig.33 R ON vs. Temperature Fig.34 EN Threshold vs. Temperature I BIAS (ua) Fig.35 VBIAS==5V VBIAS==3.3V T J ( C) Quiescent Current vs. Temperature 11/14

12 Application Information On/Off Control The load switch is controlled by the EN pin. The EN pin is active highh and has a low threshold making it capable of interfacing with low voltage signals. The EN pin can be ed with standardd 1.2V, 1.8V, 2.5V or 3.3V GPIO logic threshold. Do not leave the EN pin floating. Output Rise Time Control The rise time of is adjtable by an external capacitor on the CT pin. The rise time shown in the table w below is the typical measured value. Please refer to it for determining rise time. Rise Time, t R (µs), C T (nf) 10% ~90%, V BIAS =V EN =5V, C IN N=1uF, C OUT =0.1µF, R L =10Ω =0.8V =1.05V =1.2V =1.5V =1.8V =2.5V =3.3V =5V <Table 1> Input Capacitor An input capacitor is recommended to be placed between and GND to limit the voltage drop on the input supply during high current application. Output Capacitor Setting a C IN greater than the C OUT is highly recommended. Since the internal body diode is in the NMOS switch, this prevents the current flows through the body diode from to when the system supply is removed. 12/14

13 Application Information (continued) Input Capacitor An input capacitor is recommended to be placed between and GND to limit the voltage drop on the input supply during high current applications. Output Capacitor Setting a C IN greater than the C OUT is highly recommended. Since the MOSFET switch has an internal body diode, this prevents the flow of current through the body diode from to when the system supply is removed. Layout Considerationss The figure below shows the suggested layout for the. The list below will help with layout. 1. Keep the high current paths (, and GND; blue circle) wide and short to obtain the best effect. 2. The input and outpu capacitors should be as close to the device as possible to minimize any parasitic trace inductances. 3. Place thermal vias under the exposed pad of the device (green circle). This helps with thermal diffion away from the device. Fig.36 APE8937 Reference Layout 13/14

14 Package Dimensions: DFN2X2-8L D D2 E E2 e 1 b L SYMBOLS Millimeters MIN NOM MAX A A A b D D E E e L BOTTOM VIEW A A1 A2 1. All dimensions are in millimeters. 2. Dimensions do not include mold protrions. Marking Information 8937 Product : APE8937 YWWS Date/lot code (YWWS) Y: Last digit of the year WW: Work week S: Lot code sequence 14/14