10/100BASE-TX/FX Mini-Φ ΤΜ Transceiver. Figure 1: Functional Block Diagram. 10Base-T PCS. 100Base-X PCS. Digital Adaptive Equalizer.

Transcription

1 BCM521/BCM522 1/1BASE-TX/FX Mini-Φ ΤΜ Transceiver GENERAL DESCRPTON The BCM521/522 is a single-chip 1/1BASE-TX/FX transceiver targeted at Fast Ethernet switches and CardBus Network nterface devices. The BCM521 operates at 3.3 volts while the BCM522 operates at 5 volts. These devices contain a full-duplex 1BASE-T/1BASE-TX/1BASE- FX Fast Ethernet transceiver which performs all of the physical layer interface functions for 1BASE-T Ethernet on CAT 3, 4, and 5 unshielded twisted pair (UTP) cable and 1BASE-TX Fast Ethernet on CAT 5 UTP cable. 1BASE-FX is supported through the use of external fiberoptic transmit and receive devices. The BCM521/522 is a highly integrated solution combining a digital adaptive equalizer, ADC, phase lock loop, line driver, encoder, decoder and all the required support circuitry into a single monolithic CMOS chip. t complies fully with the EEE 82.3u specification, including the Media ndependent nterface (M) and Auto- Negotiation subsections, providing compatibility with all industry standard Fast Ethernet Media Access Controller (MAC) and repeater devices. FEATURES 1BASE-T/1BASE-TX/FX EEE 82.3u compliant Single-chip physical interface - M to Magnetics 3.3 Volt (BCM521) or 5 Volt (BCM522) Operation ntelligent Power Management with cable signal detect Media ndependent nterface (M) Fully-integrated digital adaptive equalizer 125 MHz clock generator and timing recovery On-chip multi-mode transmit waveshaping ntegrated digital baseline wander correction Full-duplex support EEE 82.3u-compliant Auto-Negotiation M management interface up to 12.5 Mbps LED status pins Loopback mode for diagnostics nternal Oscillator utilizes 25 MHz Crystal High Speed Token Ring frame length support Compatible with 3.3 Volt and 5 Volt /O 64-Pin TQFP for low-profile applications 8-Pin MQFP for standard applications APPLCATONS The effective use of digital technology in the BCM521/ 522 design results in robust performance over a broad range of operating scenarios. Problems inherent to mixedsignal implementations, such as analog offset and on-chip noise, are eliminated by employing field proven digital adaptive equalization and digital clock recovery techniques. Figure 1: Functional Block Diagram PCMCA and CardBus Adapter Cards PC Rev 2.2 Adapter Cards Dual-Speed Switches Printers and Print Servers Transceiver Pods (M MAU) Computer Motherboards Dual Speed Repeaters Token Ring adapters, switches, and hubs TD± RD± SD± XTAL XTALO RDAC S/H CRS/Link Detection Clock Generator Bias Generator Multimode Xmt DAC Baseline Wander Correction ADC Energy Detect Digital Adaptive Equalizer Clock Recovery Auto-Negotiation M Registers 1Base-T PCS 1Base-X PCS LED Drivers M Mgmt Control TXD[3:] TXEN TXER TXC COL/RXEN RXC CRS RXDV RXER RXD[3:] LNKLED# SPDLED# RCVLED# XMTLED# FDXLED# (BCM522 KPF only) MODES MDC MDO ENERGY_DET 521/2-DS3-R Alton Parkway P.O. Box 5713 rvine, California Phone: Fax: March 2, 1999

2 16215 Alton Parkway P.O. Box 5713 rvine, California by All rights reserved PrintedintheU.S.A.

3 March 2, 1999 BCM521 BCM522 REVSON HSTORY REVSON # DATE CHANGE DESCRPTON SP2. September 3, 1998 Preliminary Release SP3. March 2, 1999 Final Release: 1. Page 12 1Base-T Serial Mode now includes details of associated signals (Table 4 was added). 2. Force1/1 ndication explanation updated on page 28 and Table 32, 1Base-X Receive Timings updated. 4. Table 41, Recommended operating conditions updated. 5. Table 43, Electrical characteristics updated. 6. Changed from Preliminary to Final (the qualifier Preliminary is removed). Document 521/2-DS3-R Page iii

4 BCM521 BCM522 March 2, 1999 Page iv Document 521/2-DS3-R

5 March 2, 1999 BCM521 BCM522 Table of Contents Cover Page General Description Features Applications Revision History... iii Section 1: Functional Description... 1 Overview...1 Encoder/Decoder...1 Link Monitor...1 Carrier Sense...2 Collision Detection...2 Auto-Negotiation...2 Digital Adaptive Equalizer...2 ADC...2 Digital Clock Recovery/Generator...2 Baseline Wander Correction...3 Multimode Transmit DAC...3 Stream Cipher...3 Far-End Fault...3 M Management...3 Section 2: Hardware Signal Definition Table... 6 Section 3: Pinout Diagrams... 1 Section 4: Operational Description Reset...11 Mode Latching...11 Clock nput...11 solate Mode...11 Loopback Mode...11 Full-Duplex Mode...12 Repeater Mode BASE-FX Mode BASE-T Mode BASE-T Serial Mode...13 Special LED Modes...13 nterrupt Mode...13 Power Saving Modes...14 Energy Detection...14 Document 521/2-DS3-R Page v

6 521/2-DS3-R BCM522 March 2, 1999 Table of Contents Section 5: Register Summary Media ndependent nterface (M) Management nterface: Register Programming...15 M Register Map Summary...15 M Control Register...18 M Status Register...19 PHY dentifier Registers...2 Auto-Negotiation Advertisement Register...21 Auto-Negotiation Link Partner (LP) Ability Register...22 Auto-Negotiation Expansion Register...23 Auto-Negotiation Next Page Register BASE-X Auxiliary Control Register BASE-X Auxiliary Status Register BASE-X Receive Error Counter BASE-X False Carrier Sense Counter BASE-X Disconnect Counter...26 Ptest Register...26 Auxiliary Control/Status Register...27 Auxiliary Status Summary Register...28 nterrupt Register...29 Auxiliary Mode 2 Register...3 1BASE-T Auxiliary Error and General Status Register...31 Auxiliary Mode Register...32 Auxiliary Multiple PHY Register...32 Broadcom Test Register...33 Section 6: Timing and AC Characteristics Section 7: Electrical Characteristics Section 8: Application Examples Section 9: Mechanical nformation Section 1: Ordering nformation Page vi BCM521-SP3.

7 March 2, 1999 BCM521 BCM522 List of Figures Figure 1: Functional Block Diagram...Cover Page Figure 2: Pin Diagrams...1 Figure 3: Clock and Reset Timing...34 Figure 4: Transmit Start of Packet Timing (1BASE-TX)...35 Figure 5: Transmit End of Packet Timing (1BASE-TX)...36 Figure 6: Receive Start of Packet Timing (1BASE-TX)...37 Figure 7: Receive End of Packet Timing (1BASE-TX)...38 Figure 8: Receive Packet Premature End (1BASE-TX)...38 Figure 9: Link Failure or Stream Cipher Error During Receive Packet...39 Figure 1: False Carrier Sense Timing (1BASE-TX)...39 Figure 11: 1BASE-T Transmit Start of Packet Timing...4 Figure 12: Management nterface Timing...42 Figure 13: Management nterface Timing (with Preamble Suppression On)...42 Figure 14: Power Connections...45 Figure 15: Pins Sampled at Reset...45 Figure 16: 64-Pin TQFP 1mm Pkg (BCM521 KPT)...46 Figure 17: 64-Pin TQFP 14mm Pkg (BCM522 KET)...47 Figure 18: 8-Pin MQFP 14mm Pkg (BCM522 KPF)...48 Document 521/2-DS3-R Page vii

8 BCM521 BCM522 March 2, 1999 List of Tables Table 1: 4B5B Encoding...4 Table 2: Receive Error Encoding...5 Table 3: Pin Descriptions...6 Table 5: Power Modes...14 Table 6: M Management Frame Format...15 Table 7: M Register Map Summary...16 Table 8: M Control Register (Address b, d, h)...18 Table 9: M Status Register (Address 1B, 1d, 1h)...19 Table 1: PHY ndentifier Registers (Addresses 1 and 11b, 2 and 3b, 2 and 3h)... 2 Table 11: Auto-Negotiation Advertisement Register (Address 1b, 4d, and 4h)...21 Table 12: Auto-Negotiation Link Partner Ability Register (Address 11b, 5d, 5h)...22 Table 13: Auto-Negotiation Expansion Register (Address 11b, 6d, 6h)...23 Table 14: Next Page Transmit Register (Address 111b, 7d, 7h)...23 Table 15: 1BASE-X Auxiliary Control Register (Address 1b, 16d, 1h)...24 Table 16: 1BASE-X Auxiliary Status Register (Address 11b, 17d, 11h)...25 Table 17: 1BASE-X Receive Error Counter (Address 11b, 18d, 12h)...26 Table 18: 1BASE-X False Carrier Sense Counter (Address 111b, 19d, 13h)...26 Table 19: 1BASE-X Disconnect Counter (Address 11b, 2d, 14h)...26 Table 2: PTEST Register (Address 1111b, 23d, 17h)...26 Table 21: Auxiliary Control/Status Register (Address 11b, 24d, 18h)...27 Table 22: Auxiliary Status Summary Register (Address 111b, 25d, 19h)...28 Table 23: nterrupt Register (Address 111b, 26d, 1Ah)...29 Table 24: Auxiliary Mode 2 (Address 1111b, 27d, 1Bh)...3 Table 25: 1BASE-T Auxiliary Error and General Status Register (Address 111b, 28d, 1Ch) Table 26: Auxiliary Mode Register (Address 1111b, 29d, 1Dh)...32 Table 27: Auxiliary Multiple PHY Register (Address 1111b, 3d, 1Eh)...32 Table 28: Broadcom Test (Address 11111b, 31d, 1Fh)...33 Table 29: Clock Timing...34 Table 3: Reset Timing...34 Table 31: 1BASE-X Transmit Timing...35 Table 32: 1BASE-X Receive Timing...36 Table 33: 1BASE-T Transmit Timing...4 Table 34: 1BASE-T Receive Timing...41 Table 35: 1BASE-T Collision Timing...41 Table 36: Loopback Timing...41 Table 37: Auto-Negotiation Timing...41 Table 38: LED Timing...41 Table 39: Management Data nterface Timing...42 Table 4: Absolute Maximum Ratings...43 Table 41: Recommended Operating Conditions for BCM521/BCM Table 42: Package Thermal Characteristics...43 Table 43: Electrical Characteristics...44 Page viii Document 521/2-DS3-R

9 March 2, 1999 BCM521 BCM522 SECTON 1: FUNCTONAL DESCRPTON OVERVEW The BCM521/522 is a single-chip Fast Ethernet transceiver. t performs all of the physical layer interface functions for 1BASE-TX full- or half-duplex Ethernet on CAT 5 twisted pair cable and 1BASE-T full- or half-duplex Ethernet on CAT 3, 4 or 5 cable. t may also be configured for 1BASE-FX full- or half-duplex transmission over fiber-optic cabling when paired with an external fiber-optic line driver and receiver. The chip performs 4B5B, MLT3, NRZ, and Manchester encoding and decoding, clock and data recovery, stream cipher scrambling/descrambling, digital adaptive equalization, line transmission, carrier sense and link integrity monitor, Auto- Negotiation and Media ndependent nterface (M) management functions. The BCM521/522 may be connected to a MAC, switch controller or repeater controller through the M on one side, and connects directly to the network media on the other side (through isolation transformers for unshielded twisted pair (UTP) modes or fiber-optic transmitter/receiver components for FX modes). n repeater mode, the M port may be bussed with other BCM521/522 devices. The BCM521/522 is fully compliant with the EEE 82.3 and 82.3u standards. ENCODER/DECODER n 1BASE-TX and 1BASE-FX modes, the BCM521/522 transmits and receives a continuous data stream on twisted pair or fiber-optic cable. When the M transmit enable is asserted, nibble-wide (4-bit) data from the transmit data pins is encoded into 5-bit code-groups and inserted into the transmit data stream. The 4B5B encoding is shown in Table 1. The transmit packet is encapsulated by replacing the first two nibbles of preamble with a start of stream delimiter (J/K codes) and appending an end of stream delimiter (T/R codes) to the end of the packet. When the M transmit error input is asserted during a packet, the transmit error code group (H) is sent in place of the corresponding data code group. The transmitter will repeatedly send the idle code group between packets. n TX mode, the encoded data stream is scrambled by a stream cipher block and then serialized and encoded into MLT3 signal levels. A multi-mode transmit DAC is used to drive the MLT3 data onto the twisted pair cable. n FX mode, the scrambling function is bypassed and the data is NRZ encoded. The multimode transmit DAC drives differential positive ECL (PECL) levels to an external fiber-optic transmitter. Following baseline wander correction, adaptive equalization, and clock recovery in TX mode, the receive data stream is converted from MLT3 to serial NRZ data. The NRZ data is descrambled by the stream cipher block and then deserialized and aligned into 5-bit code groups. n FX mode, the receive data stream differential PECL levels are sampled from the fiber-optic receiver. Baseline wander correction, adaptive equalization, and stream cipher descrambling functions are bypassed and NRZ decoding is used instead of MLT3. The 5-bit code groups are decoded into 4-bit data nibbles, as shown in Table 1. The start of stream delimiter is replaced with preamble nibbles and the end of stream delimiter and idle codes are replaced with all zeros. The decoded data is driven onto the M receive data pins. When an invalid code group is detected in the data stream, the BCM521/522 will assert the M RXER signal. The chip will also assert RXER for several other error conditions which improperly terminate the data stream. While RXER is asserted, the receive data pins will be driven with a 4-bit code indicating the type of error detected. The error codes are listed in Table 2. n 1BASE-T mode, Manchester encoding and decoding is performed on the data stream. The multimode transmit DAC performs pre-equalization for 1 meters of CAT 3 cable. LNK MONTOR n 1BASE-TX mode, receive signal energy is detected by monitoring the receive pair for transitions in the signal level. Signal levels are qualified using squelch detect circuits. When no signal or certain invalid signals are detected on the receive pair, the link monitor will enter and remain in the Link Fail state where only idle codes will be transmitted. When a valid signal is detected on the receive pair for a minimum period of time, the link monitor will enter the Link Pass state and the transmit and receive functions will be enabled. n 1BASE-FX mode, the external fiber-optic receiver performs the signal energy detection function and communicates this information directly to the BCM521/522 through the differential SD± pins. n 1BASE-T mode, a link-pulse detection circuit constantly monitors the RD± pins for the presence of valid link pulses. Document 521/2-DS3-R Page 1

10 BCM521 BCM522 March 2, 1999 CARRER SENSE n 1BASE-X modes, carrier sense is asserted asynchronously on the CRS pin as soon as activity is detected in the receive data stream. RXDV is asserted as soon as a valid Start-of-Stream Delimiter (SSD) is detected. Carrier sense and RXDV are deasserted synchronously upon detection of a valid end of stream delimiter or two consecutive idle code groups in the receive data stream. f carrier sense is asserted and a valid SSD is not detected immediately, then RXER will be asserted in place of RXDV. A value of 111 will be driven on the receive data pins to indicate false carrier sense. n 1BASE-T mode, carrier sense is asserted asynchronously on the CRS pin when valid preamble activity is detected on the RD+/ input pins. n half-duplex DTE mode, the BCM521/522 will also assert carrier sense while transmit enable is asserted and the link monitor is in the Pass state. n full-duplex mode, CRS is only asserted for receive activity. COLLSON DETECTON n half-duplex mode, collision detect is asserted on the COL pin whenever carrier sense is asserted and transmission is in progress. Collision detect is never asserted in full-duplex mode or repeater mode. AUTO-NEGOTATON The BCM521/522 contains the ability to negotiate its mode of operation over the twisted pair link using the Auto-Negotiation mechanism defined in the EEE 82.3u specification. Auto-Negotiation may be enabled or disabled by hardware or software control. When the Auto-Negotiation function is enabled, the BCM521/522 will automatically choose its mode of operation by advertising its abilities and comparing them with those received from its link partner. The BCM521/522 can be configured to advertise 1BASE-TX full-duplex and/or half-duplex and 1BASE-T full and/or half-duplex. The transceiver will negotiate with its link partner, and choose the highest level of operation available for its own link. Auto-Negotiation is not operational during 1BASE-FX operation and will not advertise full-duplex abilities when the device is configured in repeater mode. DGTAL ADAPTVE EQUALZER The digital adaptive equalizer removes ntersymbol nterference (S) created by the transmission channel media. The equalizer accepts sampled unequalized data from the ADC on each channel and produces equalized data. The BCM521/ 522 achieves an optimum signal to noise ratio by using a combination of feed forward equalization and decision feedback equalization. This powerful technique achieves a 1BASE-TX BER of less than 1 x 1-12 fortransmissionupto1meters on CAT 5 twisted pair cable, even in harsh noise environments. The digital adaptive equalizers in the BCM521/522 achieve performance close to theoretical limits. The all-digital nature of the design makes the performance very tolerant to on-chip noise. The filter coefficients are self adapting to any quality of cable or cable length. Due to transmit pre-equalization in 1BASE-T mode and complete lack of S in 1BASE-FX mode, the adaptive equalizer is bypassed in these two modes of operation. ADC The receive channel has a 6-bit 125 MHz analog to digital converter (ADC). The ADC samples the incoming data on the receive channel and produces a 6-bit output. The output of the ADC is fed to the digital adaptive equalizer. Advanced analog circuit techniques achieve low offset, high power supply noise rejection, fast settling time, and low bit error rate. DGTAL CLOCK RECOVERY/GENERATOR The all-digital clock recovery and generator block creates all internal transmit and receive clocks. The transmit clock is locked to the 25 MHz clock input while the receive clock is locked to the incoming data stream. Clock recovery circuits optimized to MLT3, NRZ, and Manchester encoding schemes are included for use with each of the three different operating modes. The input data stream is sampled by the recovered clock and fed synchronously to the digital adaptive equalizer. Page 2 Document 521/2-DS3-R

11 March 2, 1999 BCM521 BCM522 BASELNE WANDER CORRECTON A 1BASE-TX data stream is not always DC balanced. Because the receive signal must pass through a transformer, the DC offset of the differential receive input can wander. This effect, known as baseline wander, can greatly reduce the noise immunity of the receiver. The BCM521/522 automatically compensates for baseline wander by removing the DC offset from the input signal, and thereby significantly reduces the chance of a receive symbol error. The baseline wander correction circuit is not required, and therefore bypassed, in 1BASE-T and 1BASE-FX operating modes. MULTMODE TRANSMT DAC The multimode transmit digital to analog converter (DAC) transmits MLT3-coded symbols in 1BASE-TX mode, NRZcoded symbols in 1BASE-FX mode, and Manchester-coded symbols in 1BASE-T mode. t allows programmable edgerate control in TX mode which decreases unwanted high frequency signal components thus reducing EM. High-frequency pre-emphasis is performed in 1BASE-T mode; no filtering is performed in 1BASE-FX mode. The transmit DAC utilizes a current drive output which is well balanced and produces very low-noise transmit signals. PECL voltage levels are produced with resistive terminations in 1BASE-FX mode. STREAM CPHER n 1BASE-TX mode, the transmit data stream is scrambled in order to reduce radiated emissions on the twisted pair cable. The data is scrambled by exclusive or ing the NRZ signal with the output of an 11-bit wide linear feedback shift register (LFSR), which produces a 247-bit non-repeating sequence. The scrambler reduces peak emissions by randomly spreading the signal energy over the transmit frequency range, and eliminating peaks at certain frequencies. The receiver descrambles the incoming data stream by exclusive or ing it with the same sequence generated at the transmitter. The descrambler detects the state of the transmit LFSR by looking for a sequence representing consecutive idle codes. The descrambler will lock to the scrambler state after detecting a sufficient number of consecutive idle code-groups. The receiver will not attempt to decode the data stream unless the descrambler is locked. Once locked, the descrambler will continuously monitor the data stream to make sure that it has not lost synchronization. The receive data stream is expected to contain inter-packet idle periods. f the descrambler does not detect enough idle codes within 724µs, it will become unlocked, and the receive decoder will be disabled. The descrambler will always be forced into the unlocked state when a link failure condition is detected. A special node called High Speed Token Ring can be enabled. t will increase the scrambler timeout from 724 µs to 5816 µs, thus allowing frames as large as the Token Ring maximum length to be received without error. Stream cipher scrambling/descrambling is not used in 1BASE-FX and 1BASE-T modes. FAR-END FAULT Auto-Negotiation provides a Remote Fault capability for detection of asymmetric link failures. Since Auto-Negotiation is not available for 1BASE-FX, the BCM521/522 implements the EEE 82.3 standard Far-End Fault mechanism for the indication and detection of remote error conditions. When the Far-End Fault mechanism is enabled, a transceiver will transmit the Far-End Fault ndication whenever a receive channel failure is detected (signal detect is deasserted). The transceiver will also continuously monitor the receive channel when a valid signal is present (signal detect asserted). When its link partner is indicating a remote error, the transceiver will force its link monitor into the link fail state and set the Remote Fault bit in the M status register. The Far-End Fault mechanism is enabled by default in 1BASE-FX mode and disabled in 1BASE-TX and 1BASE-T modes, and may be controlled by software after reset. M MANAGEMENT The BCM521/522 contains a complete set of M management registers accessible by using the management clock line (MDC) and the bidirectional serial data line (MDO). Many transceivers can be bussed together on a single MDO/MDC wire pair by giving each a unique PHY address, defined by configuring the five external PHY address input pins. Every time an M read or write operation is executed, the BCM521/522 compares the operation s PHY address with its own PHY address definition. The operation is executed only when the addresses match. For further details, see Section 5: Register Summary on page 15. Document 521/2-DS3-R Page 3

12 BCM521 BCM522 March 2, 1999 Table 1: 4B5B Encoding NAME 4B CODE 5B CODE MEANNG 1111 Data Data Data Data Data Data Data Data Data Data 9 A Data A B Data B C Data C D Data D E Data E F Data F * dle J 11* 11 Start-of-Stream Delimiter, Part 1 K 11* 11 Start-of-Stream Delimiter, Part 2 T * 111 End-of-Stream Delimiter, Part 1 R * 111 End-of-Stream Delimiter, Part 2 H 1 1 Transmit Error (used to force signalling errors) V 111 nvalid Code V nvalid Code V nvalid Code V nvalid Code V nvalid Code V nvalid Code V nvalid Code V nvalid Code V nvalid Code V nvalid Code * Treated as invalid code (mapped to 111) when received in data field. Page 4 Document 521/2-DS3-R

13 March 2, 1999 BCM521 BCM522 Table 2: Receive Error Encoding ERROR TYPE RXD[3:] Stream cipher error - descrambler lost lock 1 Link failure 11 Premature end of stream 11 nvalid code 111 Transmit error 1 False carrier sense 111 Document 521/2-DS3-R Page 5

14 BCM521 BCM522 March 2, 1999 SECTON 2: HARDWARE SGNAL DEFNTON TABLE Table 3 provides the pin descriptions for the BCM521 and BCM KPT 522 KET 522 KPF MEDA CONNECTONS 26, 25 26, 25 31, 3 31, 3 31, 3 36, 35 CLOCK 6, 5 6, 5 8, 7 M NTERFACE Table 3: Pin Descriptions PN LABEL TYPE DESCRPTON RD+ RD TD+ TD XTAL, XTALO TXC O 6, 59, 58, 57 6, 59, 58, 57 74, 73, 72, 71 O,O Receive Pair. Differential data from the media is received on the RD± signal pair. Transmit Pair. Differential data is transmitted to the media on the TD± signal pair. 25 MHz Crystal Oscillator nput, Output. A 25 MHz parallel-resonant crystal may be connected between these pins to stabilize the internal oscillator. Connect a 27 pf capacitor from each pin to GND. Alternatively, a stable 25 MHz clock may be applied to the XTAL pin. n this case, leave XTALO unconnected. No capacitors are required. Transmit Clock. 25 MHz output in 1BASE-X mode and 2.5 MHz in 1BASE-T M mode. 1 MHz output in 1BASE-T serial mode. This clock is a continuously driven output, generated from the XTAL input. TXD[3:] PD these pins synchronous with TXC. TXD[3] is the most significant bit. Transmit Data nput. Nibble-wide transmit data stream is input on Only bit is used in 1BASE-T serial mode TXEN Transmit Enable. Active high. ndicates that the data nibble on PD TXD[3:] is valid TXER Transmit Error. An active high input is asserted when a transmit error PD condition is requested by the repeater controller RXC O 43, 44, 47, 48 43, 44, 47, 48 53, 54, 57, 58 RXD[3:] RXDV O RXER O O Receive Clock. 25 MHz output in 1BASE-X M mode and 2.5 MHz output in 1BASE-T mode. 1 MHz output in 1BASE-T serial mode. This clock is recovered from the incoming data on the cable inputs. RXC is a continuously running output clock resynchronized at the start of each incoming packet. This synchronization may result in an elongated period during one cycle while RXDV is low. Receive Data Outputs. Nibble-wide receive data stream is driven out on these pins synchronous with RXC. RXD[3] is the most significant bit. Only bit is used in 1BASE-T serial mode. Receive Data Valid. Active high. ndicates that a receive frame is in progress, and that the data stream present on the RXD output pins is valid. Receive Error Detected. Active high. ndicates that an error is occurring during a receive frame. [MSB:LSB]; # = active-low signal, = input, O = output, /O = bidirectional, PU = input w/ internal pull-up, O OD = open-drain output, O 3S = three-state output, B = Bias, PWR = power supply, GND = ground Page 6 Document 521/2-DS3-R

15 March 2, 1999 BCM521 BCM KPT CRS O Carrier Sense. Active high. ndicates traffic on link. n 1BASE-X modes, CRS is asserted when a non-idle condition is detected in the receive data stream and deasserted when idle or a valid end of stream delimiter is detected. n 1BASE-T mode, CRS is asserted when a valid preamble is detected and deasserted when end-of-file or an idle condition is detected. CRS is also asserted during transmission of packets except in repeater or full-duplex modes. CRS is an asynchronous output signal COL/RXEN /O PD Collision Detect. n half-duplex modes, active high output indicates that a collision has occurred. n full-duplex mode, COL remains low. COL is an asynchronous output signal. Receive Enable. n repeater mode, RXEN becomes an active high input allowing the repeater controller to enable the M receive bus MDO /O PU and write to the M registers. The data value on the MDO pin is valid Management Data /O. This serial input/output bit is used to read from and latched on the rising edge of MDC MDC PD allow M management functions. Clock frequencies up to 12.5 MHz are Management Data Clock. The MDC clock input must be provided to supported RESET# Reset. Active Low. Resets the BCM521/522. Also used to enable PU Power Off and Low Power modes. MODE 14, 13, 12, 11, KET 14, 13, 12, 11, KPF 16, 15, 14, 13, 12 PHYAD [4:] PD PHY Address Selects. These inputs set the M management PHY address FDX PD logically OR ed with register, bit 8 to select full-duplex (1) or half-duplex () operation. This selection is only performed in DTE mode Full-Duplex Mode. When Auto-Negotiation is disabled, the FDX pin is as full-duplex operation is not allowed in repeater mode F1/SD+ Table 3: Pin Descriptions (Continued) PN LABEL TYPE DESCRPTON 1BASE-FX Signal Detect/Force 1BASE-X Control. When 1BASE-FX is selected, SD+ and SD indicate signal quality status on the fiber optic link. When the signal quality is good, the SD+ pin will be high relative to the SD pin. When 1BASE-FX mode is not selected, the F1 function is enabled. When F1 is high and ANEN is low, the transceiver will be forced to 1BASE-TX operation. When F1 is low and ANEN is low, the transceiver is forced to 1BASE-T operation. When ANEN is high, F1 has no effect on operation ANEN/SD 1BASE-FX Signal Detect/Auto-Negotiation Enable. When 1BASE-FX is selected, the SD function is enabled. See SD+ description above. When 1BASE-FX is not selected, the ANEN function is enabled. ANEN is active high. When pulled high, Auto- Negotiation will begin immediately after reset. When low, Auto- Negotiation is disabled by default. After reset, the Auto-Negotiation function is under software control TESTEN Test Mode Enable. Active high. May float or be grounded for normal PD operation. [MSB:LSB]; # = active-low signal, = input, O = output, /O = bidirectional, PU = input w/ internal pull-up, O OD = open-drain output, O 3S = three-state output, B = Bias, PWR = power supply, GND = ground Document 521/2-DS3-R Page 7

16 BCM521 BCM522 March 2, KPT LOWPWR PD into Low Power operation with the chip deactivated except for the energy detect block and the crystal oscillator. When asserted with Low Power Mode Enable. Active high input places the BCM521/522 RESET# pulled low, the entire chip is deactivated (Power Off mode) ENERGY_DET O BAS RDAC B LEDS LNKLED# /O PU SPDLED# /O PU POWER 522 KET 522 KPF XMTLED# NTR# FDXLED# RCVLED# ACTLED# 2 FDXLED# O Table 3: Pin Descriptions (Continued) PN LABEL TYPE DESCRPTON O OD O OD Energy Detection. Active high output indicates the presence of a signal on RD+/ receive analog wire pair. Operational in all modes except Power Off. DAC Bias Resistor. Adjusts the current level of the transmit DAC. A resistor of 1.27 kω ±1% must be connected between the RDAC pin and GND. Link ntegrity LED. The Link ntegrity LED indicates the link status of the PHY. LNKLED# is driven low when the link to the PHY is good. During RESET, the output driver is tri-stated and the input value is used to latch the fiber mode. f the pin is low, 1BASE-FX mode is selected. f the pin is high or floating, 1BASE-T or 1BASE-TX mode is selected. When FX mode is enabled, the polarity of LNKLED# is inverted. 1BASE-X LED. The 1 Base-X LED is driven low when operating in 1BASE-X modes and high when operating in 1BASE-T modes. During RESET, the output driver is tri-stated and the input value is used to latch the repeater mode. f the pin is pulled low, the chip will enter repeater mode. f the pin is high or floating, DTE mode is selected. When repeater mode is enabled, the polarity of SPDLED# is inverted. Transmit Activity LED. Active low output. The transmit activity LED is driven low for approximately 8ms each time there is transmit activity while in the link pass state. When the interrupt mode is enabled, pin becomes NTR#. When FDXLED mode is enabled, pin becomes FDXLED#. Receive Activity LED. Active low output. The receive activity LED is driven low for approximately 8ms each time there is receive activity while in the link pass state. n either interrupt or FDXLED mode, pin becomes ACTLED#, indicating both receive and transmit activity. Full Duplex LED. BCM522KPF 8-Pin Package Only. The Full Duplex LED is driven low when operating in full duplex mode and driven high in half duplex mode. This output always relates the duplex status, regardless of what type of output appears on the XMTLED# pin. 8 VDD PWR nput VDD, BCM V or 5V. f any of the inputs are driven to 5.V, this pin must be connected to a 5.V supply. f none of the inputs are driven above 3.3V, this pin must be connected to the 3.3V supply. 8 1 VDD PWR nput VDD, BCM522. This pin must be connected to the 5.V supply. [MSB:LSB]; # = active-low signal, = input, O = output, /O = bidirectional, PU = input w/ internal pull-up, O OD = open-drain output, O 3S = three-state output, B = Bias, PWR = power supply, GND = ground Page 8 Document 521/2-DS3-R

17 March 2, 1999 BCM521 BCM KPT 18, 22, 27, 28 21, 24, 29, 32 18, 22, 27, 28 21, 24, 29, 32 23, 27, 32, 33 26, 29, 34, 37 AVDD PWR Analog VDD. AGND GND Analog GND. 3 5 REGDVDD PWR Voltage Regulator nput. BCM522 Only. 19, 2 24, 25 REGAVDD PWR Voltage Regulator nput. BCM522 Only. 2, 55 2, 55 4, 69 DVDD PWR Digital Core VDD. 54, 63 54, 63 68, 77 DGND GND Digital Core GND. 1, 4, 46 7, 4, 45, KET 1, 4, 46 7, 4, 45, KPF 3, 6, 56 9, 5, 55, 78 Table 3: Pin Descriptions (Continued) PN LABEL TYPE DESCRPTON OVDD PWR Digital Periphery (Output Buffer) VDD. OGND GND Digital Periphery (Output Buffer) GND. [MSB:LSB]; # = active-low signal, = input, O = output, /O = bidirectional, PU = input w/ internal pull-up, O OD = open-drain output, O 3S = three-state output, B = Bias, PWR = power supply, GND = ground Document 521/2-DS3-R Page 9

18 BCM521 BCM522 March 2, 1999 SECTON 3: PNOUT DAGRAMS Figure 2 provides the pin diagrams for the BCM521 and BCM522. Figure 2: Pin Diagrams NC NC AGND AVDD RDAC AGND RD - RD + AVDD AVDD AGND TD - TD + AGND OGND DGND CRS COL/RXEN TXD3 TXD2 TXD1 TXD TXEN DVDD DGND TXC TXER RXER RXC RXDV OVDD DVDD NC OVDD XTALO XTAL OGND VDD RESET# PHYAD PHYAD1 PHYAD2 PHYAD3 PHYAD4 TESTEN LOWPWR BCM521 KPT RXD RXD1 OVDD OGND RXD2 RXD3 MDC MDO OGND FDX ANEN/SD - F1/SD + SPDLED# LNKLED# XMTLED#/NTR#/FDXLED# RCVLED#/ACTLED# ENERGY_DET AVDD (Top View) BCM522 KET 64 PNS (Top View) OGND NC NC AVDD REGAVDD REGAVDD AGND AVDD RDAC AGND RD - RD + AVDD AVDD AGND TD - TD + AGND NC NC NC NC NC OGND DGND CRS COL/RXEN TXD3 TXD2 TXD1 TXD TXEN DVDD DGND TXC TXER RXER RXC RXDV NC NC NC NC OVDD DVDD REGDVDD OVDD XTALO XTAL OGND VDD RESET# PHYAD PHYAD1 PHYAD2 PHYAD3 PHYAD4 TESTEN LOWPWR ENERGY_DET FDXLED# BCM522 KPF NC NC RXD RXD1 OVDD OGND RXD2 RXD3 MDC MDO OGND FDX ANEN/SD - F1/SD + SPDLED# LNKLED# XMTLED#/NTR#/FDXLED# RCVLED#/ACTLED# NC NC ENERGY_DET AVDD REGAVDD REGAVDD AGND AVDD RDAC AGND RD - RD + AVDD AVDD AGND TD - TD + AGND DGND CRS COL/RXEN TXD3 TXD2 TXD1 TXD TXEN DVDD DGND TXC TXER RXER RXC RXDV OVDD DVDD REGDVDD OVDD XTALO XTAL OGND VDD RESET# PHYAD PHYAD1 PHYAD2 PHYAD3 PHYAD4 TESTEN LOWPWR RXD RXD1 OVDD OGND RXD2 RXD3 MDC MDO OGND FDX ANEW/SD - F1/SD + SPDLED# LNKLED# XMTLED#/NTR#/FDXLED# RCVLED#/ACTLED# Pins (Top View) Page 1 Document 521/2-DS3-R

19 March 2, 1999 BCM521 BCM522 SECTON 4: OPERATONAL DESCRPTON RESET There are two ways to reset the BCM521/522. A hardware reset pin has been provided that resets all internal nodes in the chip to a known state. The reset pulse must be asserted for at least 4 ns. Hardware reset should always be applied to the BCM521/522 after power-up. The BCM521/522 also has a software reset capability. To perform software reset, a 1 must be written to bit 15 of the M Control Register. This bit is self-clearing, meaning that a second write operation is not necessary to end the reset. There is no effect if a is written to the M Control Register reset bit. MODE LATCHNG n order to reduce chip pin count, two pins have been given dual functionality. The LNKLED# and SPDLED# pins, normally LED drivers, are used as inputs during hardware RESET to sample requests for fiber mode and repeater mode operation. After RESET, the pins revert to outputs. The LNKLED# pin will interpret a during hardware RESET to be a request for fiber mode of operation and a 1 to be a request for copper UTP operation. Similarly, a 1 on the SPDLED# pin during hardware RESET will be interpreted as a request for DTE mode and a a request for repeater mode. The connection of the LED to the chip must be modified as shown in Figure 15, on page 45, to provide the signal input, yet retain the LED indication function. f it is desired to have either pin sample a 1 during RESET, the LED would be connected fromthepintovddasinfigure15a.tosamplea during RESET, the LED would be connected from the pin to ground as in Figure 15B. After the chip samples the input, it will latch the value and generate the proper polarity signal to drive the LED. For example, if either LED pin is sampled as during RESET, the subsequent output signal becomes inverted, active high. This potential inversion of signal polarity may need to be accounted for if loads other than the LEDs are driven from these terminals. f no connection is made to the LNKLED# or SPDLED# pins, internal pull-ups cause the chip to sample a logical 1 at reset and give the default operation of copper UTP mode and DTE. CLOCK NPUT The BCM521/522 clock input can be driven two ways: internal crystal oscillator or external oscillator. To take advantage of the internal oscillator, attach a 25 MHz crystal between the XTAL and XTALO pins. Connect 27 pf capacitors from each pin to ground. Alternatively, a 5% duty cycle 25MHz clock may be directly applied to the XTAL pin. n this case, the XTALO output must be left unconnected. No capacitors are used. SOLATE MODE When the BCM521/522 is put into isolate mode, all M inputs (TXD[3:], TXEN, and TXER) are ignored, and all M outputs (TXC, COL, CRS, RXC, RXDV, RXER, and RXD[3:]) are set to high impedance. Only the M management pins (MDC, MDO) operate normally. Upon resetting the chip, the isolate mode is off. Writing a 1 to bit 1 of the M Control Register puts the transceiver into isolate mode. Writing a tothesamebitremovesitfromisolatemode. LOOPBACK MODE Loopback mode allows in-circuit testing of the BCM521/522 chip. All packets sent in through the TXD pins are loopedback internally to the RXD pins, and are not sent out to the cable. The loopback mode is enabled by writing a 1 to bit 14 of the M Control Register. n order to resume normal operation, bit 14 of the M Control Register must be. ncoming packets on the cable are ignored in loopback mode. Because of this, the COL pin will normally not be activated during loopback mode. n order to test that the COL pin is actually working, the BCM521/522 may be placed into collision test mode. This mode is enabled by writing a 1 to bit 7 of the M Control Register. Asserting TXEN will cause the COL output to go high, and deasserting TXEN will cause the COL output to go low. Document 521/2-DS3-R Page 11

20 BCM521 BCM522 March 2, 1999 While in loopback mode, several function bypass modes are also available that can provide a number of different combinations of feedback paths during loopback testing. These bypass modes include: bypass scrambler, bypass MLT3 encoder and bypass 4B5B encoder. All bypass modes can be accessed by writing bits of the Auxiliary Control Register (1h). mportant Note: Due to the nature of the Block RXDV mode (bit 9 of M Register 1Bh), which is enabled by default, 1BASE-T loopback will not function properly. t is necessary to first disable the Block RXDV mode by writing FD to the Aux Mode 2 Register (1Bh). FULL-DUPLEX MODE The BCM521/522 supports full-duplex operation. While in full-duplex mode, a transceiver may simultaneously transmit and receive packets on the cable. The COL signal is never activated while in full-duplex mode. The CRS output is asserted only during receive packets, not transmit packets. By default, the BCM521/522 powers up in half-duplex mode. When Auto-Negotiation is disabled, full-duplex operation can be enabled either by FDX pin control or by an M register bit (Register, bit 8). When Auto-Negotiation is enabled in DTE mode, full-duplex capability is advertised by default, but can be overridden by a write to the Auto-Negotiation Advertisement Register (4h). n repeater mode, full-duplex capability can never be advertised. One of the LED outputs can be modified to signal full-duplex vs. half-duplex operation. This capability is enabled by setting M Register 1Ah, bit 15. n this mode, XMTLED# becomes FDXLED#, where a 1 output indicates half-duplex and a output indicates full-duplex. This value is the inverse of M register 18h, bit. When the FDXLED mode is activated, the RCVLED# becomes ACTLED#. The BCM522 KPF also contains a dedicated FDXLED# pin that is always active regardless of the type of output appearing on the XMTLED# pin. REPEATER MODE The BCM521/522 supports a repeater mode for 1Mbps operation only. Activation of this mode requires a pulldown resistor on the SPDLED# output. The pin is tri-stated during hardware reset and the value is sampled on the trailing edge of RESET#. While in the repeater mode, the BCM521/522 allows only 1BASE-TX or 1BASE-FX operation. Several signals change their functionality in repeater mode. The COL output becomes a RXEN input, allowing the repeater controller to enable the M receive bus. The CRS output is asserted only during receive packets, not transmit packets. No full-duplex operation is allowed. 1BASE-FX MODE For 1BASE-FX mode, the BCM521/522 transceiver interfaces with an external 1BASE-FX fiber-optic driver and receiver instead of the magnetics module used with twisted-pair cable. The differential transmit and receive data pairs operate at PECL voltage levels instead of those required for twisted-pair transmission. The data stream is encoded using two-level NRZ instead of three-level MLT3. Since scrambling is not used in 1BASE-FX operation, the stream cipher function is bypassed. To activate the 1BASE-FX mode, a pull down resistor must be placed on the LNKLED# output. During hardware reset, the output driver is tri-stated and the value is sampled on the trailing edge of RESET#. The external fiber-optic receiver will detect signal status and pass it into the BCM521/522 through the SD± pins. The SD± pins are functional only after the 1BASE-FX mode is selected. 1BASE-T MODE The same magnetics module used in 1BASE-TX mode can be used to interface to the twisted-pair cable when operating in 1BASE-T mode. The data will be two-level Manchester encoded instead of three-level MLT3 and no scrambling/ descrambling or 4B5B coding is performed. Data and clock rates are decreased by a factor of 1, with the M interface signals operating at 2.5 MHz. Page 12 Document 521/2-DS3-R

21 March 2, 1999 BCM521 BCM522 1BASE-T SERAL MODE The BCM521/522 supports 1BASE-T serial mode, also know as the 7-wire interface. n this mode, 1BASE-T transmit and receive packets appear at the M in serial fashion, at a rate of 1 MHz. Receive packet data is output on RXD () synchronously with RXC. Transmit packet data must be input on TXD () synchronously with TXC. Both clocks toggle at 1 MHz. The 1BASE-T serial mode is enabled by writing a 1 to bit 1 of the Auxiliary Multiple-PHY register (1Eh). Note that this mode is not available in 1BASE-X modes. The following table shows the M pins used in this mode and their direction of operation. 521 KPT 522 KET 522 KPF Table 4: 1BASE-T Serial Mode (7-Wire) Signals PN LABEL TYPE DESCRPTON TXD () Serial Transmit Data TXC O Tranmit Data Clock (1 MHz) TXEN Transmit Enable RXD () O Serial Receive Data RXC O Receive Data Clock (1 MHz) CRS O Carrier Sense COL/RXEN O Collision Detect SPECAL LED MODES Traffic Meter Mode. The blink rate of XMTLED# and RCVLED# is decreased dramatically to better show the volume of traffic. Lower traffic levels will make the corresponding LED appear dimmer than higher traffic levels. This mode is activated by writing a 1 to bit 6 of the Aux Mode 2 register (1Bh). Two Link LED Mode. n this mode, the functions of SPDLED# and LNKLED# are changed. SPDLED# becomes an indicator of 1BASE-T link while LNKLED# becomes an indicator of 1BASE-X link. The Two Link LED mode is enabled by writing a 1 to bit 2 of the Aux Mode 2 Register (1Bh). Note that the polarities of these two outputs are influenced by whether FX mode or RPTR mode are enabled. See the definitions of SPDLED# and LNKLED# pins. Force LEDs On. The XMTLED# and RCVLED# outputs can be forced on ( value) by writing a 1 to bit 5 of the Aux Mode 2 register(1bh). Disable LEDs. The XMTLED# and RCVLED# outputs can be forced off ( 1 value) by writing a 1 to bit 4 of the Aux Mode register (1Dh). Similarly, the LNKLED# output can be forced off (value depends on FX mode, see definition of LNKLED# pin) by writing a 1 to bit 3 of the Aux Mode register (1Dh). NTERRUPT MODE The BCM521/522 can be programmed to provide an interrupt output. Three conditions can cause an interrupt to be generated: changes in the duplex mode, changes in the speed of operation or changes in the link status. The interrupt feature is disabled by default. When the interrupt capability is enabled by setting M register 1Ah, bit 14, the XMTLED# pin becomes the NTR# pin and the RCVLED# pin becomes an activity pin named ACTLED#. The NTR# pin is open-drain and may be wire-ored with NTR# pins of other chips on a board. The status of each interrupt source is reflected in register 1Ah, bits 1, 2 and 3. f any type of interrupt occurs, the nterrupt Status bit, register 1Ah, bit, will be set. Document 521/2-DS3-R Page 13

22 BCM521 BCM522 March 2, 1999 The nterrupt Register (1Ah) also contains several bits to control different facets of the interrupt function. f the interrupt enable bit is set to, no status bits will be set and no interrupts will be generated. f the interrupt enable bit is set to 1, the following conditions apply: 1. f mask status bits (bits 9,1,11) are set to and the interrupt mask (bit 8) is set to, status bits and interrupts will be available. 2. f mask status bits (bits 9,1,11) are set to and the interrupt mask (bit 8) is set to 1, statusbitswillbesetbutno interrupts generated. 3. f any mask status bit is set to 1 and the interrupt mask is set to, that status bit will not be set and no interrupt of that type will be generated. 4. f any mask status bit is set to 1 and the interrupt mask is set to 1, that status bit will not be set and no interrupt of any kind will be generated. POWER SAVNG MODES Two power saving modes are implemented in the BCM521/522, which target PCMCA and CardBus applications. The first, called Power Off, disables all circuitry on the chip and consumes the least amount of power. n this mode, register contents are not preserved. Thus, a hard reset should be issued at least 2 milliseconds after exiting this mode. The Power Off mode is enabled by setting LOWPWR to 1 and RESET# to. The second power saving mode is Low Power. n this modes, all chip circuitry is disabled except for the crystal oscillator and the special Energy Detection function. This mode is useful for determining whether the transceiver is connected to a link partner. The Energy Detection block outputs its result on the ENERGYDET pin which can be used by external logic to control when the transceiver is placed in Full Power or Low Power modes. Register contents are preserved while the chip is in Low Power mode, so a hard reset is not necessary after resuming Full Power. The Low Power Mode is enabled by setting LOWPWR to 1 and RESET# to 1. Table 5: Power Modes MODE OSCLLATOR AND ENERGY DETECTON LOWPWR RESET# Full Power Active X Low Power Active 1 1 Power Off Disabled 1 ENERGY DETECTON An on-chip Energy Detection circuit has the capability of determining when a link partner is connected to the end of the transmission media. The circuit monitors the receive inputs for any type of energy, including 1BASE-T, 1BASE-TX or 1BASE-FX packets, and 1BASE-T or Auto-Negotiation link pulses. When energy is detected on the receive inputs for longer than 1.3 milliseconds, the ENERGYDET output is asserted. f all traces of energy disappear for longer the 1.3 seconds, it is assumed that the link partner has disconnected, and the ENERGYDET output is deasserted. The Energy Detection circuit is operational in both Full Power and Low Power modes. n addition, there is a special mode called Automatic Low Power which is enabled by writing a 1 to bit 3 of the Aux Mode 2 register (1Bh). n this mode, a loss of energy on the receive inputs automatically causes the chip to enter the Low Power mode. Similarly, the next time energy is detected, the chip will resume Full Power mode. Page 14 Document 521/2-DS3-R

23 March 2, 1999 BCM521 BCM522 SECTON 5: REGSTER SUMMARY MEDA NDEPENDENT NTERFACE (M) MANAGEMENT NTERFACE: REGSTER PROGRAMMNG The BCM521/522 fully complies with the EEE 82.3u Media ndependent nterface (M) specification. The M management interface registers are serially written-to and read-from using the MDO and MDC pins. A single clock waveform must be provided to the BCM521/522 at a rate of MHz through the MDC pin. The serial data is communicated on the MDO pin. Every MDO bit must have the same period as the MDC clock. The MDO bits are latched on the rising edge of the MDC clock. See Table 6 for the fields in every M instruction s read or write packet frame. Table 6: M Management Frame Format OPERATON PRE ST OP PHYAD REGAD TA DATA DLE DRECTON READ AAAAA RRRRR ZZ Z Z...Z D...D Preamble (PRE). Thirty two consecutive 1 bits must be sent through the MDO pin to the BCM521/522 to signal the beginning of an M instruction. Fewer than 32 1 bits will cause the remainder of the instruction to be ignored, unless the Preamble Suppression mode is enabled (register 1, bit 6). StartofFrame(ST).A 1 pattern indicates that the start of the instruction follows. Operation Code (OP). A READ instruction is indicated by 1, while a WRTE instruction is indicated by 1. PHY Address (PHYAD). A 5-bit PHY address follows next, with the MSB transmitted first. The PHY address allows a single MDO bus to access multiple transceivers. The BCM521/522 supports the full 32-PHY address space. Register Address (REGAD). A 5-bit Register Address follows, with the MSB transmitted first. The register map of the BCM521/522, containing register addresses and bit definitions, are provided on the following pages. Turnaround (TA). The next two bit times are used to avoid contention on the MDO pin when a Read operation is performed. For a Write operation, 1 must be sent to the chip during these two bit times. For a Read operation, the MDO pin must be placed into High-mpedance during these two bit times. The chip will drive the MDO pin to during the second bit time. Data. The last 16 bits of the frame are the actual data bits. For a Write operation, these bits are sent to the BCM521/522. For a Read operation, these bits are driven by the BCM521/522. n either case, the MSB is transmitted first. When writing to the BCM521/522, the data field bits must be stable 1 ns before the rising-edge of MDC, and must be held valid for 1 ns after the rising edge of MDC. When reading from the BCM521/522, the data field bits are valid after the rising edge of MDC until the next rising-edge of MDC. dle. A high impedance state of the MDO line. All drivers are disabled and the PHYs pull-up resistor pulls the line high. Following are two examples of M write and read instructions: n order to put a chip with PHY address 1 into Loopback mode, the following M write instruction must be issued: n order to determine if a PHY is in the link pass state, the following M read instruction must be issued: ZZ ZZZZ ZZZZ ZZZZ ZZZZ For the M read operation, the BCM521/522 will drive the MDO line during the TA and Data fields (the last 17 bit times). Z Z Driven to BCM521/522 Driven by BCM521/522 WRTE AAAAA RRRRR 1 D... D Z Driven to BCM521/522 M REGSTER MAP SUMMARY Table 7 contains the M register summary for the BCM521/522. The register addresses are specified in hex form, and the name of register bits have been abbreviated. When writing to the reserved bits, always write a value, and when reading from these bits, ignore the output value. Never write any value to an undefined register address. The reset value of the registers are shown in the NT column. Document 521/2-DS3-R Page 15