FDDI on Copper with AMD PHY Components

Transcription

1 Advanced Micro Devices FDDI on Copper with AMD PHY Components by Eugen Gershon Publication # Rev. Amendment Issue Date A /0 6/ Advanced Micro Devices, Inc.

2 by Eugen Gershon INTRODUCTION This application note outlines an implementation using AMD PHY components found in either the SUPERNET 1 or SUPERNET 2 families to drive and receive signals over shielded twisted pair media. The circuit described meets the electrical specification of the interoperable solution (PID 16011A) endorsed by AMD, Chipcom, DEC, Motorola, and SynOptics. This interoperable solution (IOS) is designed to minimize the cost of FDDI connections confined within 100 meter range by replacing the optical transceiver and fiber with a shielded twisted pair (STP) transceiver and STP cabling. If a design utilizes AMD s SUPERNET 1 or SUPERNET 2 chipsets, no major changes are required; only a simple interface circuit from the PHY transmitter to the cable and another interface from the cable to the PHY receiver are necessary. The interface can be implemented at minimal cost and with no more board space requirements than available optical Media Interface Connectors (MICs). We built the circuit described herein using surface mount devices on a small daughter board that was form factor and pin-out compatible with the MIC device found on one of our demonstration platforms. When optical PMD devices are removed from the board, the signals at their interface to the system should be kept intact, both in logical content and as voltage/current levels see Figure 1. The optical transmitter accepts both Serial Out from the PHY transmitter and Output Disable control (not used in IOS), at P-ECL levels. Similarly, the optical receiver supplies Serial In to the PHY receiver and Carrier Detect status (here called Link Detect ) at the same P-ECL levels. One new signal handled by the copper interface circuit is a status signal, incorporated into Link Detect, that shows that the cable is connected at both ends. It is detected by both transmitter and receiver because each one uses a separate twisted pair. This solution is designed to work on STP cable, 150 ohm, Type 1 or 2. It specifies a maximum FDDI signal attenuation of 12 db (a factor of 4) at 100 meters. STP Z0 = D A T A I N PHY Serial Out T Copper Interface Connection Detected AND Link Detect Connection Detected Sufficient Power Level ( Signal Detect ) D A T A O U T PHY Serial In R Copper Interface STP Z0 = 15923A-001A Figure 1. Block Diagram Publication # Rev. Amendment Issue Date A /0 6/ Advanced Micro Devices, Inc. 1

3 The transmit waveform going to the cable is required to meet a template based on a differential P-ECL output waveform, such as at the PDT (ENDEC) outputs. This means that AMD parts can be used to drive the STP cable directly (source terminations should be added as required by the IOS specifications). Also, the attenuated signal coming out of the cable at the receiver end is sufficient to allow clock and data recovery by the PDR (EDS) without any need for amplification. Interface The main coupling component to the cable is a transformer, which should be designed for the speed (rise and fall time) and the frequency spectrum of the FDDI signal. Figure 2 shows the data path. The transformer shown is a 1:1 transformer with center taps made by Pulse Engineering, Inc. and are biasing resistors for the output driver stage inside the PDT (ENDEC). The output voltages are roughly 3 volts for LOW and 4 volts for HIGH, therefore the resistor values can be calculated from the average DC current: 3.5 V/ = 10 to 20 ma. R3 and combined with the output impedance of the driver and with the transformer series impedance form the cable termination (150 ohms) at the transmitter end. R3 and will reduce the output signal to the cable by a factor of two. The PDT output driver sees a differential impedance of about 300 ohms in parallel with the 540 ohm biasing resistors. This requires less than its full driving capability of 100 ohms differential. IOS specifies no precompensation at the transmitter end in order to minimize high frequency power levels in the transmitted signal spectrum, which improves the FCC-related performance. Interface The main coupling component at the receiver end is also the transformer. Figure 3 shows the data path., R5 and R6 are bias resistors to bring the input stage of the PDR (EDS) to its DC operating point of about 3.5 volts. R5 provides a small offset voltage between RX and RY to keep the inputs (and outputs) stable in the absence of a carrier. The bias voltage level is isolated from the transformer secondary by C3 and C4. It is also possible to include the transformer in the DC path in order to avoid the need for capacitors C3 and C4. In this case a two-transformer option is a better choice. The, and R3//R5 combination, and the parallel loading of Link Detect (not shown) give the proper cable termination at the receiver end (150 ohms). and with their parallel capacitors and C2 form a high-pass filter that compensates for the high-frequency attenuation and phase shift in the cable. There are many possible correct schemes for compensation. AMD s parts can run a 100 meter link without compensation in most cases, provided the signal is not deteriorated by low performance transformers or external noise. However, in the interest of providing a robust implementation over the IOS specification, compensation has been included. R3 Am79865 (PDT) TY TX STP Either one 1:1 transformer with center taps (as shown), or two simple 1:1 transformers 15923A-002A Figure 2. Interface for Out 2

4 Cable Continuity Detection As mentioned before IOS requires a DC path to check cable connection between two ( master and slave ) stations. The cable continuity signal is one part of Link Detect status, which is comprised of both cable continuity and minimum signal level. STP R3 C3 R5 C4 RY RX Am79866 (PDR) C2 R6 6 KΩ Either one 1:1 transformer with center taps (as shown), or two simple 1:1 transformers 15923A-003A Figure 3. Receive Interface for In Figure 4 shows the required DC path for which there are two interoperable options. The simpler of the two solutions (shown) reports continuity if at least one of the wires in the twisted pair is connected. The second option requires both wires to be connected in order to report continuity, but its implementation uses more components. For example, the second option requires two transformers at each twisted pair end and cannot be implemented with one center-tapped transformer. Both implementation options are shown in the IOS document, Appendix 1. The S-port cable continuity test will signal a high at the emitter output or a low at the collector output when the cable is connected. An M-port needs to check that the voltage across the resistor is within a window. A low voltage indicates no connection; a high voltage indicates a loop-back condition. In both cases cable continuity signal is false. Signal Level Detection The circuit for input signal level detection is based on a fast comparator. In Figures 5 and 6 the comparator is built from a 4 transistor amplifier and a peak detector. In Figure 7, a fast IC comparator is used. Other implementations are shown in the IOS document. If the input signal level is 50 mv or more peak-to-peak, and the cable is connected, the output level of Link Detect goes to high (4 volts). 3

5 M-PORT S-PORT R3 Optocoupler C2 R3 C2 Vmax Vmin 15923A-004A Window Comparator Figure 4. The Simple Option for Cable Continuity Detection Lay-Out During the time we have been experimenting with the copper interface, it has become apparent that one major source of problems is the computer noise coupled into the transmitted and received signals. Little serial inductors were added to the serial lines that come from the PDT or ENDEC (TX, TY), and go to the PDR or EDS (RX, RY), to filter high frequency components that do not belong to the FDDI signal. The protoypes we have built for preliminary testing were based on FASTcards (ENDEC and EDS). The whole interface circuit, including data path, bias resistors and Link Detect, was plugged into the ODL footprint. The newer generation of FASTcards based on PDT/Rs will use exactly the same interface. Detailed schematics of an S-port and an M-port are shown in Figures 5 and 6 respectively. Since FCC compliance is dependent on both the circuit characteristics and the system lay-out and configuration, test results will vary from implementation to implementation. However, the circuit includes noise suppressing elements to minimize EMI. 4

6 S-PORT C3 L1 L3 R5 R3 C2 R6 RY RX Am79866 (PDR) L5 C4 L6 L2 R7 6 KΩ L4 R8 L7 2.5 µh R Q3 R Ω C5 0 Q1 Q2 1 C C8 R31 4 KΩ 9 Q4 Signal Level Detected D1 1N6263 C9 0 L8 1 5 Q1, Q2, Q4: 2N2369 or PN2369 or equivalent Q3: 2N3639, PN3639, 2N3546 or equivalent Ω Ω 4N32 4 Cable Continuity Detected Ω LINK DETECT T2 6 7 L10 L11 8 TY TX 9 Figure 5. Schematic For the S-Port Am79865 (PDT) 15923A-005A 5

7 C3 M-PORT L1 L3 R5 R3 C2 R6 RY RX Am79866 (PDR) L5 C4 L6 L2 R7 6 KΩ L4 R8 L7 2.5 µh L8 C5 R9 0 Q1 2 Q2 1 75Ω 3 C6 4 C7 5 6 Q3 7 8 C8 R31 4 KΩ R Ω 9 Q4 Signal Level Detected D1 1N6263 C Ω R KΩ R KΩ R KΩ R KΩ + U1 LM393 or LM R KΩ L9 Q1, Q2, Q4: 2N2369 or PN2369 or equivalent Q3: 2N3639, PN3639, 2N3546 or equivalent Cable Continuity Detected Ω Ω LINK DETECT Ω T2 6 7 L10 L11 8 TY TX 9 Figure 6. Schematic For the M-Port Am79865 (PDT) 15923A-006A 6

8 S-PORT C3 L1 L3 R5 R3 C2 R6 RY RX Am79866 (PDR) L5 C4 L6 L2 R7 6 KΩ L4 +5V L8 R8 R9 L7 2.5 µh C KΩ Ω U1 LM Ω Signal Level Detected 1 U2 5 C6 2 STROBE 5 V Ω 4N32 4 Cable Continuity Detected 5 D1 1N6263 C7 10 n 6 50 KΩ LINK DETECT T2 7 8 L9 L10 9 TY TX 0 Am79865 (PDT) 15923A-007A Figure 7. Alternative Schematic For the S-Port Using a Fast Comparator For Signal Detect 7