LAN8720A/LAN8720Ai. Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support PRODUCT FEATURES DATASHEET. Highlights.

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1 LAN8720A/LAN8720Ai Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support PRODUCT FEATURES Highlights Single-Chip Ethernet Physical Layer Transceiver (PHY) Comprehensive flexpwr Technology Flexible Power Management Architecture LVCMOS Variable I/O voltage range: +1.6V to +3.6V Integrated 1.2V regulator HP Auto-MDIX support Miniature 24-pin QFN lead-free RoHS compliant package (4 x 4 x 0.85mm height). Target Applications Set-Top Boxes Networked Printers and Servers Test Instrumentation LAN on Motherboard Embedded Telecom Applications Video Record/Playback Systems Cable Modems/Routers DSL Modems/Routers Digital Video Recorders IP and Video Phones Wireless Access Points Digital Televisions Digital Media Adaptors/Servers Gaming Consoles Key Benefits High-Performance 10/100 Ethernet Transceiver Compliant with IEEE802.3/802.3u (Fast Ethernet) Compliant with ISO 802-3/IEEE (10BASE-T) Loop-back modes Auto-negotiation Automatic polarity detection and correction Link status change wake-up detection Vendor specific register functions Supports the reduced pin count RMII interface Power and I/Os Various low power modes Integrated power-on reset circuit Two status LED outputs Latch-Up Performance Exceeds 150mA per EIA/JESD 78, Class II May be used with a single 3.3V supply Additional Features Ability to use a low cost 25Mhz crystal for reduced BOM Packaging 24-pin QFN (4x4 mm) Lead-Free RoHS Compliant package with RMII Environmental Extended commercial temperature range (0 C to +85 C) Industrial temperature range version available (-40 C to +85 C) POE Applications (Refer to SMSC Application Note 17.18) SMSC LAN8720A/LAN8720Ai Revision 1.4 ( )

2 Order Numbers: LAN8720A-CP-TR for 24-pin QFN lead-free RoHS compliant package (0 to +85 C temp) LAN8720Ai-CP-TR for 24-pin QFN lead-free RoHS compliant package (-40 to +85 C temp) Reel size is 4,000. This product meets the halogen maximum concentration values per IEC For RoHS compliance and environmental information, please visit Please contact your SMSC sales representative for additional documentation related to this product such as application notes, anomaly sheets, and design guidelines. Copyright 2012 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC s website at SMSC is a registered trademark of Standard Microsystems Corporation ( SMSC ). Product names and company names are the trademarks of their respective holders. The Microchip name and logo, and the Microchip logo are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Revision 1.4 ( ) 2 SMSC LAN8720A/LAN8720Ai

3 Table of Contents Chapter 1 Introduction General Terms and Conventions General Description Chapter 2 Pin Description and Configuration Pin Assignments Buffer Types Chapter 3 Functional Description Transceiver BASE-TX Transmit BASE-TX Receive BASE-T Transmit BASE-T Receive Auto-negotiation Parallel Detection Restarting Auto-negotiation Disabling Auto-negotiation Half vs. Full Duplex HP Auto-MDIX Support MAC Interface RMII Serial Management Interface (SMI) Interrupt Management Primary Interrupt System Alternate Interrupt System Configuration Straps PHYAD[0]: PHY Address Configuration MODE[2:0]: Mode Configuration REGOFF: Internal +1.2V Regulator Configuration nintsel: nint/refclko Configuration Miscellaneous Functions LEDs Variable Voltage I/O Power-Down Modes Isolate Mode Resets Carrier Sense Link Integrity Test Loopback Operation Application Diagrams Simplified System Level Application Diagram Power Supply Diagram (1.2V Supplied by Internal Regulator) Power Supply Diagram (1.2V Supplied by External Source) Twisted-Pair Interface Diagram (Single Power Supply) Twisted-Pair Interface Diagram (Dual Power Supplies) Chapter 4 Register Descriptions Register Nomenclature Control and Status Registers Basic Control Register SMSC LAN8720A/LAN8720Ai 3 Revision 1.4 ( )

4 4.2.2 Basic Status Register PHY Identifier 1 Register PHY Identifier 2 Register Auto Negotiation Advertisement Register Auto Negotiation Link Partner Ability Register Auto Negotiation Expansion Register Mode Control/Status Register Special Modes Register Symbol Error Counter Register Special Control/Status Indications Register Interrupt Source Flag Register Interrupt Mask Register PHY Special Control/Status Register Chapter 5 Operational Characteristics Absolute Maximum Ratings* Operating Conditions** Power Consumption REF_CLK In Mode REF_CLK Out Mode DC Specifications AC Specifications Equivalent Test Load Power Sequence Timing Power-On nrst & Configuration Strap Timing RMII Interface Timing SMI Timing Clock Circuit Chapter 6 Package Outline Chapter 7 Revision History Revision 1.4 ( ) 4 SMSC LAN8720A/LAN8720Ai

5 List of Figures Figure 1.1 System Block Diagram Figure 1.2 Architectural Overview Figure QFN Pin Assignments (TOP VIEW) Figure BASE-TX Transmit Data Path Figure BASE-TX Receive Data Path Figure 3.3 Relationship Between Received Data and Specific MII Signals Figure 3.4 Direct Cable Connection vs. Cross-over Cable Connection Figure 3.5 MDIO Timing and Frame Structure - READ Cycle Figure 3.6 MDIO Timing and Frame Structure - WRITE Cycle Figure 3.7 External 50MHz clock sources the REF_CLK Figure 3.8 Sourcing REF_CLK from a 25MHz Crystal Figure 3.9 Sourcing REF_CLK from External 25MHz Source Figure 3.10 LED1/REGOFF Polarity Configuration Figure 3.11 LED2/nINTSEL Polarity Configuration Figure 3.12 Near-end Loopback Block Diagram Figure 3.13 Far Loopback Block Diagram Figure 3.14 Connector Loopback Block Diagram Figure 3.15 Simplified System Level Application Diagram Figure 3.16 Power Supply Diagram (1.2V Supplied by Internal Regulator) Figure 3.17 Power Supply Diagram (1.2V Supplied by External Source) Figure 3.18 Twisted-Pair Interface Diagram (Single Power Supply) Figure 3.19 Twisted-Pair Interface Diagram (Dual Power Supplies) Figure 5.1 Output Equivalent Test Load Figure 5.2 Power Sequence Timing Figure 5.3 Power-On nrst & Configuration Strap Timing Figure 5.4 RMII Timing (REF_CLK Out Mode) Figure 5.5 RMII Timing (REF_CLK In Mode) Figure 5.6 SMI Timing SMSC LAN8720A/LAN8720Ai 5 Revision 1.4 ( )

6 List of Tables Table 2.1 RMII Signals Table 2.2 LED Pins Table 2.3 Serial Management Interface (SMI) Pins Table 2.4 Ethernet Pins Table 2.5 Miscellaneous Pins Table 2.6 Analog Reference Pins Table 2.7 Power Pins Table QFN Package Pin Assignments Table 2.9 Buffer Types Table 3.1 4B/5B Code Table Table 3.2 Interrupt Management Table Table 3.3 Alternative Interrupt System Management Table Table 3.4 MODE[2:0] Bus Table 3.5 Pin Names for Mode Bits Table 3.6 nintsel Configuration Table 4.1 Register Bit Types Table 4.2 SMI Register Map Table 5.1 Device Only Current Consumption and Power Dissipation (REF_CLK In Mode) Table 5.2 Device Only Current Consumption and Power Dissipation (REF_CLK Out Mode) Table 5.3 Non-Variable I/O Buffer Characteristics Table 5.4 Variable I/O Buffer Characteristics Table BASE-TX Transceiver Characteristics Table BASE-T Transceiver Characteristics Table 5.7 Power Sequence Timing Values Table 5.8 Power-On nrst & Configuration Strap Timing Values Table 5.9 RMII Timing Values (REF_CLK Out Mode) Table 5.10 RMII Timing Values (REF_CLK In Mode) Table 5.11 RMII CLKIN (REF_CLK) Timing Values Table 5.12 SMI Timing Values Table 5.13 Crystal Specifications Table 7.1 Customer Revision History Revision 1.4 ( ) 6 SMSC LAN8720A/LAN8720Ai

7 Chapter 1 Introduction 1.1 General Terms and Conventions The following is list of the general terms used throughout this document: BYTE FIFO MAC RMII TM N/A X RESERVED SMI 8-bits First In First Out buffer; often used for elasticity buffer Media Access Controller Reduced Media Independent Interface TM Not Applicable Indicates that a logic state is don t care or undefined. Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must always be zero for write operations. Unless otherwise noted, values are not guaranteed when reading reserved bits. Unless otherwise noted, do not read or write to reserved addresses. Serial Management Interface 1.2 General Description The LAN8720A/LAN8720Ai is a low-power 10BASE-T/100BASE-TX physical layer (PHY) transceiver with variable I/O voltage that is compliant with the IEEE standards. The LAN8720A/LAN8720Ai supports communication with an Ethernet MAC via a standard RMII interface. It contains a full-duplex 10-BASE-T/100BASE-TX transceiver and supports 10Mbps (10BASE-T) and 100Mbps (100BASE-TX) operation. The LAN8720A/LAN8720Ai implements autonegotiation to automatically determine the best possible speed and duplex mode of operation. HP Auto-MDIX support allows the use of direct connect or cross-over LAN cables. The LAN8720A/LAN8720Ai supports both IEEE compliant and vendor-specific register functions. However, no register access is required for operation. The initial configuration may be selected via the configuration pins as described in Section 3.7, "Configuration Straps," on page 31. Register-selectable configuration options may be used to further define the functionality of the transceiver. Per IEEE standards, all digital interface pins are tolerant to 3.6V. The device can be configured to operate on a single 3.3V supply utilizing an integrated 3.3V to 1.2V linear regulator. The linear regulator may be optionally disabled, allowing usage of a high efficiency external regulator for lower system power dissipation. The LAN8720A/LAN8720Ai is available in both extended commercial and industrial temperature range versions. A typical system application is shown in Figure 1.1. SMSC LAN8720A/LAN8720Ai 7 Revision 1.4 ( )

8 10/100 Ethernet MAC RMII LAN8720A/ LAN8720Ai MDI Transformer RJ45 Mode LED Crystal or Clock Oscillator Figure 1.1 System Block Diagram MODE[0:2] nrst RMIISEL Mode Control Reset Control Auto- Negotiation 100M TX Logic 100M Transmitter Transmitter HP Auto-MDIX TXP/TXN RXP/RXN TXD[0:1] TXEN RXD[0:1] RXER CRS_DV MDC MDIO RMII Logic SMI Management Control 100M RX Logic 10M RX Logic 10M TX Logic DSP System: Clock Data Recovery Equalizer Receiver 10M PLL 10M Transmitter Analog-to- Digital 100M PLL Squeltch & Filters MDIX Control PLL Interrupt Generator LEDs Central Bias XTAL1/CLKIN XTAL2 nint LED1 LED2 RBIAS LAN8720A/LAN8720Ai PHY Address Latches PHYAD0 Figure 1.2 Architectural Overview Revision 1.4 ( ) 8 SMSC LAN8720A/LAN8720Ai

9 Chapter 2 Pin Description and Configuration VDD1A TXN TXP RXN RXP RBIAS VDD2A 1 18 TXD1 TXD0 17 SMSC LAN8720A/LAN8720Ai 24 PIN QFN (TOP VIEW) 2 LED2/nINTSEL TXEN 16 3 LED1/REGOFF VSS nrst 15 4 XTAL2 nint/refclko 14 5 XTAL1/CLKIN MDC 13 6 VDDCR MDIO CRS_DV/MODE2 RXER/PHYAD0 VDDIO RXD0/MODE0 RXD1/MODE1 NOTE: Exposed pad (VSS) on bottom of package must be connected to ground Figure QFN Pin Assignments (TOP VIEW) When a lower case n is used at the beginning of the signal name, it indicates that the signal is active low. For example, nrst indicates that the reset signal is active low. The buffer type for each signal is indicated in the BUFFER TYPE column. A description of the buffer types is provided in Section 2.2. SMSC LAN8720A/LAN8720Ai 9 Revision 1.4 ( )

10 Table 2.1 RMII Signals NUM PINS NAME SYMBOL BUFFER TYPE DESCRIPTION 1 1 Transmit Data 0 Transmit Data 1 TXD0 VIS The MAC transmits data to the transceiver using this signal. TXD1 VIS The MAC transmits data to the transceiver using this signal. 1 Transmit Enable TXEN VIS (PD) Indicates that valid transmission data is present on TXD[1:0]. Receive Data 0 RXD0 VO8 Bit 0 of the 2 data bits that are sent by the transceiver on the receive path. 1 PHY Operating Mode 0 Configuration Strap MODE0 VIS (PU) Combined with MODE1 and MODE2, this configuration strap sets the default PHY mode. See Note 2.1 for more information on configuration straps. Refer to Section 3.7.2, "MODE[2:0]: Mode Configuration," on page 31 for additional details. Receive Data 1 RXD1 VO8 Bit 1 of the 2 data bits that are sent by the transceiver on the receive path. 1 PHY Operating Mode 1 Configuration Strap MODE1 VIS (PU) Combined with MODE0 and MODE2, this configuration strap sets the default PHY mode. See Note 2.1 for more information on configuration straps. Refer to Section 3.7.2, "MODE[2:0]: Mode Configuration," on page 31 for additional details. Receive Error RXER VO8 This signal is asserted to indicate that an error was detected somewhere in the frame presently being transferred from the transceiver. 1 PHY Address 0 Configuration Strap PHYAD0 VIS (PD) This configuration strap sets the transceiver s SMI address. See Note 2.1 for more information on configuration straps. Refer to Section 3.7.1, "PHYAD[0]: PHY Address Configuration," on page 31 for additional information. Revision 1.4 ( ) 10 SMSC LAN8720A/LAN8720Ai

11 Table 2.1 RMII Signals (continued) NUM PINS NAME SYMBOL BUFFER TYPE DESCRIPTION 1 Carrier Sense / Receive Data Valid PHY Operating Mode 2 Configuration Strap CRS_DV VO8 This signal is asserted to indicate the receive medium is non-idle. When a 10BASE-T packet is received, CRS_DV is asserted, but RXD[1:0] is held low until the SFD byte ( ) is received. MODE2 VIS (PU) Per the RMII standard, transmitted data is not looped back onto the receive data pins in 10BASE-T half-duplex mode. Combined with MODE0 and MODE1, this configuration strap sets the default PHY mode. See Note 2.1 for more information on configuration straps. Refer to Section 3.7.2, "MODE[2:0]: Mode Configuration," on page 31 for additional details. Note 2.1 Configuration strap values are latched on power-on reset and system reset. Configuration straps are identified by an underlined symbol name. Signals that function as configuration straps must be augmented with an external resistor when connected to a load. Refer to Section 3.7, "Configuration Straps," on page 31 for additional information. Table 2.2 LED Pins NUM PINS NAME SYMBOL BUFFER TYPE DESCRIPTION LED 1 LED1 O12 Link activity LED Indication. This pin is driven active when a valid link is detected and blinks when activity is detected. Refer to Section 3.8.1, "LEDs," on page 37 for additional LED information. Regulator Off Configuration Strap REGOFF IS (PD) This configuration strap is used to disable the internal 1.2V regulator. When the regulator is disabled, external 1.2V must be supplied to VDDCR. 1 When REGOFF is pulled high to VDD2A with an external resistor, the internal regulator is disabled. When REGOFF is floating or pulled low, the internal regulator is enabled (default). See Note 2.2 for more information on configuration straps. Refer to Section 3.7.3, "REGOFF: Internal +1.2V Regulator Configuration," on page 32 for additional details. SMSC LAN8720A/LAN8720Ai 11 Revision 1.4 ( )

12 Table 2.2 LED Pins (continued) NUM PINS NAME SYMBOL BUFFER TYPE DESCRIPTION LED 2 LED2 O12 Link Speed LED Indication. This pin is driven active when the operating speed is 100Mbps. It is inactive when the operating speed is 10Mbps or during line isolation. Refer to Section 3.8.1, "LEDs," on page 37 for additional LED information. 1 nint/ REFCLKO Function Select Configuration Strap nintsel IS (PU) This configuration strap selects the mode of the nint/refclko pin. When nintsel is floated or pulled to VDD2A, nint is selected for operation on the nint/refclko pin (default). When nintsel is pulled low to VSS, REFCLKO is selected for operation on the nint/refclko pin. See Note 2.2 for more information on configuration straps. Refer to See Section , "nintsel and LED2 Polarity Selection," on page 37 for additional information. Note 2.2 Configuration strap values are latched on power-on reset and system reset. Configuration straps are identified by an underlined symbol name. Signals that function as configuration straps must be augmented with an external resistor when connected to a load. Refer to Section 3.7, "Configuration Straps," on page 31 for additional information. Table 2.3 Serial Management Interface (SMI) Pins NUM PINS NAME SYMBOL BUFFER TYPE DESCRIPTION 1 SMI Data Input/Output MDIO VIS/ VOD8 Serial Management Interface data input/output 1 SMI Clock MDC VIS Serial Management Interface clock Table 2.4 Ethernet Pins NUM PINS NAME SYMBOL BUFFER TYPE DESCRIPTION 1 1 Ethernet TX/RX Positive Channel 1 Ethernet TX/RX Negative Channel 1 TXP AIO Transmit/Receive Positive Channel 1 TXN AIO Transmit/Receive Negative Channel 1 Revision 1.4 ( ) 12 SMSC LAN8720A/LAN8720Ai

13 Table 2.4 Ethernet Pins (continued) NUM PINS NAME SYMBOL BUFFER TYPE DESCRIPTION 1 1 Ethernet TX/RX Positive Channel 2 Ethernet TX/RX Negative Channel 2 RXP AIO Transmit/Receive Positive Channel 2 RXN AIO Transmit/Receive Negative Channel 2 Table 2.5 Miscellaneous Pins NUM PINS NAME SYMBOL BUFFER TYPE DESCRIPTION 1 1 External Crystal Input External Clock Input External Crystal Output XTAL1 ICLK External crystal input CLKIN ICLK Single-ended clock oscillator input. When using a single ended clock oscillator, XTAL2 should be left unconnected. XTAL2 OCLK External crystal output 1 External Reset nrst VIS (PU) System reset. This signal is active low. 1 Interrupt Output Reference Clock Output nint VOD8 (PU) Active low interrupt output. Place an external resistor pull-up to VDDIO. Refer to Section 3.6, "Interrupt Management," on page 29 for additional details on device interrupts. Refer to Section , "nintsel and LED2 Polarity Selection," on page 37 for details on how the nintsel configuration strap is used to determine the function of this pin. REFCLKO VO8 This optional 50MHz clock output is derived from the 25MHz crystal oscillator. REFCLKO is selectable via the nintsel configuration strap. Refer Section , "REF_CLK Out Mode," on page 34 for additional details. Refer to Section , "nintsel and LED2 Polarity Selection," on page 37 for details on how the nintsel configuration strap is used to determine the function of this pin. SMSC LAN8720A/LAN8720Ai 13 Revision 1.4 ( )

14 Table 2.6 Analog Reference Pins NUM PINS NAME SYMBOL BUFFER TYPE DESCRIPTION 1 External 1% Bias Resistor Input RBIAS AI This pin requires connection of a 12.1k ohm (1%) resistor to ground. Refer to the LAN8720A/LAN8720Ai reference schematic for connection information. The nominal voltage is 1.2V and the resistor will dissipate approximately 1mW of power. Table 2.7 Power Pins NUM PINS NAME SYMBOL BUFFER TYPE DESCRIPTION V to +3.6V Variable I/O Power +1.2V Digital Core Power Supply +3.3V Channel 1 Analog Port Power +3.3V Channel 2 Analog Port Power VDDIO P +1.6V to +3.6V variable I/O power Refer to the LAN8720A/LAN8720Ai reference schematic for connection information. VDDCR P Supplied by the on-chip regulator unless configured for regulator off mode via the REGOFF configuration strap. Refer to the LAN8720A/LAN8720Ai reference schematic for connection information. 1 uf and 470 pf decoupling capacitors in parallel to ground should be used on this pin. VDD1A P +3.3V Analog Port Power to Channel 1 Refer to the LAN8720A/LAN8720Ai reference schematic for connection information. VDD2A P +3.3V Analog Port Power to Channel 2 and the internal regulator. Refer to the LAN8720A/LAN8720Ai reference schematic for connection information. 1 Ground VSS P Common ground. This exposed pad must be connected to the ground plane with a via array. Revision 1.4 ( ) 14 SMSC LAN8720A/LAN8720Ai

15 2.1 Pin Assignments Table QFN Package Pin Assignments PIN NUM PIN NAME PIN NUM PIN NAME 1 VDD2A 13 MDC 2 LED2/nINTSEL 14 nint/refclko 3 LED1/REGOFF 15 nrst 4 XTAL2 16 TXEN 5 XTAL1/CLKIN 17 TXD0 6 VDDCR 18 TXD1 7 RXD1/MODE1 19 VDD1A 8 RXD0/MODE0 20 TXN 9 VDDIO 21 TXP 10 RXER/PHYAD0 22 RXN 11 CRS_DV/MODE2 23 RXP 12 MDIO 24 RBIAS SMSC LAN8720A/LAN8720Ai 15 Revision 1.4 ( )

16 2.2 Buffer Types Table 2.9 Buffer Types BUFFER TYPE DESCRIPTION IS O12 VIS VO8 VOD8 PU PD AI AIO ICLK OCLK P Schmitt-triggered input Output with 12mA sink and 12mA source Variable voltage Schmitt-triggered input Variable voltage output with 8mA sink and 8mA source Variable voltage open-drain output with 8mA sink 50uA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pullups are always enabled. Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on internal resistors to drive signals external to the device. When connected to a load that must be pulled high, an external resistor must be added. 50uA (typical) internal pull-down. Unless otherwise noted in the pin description, internal pull-downs are always enabled. Analog input Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on internal resistors to drive signals external to the device. When connected to a load that must be pulled low, an external resistor must be added. Analog bi-directional Crystal oscillator input pin Crystal oscillator output pin Power pin The digital signals are not 5V tolerant. Refer to Section 5.1, "Absolute Maximum Ratings*," on page 63 for additional buffer information. Note 2.3 Sink and source capabilities are dependant on the VDDIO voltage. Refer to Section 5.1, "Absolute Maximum Ratings*," on page 63 for additional information. Revision 1.4 ( ) 16 SMSC LAN8720A/LAN8720Ai

17 Chapter 3 Functional Description Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support This chapter provides functional descriptions of the various device features. These features have been categorized into the following sections: Transceiver Auto-negotiation HP Auto-MDIX Support MAC Interface Serial Management Interface (SMI) Interrupt Management Configuration Straps Miscellaneous Functions Application Diagrams 3.1 Transceiver BASE-TX Transmit The 100BASE-TX transmit data path is shown in Figure 3.1. Each major block is explained in the following subsections. PLL MAC Ext Ref_CLK RMII 50Mhz by 2 bits RMII 25MHz by 4 bits 4B/5B Encoder 25MHz by 5 bits Scrambler and PISO 125 Mbps Serial NRZI Converter NRZI MLT-3 Converter MLT-3 Tx Driver MLT-3 Magnetics MLT-3 RJ45 MLT-3 CAT-5 Figure BASE-TX Transmit Data Path BASE-TX Transmit Data Across the RMII Interface The MAC controller drives the transmit data onto the TXD bus and asserts TXEN to indicate valid data. The data is latched by the transceiver s RMII block on the rising edge of REF_CLK. The data is in the form of 2-bit wide 50MHz data. SMSC LAN8720A/LAN8720Ai 17 Revision 1.4 ( )

18 B/5B Encoding The transmit data passes from the RMII block to the 4B/5B encoder. This block encodes the data from 4-bit nibbles to 5-bit symbols (known as code-groups ) according to Table 3.1. Each 4-bit data-nibble is mapped to 16 of the 32 possible code-groups. The remaining 16 code-groups are either used for control information or are not valid. The first 16 code-groups are referred to by the hexadecimal values of their corresponding data nibbles, 0 through F. The remaining code-groups are given letter designations with slashes on either side. For example, an IDLE code-group is /I/, a transmit error code-group is /H/, etc. Table 3.1 4B/5B Code Table CODE GROUP SYM RECEIVER INTERPRETATION TRANSMITTER INTERPRETATION DATA DATA A A 1010 A B B 1011 B C C 1100 C D D 1101 D E E 1110 E F F 1111 F I IDLE Sent after /T/R until TXEN J First nibble of SSD, translated to 0101 following IDLE, else RXER K Second nibble of SSD, translated to 0101 following J, else RXER T First nibble of ESD, causes de-assertion of CRS if followed by /R/, else assertion of RXER R Second nibble of ESD, causes deassertion of CRS if following /T/, else assertion of RXER Sent for rising TXEN Sent for rising TXEN Sent for falling TXEN Sent for falling TXEN H Transmit Error Symbol Sent for rising TXER V INVALID, RXER if during RXDV INVALID Revision 1.4 ( ) 18 SMSC LAN8720A/LAN8720Ai

19 Table 3.1 4B/5B Code Table (continued) CODE GROUP SYM RECEIVER INTERPRETATION TRANSMITTER INTERPRETATION V INVALID, RXER if during RXDV INVALID V INVALID, RXER if during RXDV INVALID V INVALID, RXER if during RXDV INVALID V INVALID, RXER if during RXDV INVALID V INVALID, RXER if during RXDV INVALID V INVALID, RXER if during RXDV INVALID V INVALID, RXER if during RXDV INVALID V INVALID, RXER if during RXDV INVALID V INVALID, RXER if during RXDV INVALID Scrambling Repeated data patterns (especially the IDLE code-group) can have power spectral densities with large narrow-band peaks. Scrambling the data helps eliminate these peaks and spread the signal power more uniformly over the entire channel bandwidth. This uniform spectral density is required by FCC regulations to prevent excessive EMI from being radiated by the physical wiring. The seed for the scrambler is generated from the transceiver address, PHYAD, ensuring that in multiple-transceiver applications, such as repeaters or switches, each transceiver will have its own scrambler sequence. The scrambler also performs the Parallel In Serial Out conversion (PISO) of the data NRZI and MLT-3 Encoding The scrambler block passes the 5-bit wide parallel data to the NRZI converter where it becomes a serial 125MHz NRZI data stream. The NRZI is encoded to MLT-3. MLT-3 is a tri-level code where a change in the logic level represents a code bit 1 and the logic output remaining at the same level represents a code bit M Transmit Driver The MLT3 data is then passed to the analog transmitter, which drives the differential MLT-3 signal, on outputs TXP and TXN, to the twisted pair media across a 1:1 ratio isolation transformer. The 10BASE- T and 100BASE-TX signals pass through the same transformer so that common magnetics can be used for both. The transmitter drives into the 100Ω impedance of the CAT-5 cable. Cable termination and impedance matching require external components M Phase Lock Loop (PLL) The 100M PLL locks onto reference clock and generates the 125MHz clock used to drive the 125 MHz logic and the 100BASE-TX transmitter. SMSC LAN8720A/LAN8720Ai 19 Revision 1.4 ( )

20 BASE-TX Receive The 100BASE-TX receive data path is shown in Figure 3.2. Each major block is explained in the following subsections. PLL MAC Ext Ref_CLK RMII 50Mhz by 2 bits RMII 25MHz by 4 bits 4B/5B Decoder 25MHz by 5 bits Descrambler and SIPO 125 Mbps Serial NRZI Converter NRZI MLT-3 Converter MLT-3 DSP: Timing recovery, Equalizer and BLW Correction A/D Converter MLT-3 Magnetics MLT-3 RJ45 MLT-3 CAT-5 6 bit Data M Receive Input Figure BASE-TX Receive Data Path The MLT-3 from the cable is fed into the transceiver (on inputs RXP and RXN) via a 1:1 ratio transformer. The ADC samples the incoming differential signal at a rate of 125M samples per second. Using a 64-level quanitizer, it generates 6 digital bits to represent each sample. The DSP adjusts the gain of the ADC according to the observed signal levels such that the full dynamic range of the ADC can be used Equalizer, Baseline Wander Correction and Clock and Data Recovery The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates for phase and amplitude distortion caused by the physical channel consisting of magnetics, connectors, and CAT- 5 cable. The equalizer can restore the signal for any good-quality CAT-5 cable between 1m and 150m. If the DC content of the signal is such that the low-frequency components fall below the low frequency pole of the isolation transformer, then the droop characteristics of the transformer will become significant and Baseline Wander (BLW) on the received signal will result. To prevent corruption of the received data, the transceiver corrects for BLW and can receive the ANSI X FDDI TP-PMD defined killer packet with no bit errors. The 100M PLL generates multiple phases of the 125MHz clock. A multiplexer, controlled by the timing unit of the DSP, selects the optimum phase for sampling the data. This is used as the received recovered clock. This clock is used to extract the serial data from the received signal. Revision 1.4 ( ) 20 SMSC LAN8720A/LAN8720Ai

21 NRZI and MLT-3 Decoding The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then converted to an NRZI data stream Descrambling Alignment The descrambler performs an inverse function to the scrambler in the transmitter and also performs the Serial In Parallel Out (SIPO) conversion of the data. During reception of IDLE (/I/) symbols. the descrambler synchronizes its descrambler key to the incoming stream. Once synchronization is achieved, the descrambler locks on this key and is able to descramble incoming data. Special logic in the descrambler ensures synchronization with the remote transceiver by searching for IDLE symbols within a window of 4000 bytes (40us). This window ensures that a maximum packet size of 1514 bytes, allowed by the IEEE standard, can be received with no interference. If no IDLEsymbols are detected within this time-period, receive operation is aborted and the descrambler re-starts the synchronization process. The de-scrambled signal is then aligned into 5-bit code-groups by recognizing the /J/K/ Start-of-Stream Delimiter (SSD) pair at the start of a packet. Once the code-word alignment is determined, it is stored and utilized until the next start of frame B/4B Decoding The 5-bit code-groups are translated into 4-bit data nibbles according to the 4B/5B table. The translated data is presented on the RXD[1:0] signal lines. The SSD, /J/K/, is translated to as the first 2 nibbles of the MAC preamble. Reception of the SSD causes the transceiver to assert the receive data valid signal, indicating that valid data is available on the RXD bus. Successive valid codegroups are translated to data nibbles. Reception of either the End of Stream Delimiter (ESD) consisting of the /T/R/ symbols, or at least two /I/ symbols causes the transceiver to de-assert the carrier sense and receive data valid signals. These symbols are not translated into data Receive Data Valid Signal The Receive Data Valid signal (RXDV) indicates that recovered and decoded nibbles are being presented on the RXD[1:0] outputs synchronous to RXCLK. RXDV becomes active after the /J/K/ delimiter has been recognized and RXD is aligned to nibble boundaries. It remains active until either the /T/R/ delimiter is recognized or link test indicates failure or SIGDET becomes false. RXDV is asserted when the first nibble of translated /J/K/ is ready for transfer over the Media Independent Interface (MII mode). CLEAR-TEXT J K D data data data data T R Idle RX_CLK RX_DV RXD D data data data data Figure 3.3 Relationship Between Received Data and Specific MII Signals SMSC LAN8720A/LAN8720Ai 21 Revision 1.4 ( )

22 Receiver Errors During a frame, unexpected code-groups are considered receive errors. Expected code groups are the DATA set (0 through F), and the /T/R/ (ESD) symbol pair. When a receive error occurs, the RXER signal is asserted and arbitrary data is driven onto the RXD[1:0] lines. Should an error be detected during the time that the /J/K/ delimiter is being decoded (bad SSD error), RXER is asserted true and the value 1110 is driven onto the RXD[1:0] lines. Note that the Valid Data signal is not yet asserted when the bad SSD error occurs M Receive Data Across the RMII Interface The 2-bit data nibbles are sent to the RMII block. These data nibbles are clocked to the controller at a rate of 50MHz. The controller samples the data on the rising edge of XTAL1/CLKIN (REF_CLK). To ensure that the setup and hold requirements are met, the nibbles are clocked out of the transceiver on the falling edge of XTAL1/CLKIN (REF_CLK) BASE-T Transmit Data to be transmitted comes from the MAC layer controller. The 10BASE-T transmitter receives 4-bit nibbles from the MII at a rate of 2.5MHz and converts them to a 10Mbps serial data stream. The data stream is then Manchester-encoded and sent to the analog transmitter, which drives a signal onto the twisted pair via the external magnetics. The 10M transmitter uses the following blocks: MII (digital) TX 10M (digital) 10M Transmitter (analog) 10M PLL (analog) M Transmit Data Across the RMII Interface The MAC controller drives the transmit data onto the TXD bus. TXD[1:0] shall transition synchronously with respect to REF_CLK. When TXEN is asserted, TXD[1:0] are accepted for transmission by the device. TXD[1:0] shall be 00 to indicate idle when TXEN is deasserted. Values of TXD[1:0] other than 00 when TXEN is deasserted are reserved for out-of-band signalling (to be defined). Values other than 00 on TXD[1:0] while TXEN is deasserted shall be ignored by the device.txd[1:0] shall provide valid data for each REF_CLK period while TXEN is asserted. In order to comply with legacy 10BASE-T MAC/Controllers, in half-duplex mode the transceiver loops back the transmitted data, on the receive path. This does not confuse the MAC/Controller since the COL signal is not asserted during this time. The transceiver also supports the SQE (Heartbeat) signal Manchester Encoding The 4-bit wide data is sent to the 10M TX block. The nibbles are converted to a 10Mbps serial NRZI data stream. The 10M PLL locks onto the external clock or internal oscillator and produces a 20MHz clock. This is used to Manchester encode the NRZ data stream. When no data is being transmitted (TXEN is low), the 10M TX block outputs Normal Link Pulses (NLPs) to maintain communications with the remote link partner M Transmit Drivers The Manchester encoded data is sent to the analog transmitter where it is shaped and filtered before being driven out as a differential signal across the TXP and TXN outputs. Revision 1.4 ( ) 22 SMSC LAN8720A/LAN8720Ai

23 BASE-T Receive The 10BASE-T receiver gets the Manchester- encoded analog signal from the cable via the magnetics. It recovers the receive clock from the signal and uses this clock to recover the NRZI data stream. This 10M serial data is converted to 4-bit data nibbles which are passed to the controller via MII at a rate of 2.5MHz. This 10M receiver uses the following blocks: Filter and SQUELCH (analog) 10M PLL (analog) RX 10M (digital) MII (digital) M Receive Input and Squelch The Manchester signal from the cable is fed into the transceiver (on inputs RXP and RXN) via 1:1 ratio magnetics. It is first filtered to reduce any out-of-band noise. It then passes through a SQUELCH circuit. The SQUELCH is a set of amplitude and timing comparators that normally reject differential voltage levels below 300mV and detect and recognize differential voltages above 585mV Manchester Decoding The output of the SQUELCH goes to the 10M RX block where it is validated as Manchester encoded data. The polarity of the signal is also checked. If the polarity is reversed (local RXP is connected to RXN of the remote partner and vice versa), the condition is identified and corrected. The reversed condition is indicated by the XPOL bit of the Special Control/Status Indications Register. The 10M PLL is locked onto the received Manchester signal, from which the 20MHz cock is generated. Using this clock, the Manchester encoded data is extracted and converted to a 10MHz NRZI data stream. It is then converted from serial to 4-bit wide parallel data. The 10M RX block also detects valid 10Base-T IDLE signals - Normal Link Pulses (NLPs) - to maintain the link M Receive Data Across the RMII Interface The 2-bit data nibbles are sent to the RMII block. These data nibbles are valid on the rising edge of the RMII REF_CLK Jabber Detection Jabber is a condition in which a station transmits for a period of time longer than the maximum permissible packet length, usually due to a fault condition, which results in holding the TXEN input for a long period. Special logic is used to detect the jabber state and abort the transmission to the line within 45ms. Once TXEN is deasserted, the logic resets the jabber condition. As shown in Section 4.2.2, "Basic Status Register," on page 50, the Jabber Detect bit indicates that a jabber condition was detected. 3.2 Auto-negotiation The purpose of the auto-negotiation function is to automatically configure the transceiver to the optimum link parameters based on the capabilities of its link partner. Auto-negotiation is a mechanism for exchanging configuration information between two link-partners and automatically selecting the highest performance mode of operation supported by both sides. Auto-negotiation is fully defined in clause 28 of the IEEE specification. Once auto-negotiation has completed, information about the resolved link can be passed back to the controller via the Serial Management Interface (SMI). The results of the negotiation process are SMSC LAN8720A/LAN8720Ai 23 Revision 1.4 ( )

24 reflected in the Speed Indication bits of the PHY Special Control/Status Register, as well as in the Auto Negotiation Link Partner Ability Register. The auto-negotiation protocol is a purely physical layer activity and proceeds independently of the MAC controller. The advertised capabilities of the transceiver are stored in the Auto Negotiation Advertisement Register. The default advertised by the transceiver is determined by user-defined on-chip signal options. The following blocks are activated during an Auto-negotiation session: Auto-negotiation (digital) 100M ADC (analog) 100M PLL (analog) 100M equalizer/blw/clock recovery (DSP) 10M SQUELCH (analog) 10M PLL (analog) 10M Transmitter (analog) When enabled, auto-negotiation is started by the occurrence of one of the following events: Hardware reset Software reset Power-down reset Link status down Setting the Restart Auto-Negotiate bit of the Basic Control Register On detection of one of these events, the transceiver begins auto-negotiation by transmitting bursts of Fast Link Pulses (FLP), which are bursts of link pulses from the 10M transmitter. They are shaped as Normal Link Pulses and can pass uncorrupted down CAT-3 or CAT-5 cable. A Fast Link Pulse Burst consists of up to 33 pulses. The 17 odd-numbered pulses, which are always present, frame the FLP burst. The 16 even-numbered pulses, which may be present or absent, contain the data word being transmitted. Presence of a data pulse represents a 1, while absence represents a 0. The data transmitted by an FLP burst is known as a Link Code Word. These are defined fully in IEEE clause 28. In summary, the transceiver advertises compliance in its selector field (the first 5 bits of the Link Code Word). It advertises its technology ability according to the bits set in the Auto Negotiation Advertisement Register. There are 4 possible matches of the technology abilities. In the order of priority these are: 100M Full Duplex (Highest Priority) 100M Half Duplex 10M Full Duplex 10M Half Duplex (Lowest Priority) If the full capabilities of the transceiver are advertised (100M, Full Duplex), and if the link partner is capable of 10M and 100M, then auto-negotiation selects 100M as the highest performance mode. If the link partner is capable of half and full duplex modes, then auto-negotiation selects full duplex as the highest performance operation. Once a capability match has been determined, the link code words are repeated with the acknowledge bit set. Any difference in the main content of the link code words at this time will cause auto-negotiation to re-start. Auto-negotiation will also re-start if not all of the required FLP bursts are received. The capabilities advertised during auto-negotiation by the transceiver are initially determined by the logic levels latched on the MODE[2:0] configuration straps after reset completes. These configuration straps can also be used to disable auto-negotiation on power-up. Refer to Section 3.7.2, "MODE[2:0]: Mode Configuration," on page 31 for additional information. Revision 1.4 ( ) 24 SMSC LAN8720A/LAN8720Ai

25 Writing the bits 8 through 5 of the Auto Negotiation Advertisement Register allows software control of the capabilities advertised by the transceiver. Writing the Auto Negotiation Advertisement Register does not automatically re-start auto-negotiation. The Restart Auto-Negotiate bit of the Basic Control Register must be set before the new abilities will be advertised. Auto-negotiation can also be disabled via software by clearing the Auto-Negotiation Enable bit of the Basic Control Register. The device does not support Next Page capability Parallel Detection If the LAN8720A/LAN8720Ai is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs are detected), it is able to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses. In this case the link is presumed to be half duplex per the IEEE standard. This ability is known as Parallel Detection. This feature ensures interoperability with legacy link partners. If a link is formed via parallel detection, then the Link Partner Auto-Negotiation Able bit of the Auto Negotiation Expansion Register is cleared to indicate that the Link Partner is not capable of autonegotiation. The controller has access to this information via the management interface. If a fault occurs during parallel detection, the Parallel Detection Fault bit of Link Partner Auto-Negotiation Able is set. Auto Negotiation Link Partner Ability Register is used to store the link partner ability information, which is coded in the received FLPs. If the link partner is not auto-negotiation capable, then the Auto Negotiation Link Partner Ability Register is updated after completion of parallel detection to reflect the speed capability of the link partner Restarting Auto-negotiation Auto-negotiation can be restarted at any time by setting the Restart Auto-Negotiate bit of the Basic Control Register. Auto-negotiation will also restart if the link is broken at any time. A broken link is caused by signal loss. This may occur because of a cable break, or because of an interruption in the signal transmitted by the link partner. Auto-negotiation resumes in an attempt to determine the new link configuration. If the management entity re-starts auto-negotiation by setting the Restart Auto-Negotiate bit of the Basic Control Register, the LAN8720A/LAN8720Ai will respond by stopping all transmission/receiving operations. Once the break_link_timer is completed in the Auto-negotiation state-machine (approximately 1200ms), auto-negotiation will re-start. In this case, the link partner will have also dropped the link due to lack of a received signal, so it too will resume auto-negotiation Disabling Auto-negotiation Auto-negotiation can be disabled by setting the Auto-Negotiation Enable bit of the Basic Control Register to zero. The device will then force its speed of operation to reflect the information in the Basic Control Register (Speed Select bit and Duplex Mode bit). These bits should be ignored when autonegotiation is enabled Half vs. Full Duplex Half duplex operation relies on the CSMA/CD (Carrier Sense Multiple Access / Collision Detect) protocol to handle network traffic and collisions. In this mode, the carrier sense signal, CRS, responds to both transmit and receive activity. If data is received while the transceiver is transmitting, a collision results. In full duplex mode, the transceiver is able to transmit and receive data simultaneously. In this mode, CRS responds only to receive activity. The CSMA/CD protocol does not apply and collision detection is disabled. SMSC LAN8720A/LAN8720Ai 25 Revision 1.4 ( )

26 3.3 HP Auto-MDIX Support HP Auto-MDIX facilitates the use of CAT-3 (10BASE-T) or CAT-5 (100BASE-T) media UTP interconnect cable without consideration of interface wiring scheme. If a user plugs in either a direct connect LAN cable, or a cross-over patch cable, as shown in Figure 3.4, the device s Auto-MDIX transceiver is capable of configuring the TXP/TXN and RXP/RXN pins for correct transceiver operation. The internal logic of the device detects the TX and RX pins of the connecting device. Since the RX and TX line pairs are interchangeable, special PCB design considerations are needed to accommodate the symmetrical magnetics and termination of an Auto-MDIX design. The Auto-MDIX function can be disabled via the AMDIXCTRL bit in the Special Control/Status Indications Register. RJ-45 8-pin straight-through for 10BASE-T/100BASE-TX signaling RJ-45 8-pin cross-over for 10BASE-T/100BASE-TX signaling TXP 1 1 TXP TXP 1 1 TXP TXN 2 2 TXN TXN 2 2 TXN RXP 3 3 RXP RXP 3 3 RXP Not Used 4 4 Not Used Not Used 4 4 Not Used Not Used 5 5 Not Used Not Used 5 5 Not Used RXN 6 6 RXN RXN 6 6 RXN Not Used 7 7 Not Used Not Used 7 7 Not Used Not Used 8 8 Not Used Not Used 8 8 Not Used Direct Connect Cable Cross-Over Cable Figure 3.4 Direct Cable Connection vs. Cross-over Cable Connection Revision 1.4 ( ) 26 SMSC LAN8720A/LAN8720Ai

27 3.4 MAC Interface RMII The device supports the low pin count Reduced Media Independent Interface (RMII) intended for use between Ethernet transceivers and switch ASICs. Under IEEE 802.3, an MII comprised of 16 pins for data and control is defined. In devices incorporating many MACs or transceiver interfaces such as switches, the number of pins can add significant cost as the port counts increase. RMII reduces this pin count while retaining a management interface (MDIO/MDC) that is identical to MII. The RMII interface has the following characteristics: It is capable of supporting 10Mbps and 100Mbps data rates A single clock reference is used for both transmit and receive It provides independent 2-bit (di-bit) wide transmit and receive data paths It uses LVCMOS signal levels, compatible with common digital CMOS ASIC processes The RMII includes the following interface signals (1 optional): transmit data - TXD[1:0] transmit strobe - TXEN receive data - RXD[1:0] receive error - RXER (Optional) carrier sense - CRS_DV Reference Clock - (RMII references usually define this signal as REF_CLK) CRS_DV - Carrier Sense/Receive Data Valid The CRS_DV is asserted by the device when the receive medium is non-idle. CRS_DV is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode. In 10BASE- T mode when squelch is passed, or in 100BASE-X mode when 2 non-contiguous zeroes in 10 bits are detected, the carrier is said to be detected. Loss of carrier shall result in the deassertion of CRS_DV synchronous to the cycle of REF_CLK which presents the first di-bit of a nibble onto RXD[1:0] (i.e. CRS_DV is deasserted only on nibble boundaries). If the device has additional bits to be presented on RXD[1:0] following the initial deassertion of CRS_DV, then the device shall assert CRS_DV on cycles of REF_CLK which present the second di-bit of each nibble and de-assert CRS_DV on cycles of REF_CLK which present the first di-bit of a nibble. The result is, starting on nibble boundaries, CRS_DV toggles at 25 MHz in 100Mbps mode and 2.5 MHz in 10Mbps mode when CRS ends before RXDV (i.e. the FIFO still has bits to transfer when the carrier event ends). Therefore, the MAC can accurately recover RXDV and CRS. During a false carrier event, CRS_DV shall remain asserted for the duration of carrier activity. The data on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchronous relative to REF_CLK, the data on RXD[1:0] shall be 00 until proper receive signal decoding takes place Reference Clock (REF_CLK) The RMII REF_CLK is a continuous clock that provides the timing reference for CRS_DV, RXD[1:0], TXEN, TXD[1:0] and RXER. The device uses REF_CLK as the network clock such that no buffering is required on the transmit data path. However, on the receive data path, the receiver recovers the clock from the incoming data stream, and the device uses elasticity buffering to accommodate for differences between the recovered clock and the local REF_CLK. SMSC LAN8720A/LAN8720Ai 27 Revision 1.4 ( )

28 3.5 Serial Management Interface (SMI) The Serial Management Interface is used to control the device and obtain its status. This interface supports registers 0 through 6 as required by Clause 22 of the standard, as well as vendorspecific registers 16 to 31 allowed by the specification. Non-supported registers (such as 7 to 15) will be read as hexadecimal FFFF. Device registers are detailed in Chapter 4, "Register Descriptions," on page 47. At the system level, SMI provides 2 signals: MDIO and MDC. The MDC signal is an aperiodic clock provided by the station management controller (SMC). MDIO is a bi-directional data SMI input/output signal that receives serial data (commands) from the controller SMC and sends serial data (status) to the SMC. The minimum time between edges of the MDC is 160 ns. There is no maximum time between edges. The minimum cycle time (time between two consecutive rising or two consecutive falling edges) is 400 ns. These modest timing requirements allow this interface to be easily driven by the I/O port of a microcontroller. The data on the MDIO line is latched on the rising edge of the MDC. The frame structure and timing of the data is shown in Figure 3.5 and Figure 3.6. The timing relationships of the MDIO signals are further described in Section 5.5.5, "SMI Timing," on page 73. Read Cycle MDC MDIO 's A4 A3 A2 A1 A0 R4 R3 R2 R1 R0 D15 D14... D1 D0 Preamble Start of Frame OP Code PHY Address Register Address Turn Around Data Data To Phy Data From Phy Figure 3.5 MDIO Timing and Frame Structure - READ Cycle Write Cycle MDC... MDIO 32 1's A4 A3 A2 A1 A0 R4 R3 R2 R1 R0... D15 D14 D1 D0 Preamble Start of Frame OP Code PHY Address Register Address Turn Around Data Data To Phy Figure 3.6 MDIO Timing and Frame Structure - WRITE Cycle Revision 1.4 ( ) 28 SMSC LAN8720A/LAN8720Ai

29 3.6 Interrupt Management The device management interface supports an interrupt capability that is not a part of the IEEE specification. This interrupt capability generates an active low asynchronous interrupt signal on the nint output whenever certain events are detected as setup by the Interrupt Mask Register. The device s interrupt system provides two modes, a Primary Interrupt mode and an Alternative interrupt mode. Both systems will assert the nint pin low when the corresponding mask bit is set. These modes differ only in how they de-assert the nint interrupt output. These modes are detailed in the following subsections. The Primary interrupt mode is the default interrupt mode after a power-up or hard reset. The Alternative interrupt mode requires setup after a power-up or hard reset Primary Interrupt System The Primary interrupt system is the default interrupt mode (ALTINT bit of the Mode Control/Status Register is 0 ). The Primary interrupt system is always selected after power-up or hard reset. In this mode, to set an interrupt, set the corresponding mask bit in the Interrupt Mask Register (see Table 3.2). Then when the event to assert nint is true, the nint output will be asserted. When the corresponding event to deassert nint is true, then the nint will be de-asserted. Table 3.2 Interrupt Management Table MASK INTERRUPT SOURCE FLAG INTERRUPT SOURCE EVENT TO ASSERT nint EVENT TO DE-ASSERT nint ENERGYON 17.1 ENERGYON Rising 17.1 (Note 3.1) Falling 17.1 or Reading register Auto-Negotiation complete 1.5 Auto-Negotiate Complete Rising 1.5 Falling 1.5 or Reading register Remote Fault Detected 1.4 Remote Fault Rising 1.4 Falling 1.4, or Reading register 1 or Reading register Link Down 1.2 Link Status Falling 1.2 Reading register 1 or Reading register Auto-Negotiation LP Acknowledge 5.14 Acknowledge Rising 5.14 Falling 5.14 or Read register Parallel Detection Fault 6.4 Parallel Detection Fault Rising 6.4 Falling 6.4 or Reading register 6, or Reading register 29 or Re-Auto Negotiate or Link down Auto-Negotiation Page Received 6.1 Page Received Rising 6.1 Falling of 6.1 or Reading register 6, or Reading register 29 Re-Auto Negotiate, or Link Down. Note 3.1 If the mask bit is enabled and nint has been de-asserted while ENERGYON is still high, nint will assert for 256 ms, approximately one second after ENERGYON goes low when the Cable is unplugged. To prevent an unexpected assertion of nint, the ENERGYON interrupt mask should always be cleared as part of the ENERGYON interrupt service routine. SMSC LAN8720A/LAN8720Ai 29 Revision 1.4 ( )

30 The ENERGYON bit in the Mode Control/Status Register is defaulted to a 1 at the start of the signal acquisition process, therefore the INT7 bit in the Interrupt Mask Register will also read as a 1 at power-up. If no signal is present, then both ENERGYON and INT7 will clear within a few milliseconds Alternate Interrupt System The Alternate interrupt system is enabled by setting the ALTINT bit of the Mode Control/Status Register to 1. In this mode, to set an interrupt, set the corresponding bit of the in the Mask Register 30, (see Table 3.3). To Clear an interrupt, either clear the corresponding bit in the Interrupt Mask Register to deassert the nint output, or clear the interrupt source, and write a 1 to the corresponding Interrupt Source Flag. Writing a 1 to the Interrupt Source Flag will cause the state machine to check the Interrupt Source to determine if the Interrupt Source Flag should clear or stay as a 1. If the Condition to deassert is true, then the Interrupt Source Flag is cleared and nint is also deasserted. If the Condition to deassert is false, then the Interrupt Source Flag remains set, and the nint remains asserted. For example, setting the INT7 bit in the Interrupt Mask Register will enable the ENERGYON interrupt. After a cable is plugged in, the ENERGYON bit in the Mode Control/Status Register goes active and nint will be asserted low. To de-assert the nint interrupt output, either clear the ENERGYON bit in the Mode Control/Status Register by removing the cable and then writing a 1 to the INT7 bit in the Interrupt Mask Register, OR clear the INT7 mask (bit 7 of the Interrupt Mask Register). Table 3.3 Alternative Interrupt System Management Table MASK INTERRUPT SOURCE FLAG INTERRUPT SOURCE EVENT TO ASSERT nint CONDITION TO DE-ASSERT BIT TO CLEAR nint ENERGYON 17.1 ENERGYON Rising low Auto-Negotiation complete 1.5 Auto-Negotiate Complete Rising low Remote Fault Detected 1.4 Remote Fault Rising low Link Down 1.2 Link Status Falling high Auto-Negotiation LP Acknowledge 5.14 Acknowledge Rising low Parallel Detection Fault 6.4 Parallel Detection Fault Rising low Auto-Negotiation Page Received 6.1 Page Received Rising low 29.1 The ENERGYON bit in the Mode Control/Status Register is defaulted to a 1 at the start of the signal acquisition process, therefore the INT7 bit in the Interrupt Mask Register will also read as a 1 at power-up. If no signal is present, then both ENERGYON and INT7 will clear within a few milliseconds. Revision 1.4 ( ) 30 SMSC LAN8720A/LAN8720Ai

31 3.7 Configuration Straps Configuration straps allow various features of the device to be automatically configured to user defined values. Configuration straps are latched upon Power-On Reset (POR) and pin reset (nrst). Configuration straps include internal resistors in order to prevent the signal from floating when unconnected. If a particular configuration strap is connected to a load, an external pull-up or pull-down resistor should be used to augment the internal resistor to ensure that it reaches the required voltage level prior to latching. The internal resistor can also be overridden by the addition of an external resistor. The system designer must guarantee that configuration strap pins meet the timing requirements specified in Section 5.5.3, "Power-On nrst & Configuration Strap Timing," on page 70. If configuration strap pins are not at the correct voltage level prior to being latched, the device may capture incorrect strap values. When externally pulling configuration straps high, the strap should be tied to VDDIO, except for REGOFF and nintsel which should be tied to VDD2A PHYAD[0]: PHY Address Configuration The PHYAD0 bit is driven high or low to give each PHY a unique address. This address is latched into an internal register at the end of a hardware reset (default = ). In a multi-phy application (such as a repeater), the controller is able to manage each PHY via the unique address. Each PHY checks each management data frame for a matching address in the relevant bits. When a match is recognized, the PHY responds to that particular frame. The PHY address is also used to seed the scrambler. In a multi-phy application, this ensures that the scramblers are out of synchronization and disperses the electromagnetic radiation across the frequency spectrum. The device s SMI address may be configured using hardware configuration to either the value 0 or 1. The user can configure the PHY address using Software Configuration if an address greater than 1 is required. The PHY address can be written (after SMI communication at some address is established) using the PHYAD bits of the Special Modes Register. The PHYAD0 hardware configuration strap is multiplexed with the RXER pin MODE[2:0]: Mode Configuration The MODE[2:0] configuration straps control the configuration of the 10/100 digital block. When the nrst pin is deasserted, the register bit values are loaded according to the MODE[2:0] configuration straps. The 10/100 digital block is then configured by the register bit values. When a soft reset occurs via the Soft Reset bit of the Basic Control Register, the configuration of the 10/100 digital block is controlled by the register bit values and the MODE[2:0] configuration straps have no affect. The device s mode may be configured using the hardware configuration straps as summarized in Table 3.4. The user may configure the transceiver mode by writing the SMI registers. SMSC LAN8720A/LAN8720Ai 31 Revision 1.4 ( )

32 Table 3.4 MODE[2:0] Bus MODE[2:0] MODE DEFINITIONS DEFAULT REGISTER BIT VALUES REGISTER 0 REGISTER 4 [13,12,10,8] [8,7,6,5] Base-T Half Duplex. Auto-negotiation disabled N/A Base-T Full Duplex. Auto-negotiation disabled N/A Base-TX Half Duplex. Auto-negotiation disabled. CRS is active during Transmit & Receive Base-TX Full Duplex. Auto-negotiation disabled. CRS is active during Receive Base-TX Half Duplex is advertised. Autonegotiation enabled. CRS is active during Transmit & Receive. 101 Repeater mode. Auto-negotiation enabled. 100Base-TX Half Duplex is advertised. CRS is active during Receive N/A 1001 N/A Power Down mode. In this mode the transceiver will wake-up in Power-Down mode. The transceiver cannot be used when the MODE[2:0] bits are set to this mode. To exit this mode, the MODE bits in Register 18.7:5(see Section 4.2.9, "Special Modes Register," on page 57) must be configured to some other value and a soft reset must be issued. N/A N/A 111 All capable. Auto-negotiation enabled. X10X 1111 The MODE[2:0] hardware configuration pins are multiplexed with other signals as shown in Table 3.5. Table 3.5 Pin Names for Mode Bits MODE BIT MODE[0] MODE[1] MODE[2] PIN NAME RXD0/MODE0 RXD1/MODE1 CRS_DV/MODE REGOFF: Internal +1.2V Regulator Configuration The incorporation of flexpwr technology provides the ability to disable the internal +1.2V regulator. When the regulator is disabled, an external +1.2V must be supplied to the VDDCR pin. Disabling the internal +1.2V regulator makes it possible to reduce total system power, since an external switching regulator with greater efficiency (versus the internal linear regulator) can be used to provide +1.2V to the transceiver circuitry. Because the REGOFF configuration strap shares functionality with the LED1 pin, proper consideration must also be given to the LED polarity. Refer to Section , "REGOFF and LED1 Polarity Selection," on page 37 for additional information on the relation between REGOFF and the LED1 polarity. Revision 1.4 ( ) 32 SMSC LAN8720A/LAN8720Ai

33 Disabling the Internal +1.2V Regulator To disable the +1.2V internal regulator, a pull-up strapping resistor should be connected from the REGOFF configuration strap to VDD2A. At power-on, after both VDDIO and VDD2A are within specification, the transceiver will sample REGOFF to determine whether the internal regulator should turn on. If the pin is sampled at a voltage greater than V IH, then the internal regulator is disabled and the system must supply +1.2V to the VDDCR pin. The VDDIO voltage must be at least 80% of the operating voltage level (1.44V when operating at 1.8V, 2.0V when operating at 2.5V, 2.64V when operating at 3.3V) before voltage is applied to VDDCR. As described in Section , when REGOFF is left floating or connected to VSS, the internal regulator is enabled and the system is not required to supply +1.2V to the VDDCR pin Enabling the Internal +1.2V Regulator The +1.2V for VDDCR is supplied by the on-chip regulator unless the transceiver is configured for the regulator off mode using the REGOFF configuration strap as described in Section By default, the internal +1.2V regulator is enabled when REGOFF is floating (due to the internal pull-down resistor). During power-on, if REGOFF is sampled below V IL, then the internal +1.2V regulator will turn on and operate with power from the VDD2A pin nintsel: nint/refclko Configuration The nintsel configuration strap is used to select between one of two available modes: REF_CLK In Mode (nint) and REF_CLK Out Mode. The configured mode determines the function of the nint/refclko pin. The nintsel configuration strap is latched at POR and on the rising edge of the nrst. By default, nintsel is configured for nint mode via the internal pull-up resistor. Table 3.6 nintsel Configuration STRAP VALUE MODE REF_CLK DESCRIPTION nintsel = 0 REF_CLK Out Mode nint/refclko is the source of REF_CLK. nintsel = 1 REF_CLK In Mode nint/refclko is an active low interrupt output. The REF_CLK is sourced externally and must be driven on the XTAL1/CLKIN pin. The RMII REF_CLK is a continuous clock that provides the timing reference for CRS_DV, RXD[1:0], TXEN, TXD[1:0] and RXER. The device uses REF_CLK as the network clock such that no buffering is required on the transmit data path. However, on the receive data path, the receiver recovers the clock from the incoming data stream. The device uses elasticity buffering to accommodate for differences between the recovered clock and the local REF_CLK. In REF_CLK In Mode, the 50MHz REF_CLK is driven on the XTAL1/CLKIN pin. This is the traditional system configuration when using RMII, and is described in Section When configured for REF_CLK Out Mode, the device generates the 50MHz RMII REF_CLK and the nint interrupt is not available. REF_CLK Out Mode allows a low-cost 25MHz crystal to be used as the reference for REF_CLK. This configuration may result in reduced system cost and is described in Section Because the nintsel configuration strap shares functionality with the LED2 pin, proper consideration must also be given to the LED polarity. Refer to Section , "nintsel and LED2 Polarity Selection," on page 37 for additional information on the relation between nintsel and the LED2 polarity. SMSC LAN8720A/LAN8720Ai 33 Revision 1.4 ( )

34 REF_CLK In Mode In REF_CLK In Mode, the 50MHz REF_CLK is driven on the XTAL1/CLKIN pin. A 50MHz source for REF_CLK must be available external to the device when using this mode. The clock is driven to both the MAC and PHY as shown in Figure 3.7. MAC Accepts external 50MHz clock RMII 2 LAN8720A/LAN8720Ai 10/100 PHY 24-QFN MDIO RMII MDC nint TXD[1:0] TXEN TXP TXN Mag RJ45 RXD[1:0] RXP 2 CRS_DV RXN REF_CLK RXER LED[2:1] XTAL1/CLKIN All RMII signals are synchronous to the supplied clock 2 nrst XTAL2 Interface 50MHz Reference Clock REF_CLK Out Mode Figure 3.7 External 50MHz clock sources the REF_CLK To reduce BOM cost, the device includes a feature to generate the RMII REF_CLK signal from a lowcost, 25MHz fundamental crystal. This type of crystal is inexpensive in comparison to 3 rd overtone crystals that would normally be required for 50MHz. The MAC must be capable of operating with an external clock to take advantage of this feature as shown in Figure 3.8. In order to optimize package size and cost, the REFCLKO pin is multiplexed with the nint pin. In REF_CLK Out mode, the nint functionality is disabled to accommodate usage of REFCLKO as a 50MHz clock to the MAC. The REF_CLK Out Mode is not part of the RMII Specification. Timing in this mode is not compliant with the RMII specification. To ensure proper system operation, a timing analysis of the MAC and LAN8720 must be performed. Revision 1.4 ( ) 34 SMSC LAN8720A/LAN8720Ai

35 MAC Capable of accepting 50MHz clock REF_CLK RMII 2 2 MDIO MDC TXD[1:0] TXEN RXD[1:0] CRS_DV RXER LAN8720A/LAN8720Ai 10/100 PHY 24-QFN RMII TXP TXN RXP RXN nint not available in this configuration Mag RJ45 REFCLKO LED[2:1] XTAL1/CLKIN 2 25MHz nrst XTAL2 Interface Figure 3.8 Sourcing REF_CLK from a 25MHz Crystal In some system architectures, a 25MHz clock source is available. The device can be used to generate the REF_CLK to the MAC as shown in Figure 3.9. It is important to note that in this specific example, only a 25MHz clock can be used (clock cannot be 50MHz). Similar to the 25MHz crystal mode, the nint function is disabled. SMSC LAN8720A/LAN8720Ai 35 Revision 1.4 ( )

36 nint is not available in this configuration MAC Capable of accepting 50MHz clock REF_CLK RMII 2 2 LAN8720A/LAN8720Ai 10/100 PHY 24-QFN MDIO RMII MDC TXD[1:0] TXEN RXD[1:0] CRS_DV RXER TXP TXN RXP RXN Mag RJ45 REFCLKO LED[2:1] XTAL1/CLKIN 25MHz Clock 2 nrst XTAL2 Interface Figure 3.9 Sourcing REF_CLK from External 25MHz Source Revision 1.4 ( ) 36 SMSC LAN8720A/LAN8720Ai

37 3.8 Miscellaneous Functions LEDs Two LED signals are provided as a convenient means to determine the transceiver's mode of operation. All LED signals are either active high or active low as described in Section , "nintsel and LED2 Polarity Selection" and Section , "REGOFF and LED1 Polarity Selection," on page 37. The LED1 output is driven active whenever the device detects a valid link, and blinks when CRS is active (high) indicating activity. The LED2 output is driven active when the operating speed is 100Mbps. This LED will go inactive when the operating speed is 10Mbps or during line isolation. When pulling the LED1 and LED2 pins high, they must be tied to VDD2A, NOT VDDIO REGOFF and LED1 Polarity Selection The REGOFF configuration strap is shared with the LED1 pin. The LED1 output will automatically change polarity based on the presence of an external pull-up resistor. If the LED1 pin is pulled high to VDD2A by an external pull-up resistor to select a logical high for REGOFF, then the LED1 output will be active low. If the LED1 pin is pulled low by the internal pull-down resistor to select a logical low for REGOFF, the LED1 output will then be an active high output. Figure 3.10 details the LED1 polarity for each REGOFF configuration. REGOFF = 1 (Regulator OFF) LED output = Active Low VDD2A REGOFF = 0 (Regulator ON) LED output = Active High LED1/REGOFF 10K ~270 ohms ~270 ohms LED1/REGOFF Figure 3.10 LED1/REGOFF Polarity Configuration Refer to Section 3.7.3, "REGOFF: Internal +1.2V Regulator Configuration," on page 32 for additional information on the REGOFF configuration strap nintsel and LED2 Polarity Selection The nintsel configuration strap is shared with the LED2 pin. The LED2 output will automatically change polarity based on the presence of an external pull-down resistor. If the LED2 pin is pulled high to VDD2A to select a logical high for nintsel, then the LED2 output will be active low. If the LED2 SMSC LAN8720A/LAN8720Ai 37 Revision 1.4 ( )

38 pin is pulled low by an external pull-down resistor to select a logical low for nintsel, the LED2 output will then be an active high output. Figure 3.11 details the LED2 polarity for each nintsel configuration. nintsel = 1 LED output = Active Low VDD2A nintsel = 0 LED output = Active High LED2/nINTSEL 10K ~270 ohms ~270 ohms LED2/nINTSEL Figure 3.11 LED2/nINTSEL Polarity Configuration Refer to Section 3.7.4, "nintsel: nint/refclko Configuration," on page 33 for additional information on the nintsel configuration strap Variable Voltage I/O The device s digital I/O pins are variable voltage, allowing them to take advantage of low power savings from shrinking technologies. These pins can operate from a low I/O voltage of +1.62V up to +3.6V. The applied I/O voltage must maintain its value with a tolerance of ± 10%. Varying the voltage up or down after the transceiver has completed power-on reset can cause errors in the transceiver operation. Refer to Chapter 5, "Operational Characteristics," on page 63 for additional information. Input signals must not be driven high before power is applied to the device Power-Down Modes There are two device power-down modes: General Power-Down Mode and Energy Detect Power- Down Mode. These modes are described in the following subsections General Power-Down This power-down mode is controlled via the Power Down bit of the Basic Control Register. In this mode, the entire transceiver (except the management interface) is powered-down and remains in this mode as long as the Power Down bit is 1. When the Power Down bit is cleared, the transceiver powers up and is automatically reset Energy Detect Power-Down This power-down mode is activated by setting the EDPWRDOWN bit of the Mode Control/Status Register. In this mode, when no energy is present on the line the transceiver is powered down (except for the management interface, the SQUELCH circuit, and the ENERGYON logic). The ENERGYON logic is used to detect the presence of valid energy from 100BASE-TX, 10BASE-T, or Auto-negotiation signals. In this mode, when the ENERGYON bit of the Mode Control/Status Register is low, the transceiver is powered-down and nothing is transmitted. When energy is received via link pulses or packets, the ENERGYON bit goes high and the transceiver powers-up. The device automatically resets into the Revision 1.4 ( ) 38 SMSC LAN8720A/LAN8720Ai

39 state prior to power-down and asserts the nint interrupt if the ENERGYON interrupt is enabled in the Interrupt Mask Register. The first and possibly the second packet to activate ENERGYON may be lost. When the EDPWRDOWN bit of the Mode Control/Status Register is low, energy detect power-down is disabled Isolate Mode Resets The device data paths may be electrically isolated from the RMII interface by setting the Isolate bit of the Basic Control Register to 1. In isolation mode, the transceiver does not respond to the TXD, TXEN and TXER inputs, but does respond to management transactions. Isolation provides a means for multiple transceivers to be connected to the same RMII interface without contention. By default, the transceiver is not isolated (on power-up (Isolate=0). The device provides two forms of reset: Hardware and Software. The device registers are reset by both Hardware and Software resets. Select register bits, indicated as NASR in the register definitions, are not cleared by a Software reset. The registers are not reset by the power-down modes described in Section For the first 16us after coming out of reset, the RMII interface will run at 2.5 MHz. After this time, it will switch to 25 MHz if auto-negotiation is enabled Hardware Reset A Hardware reset is asserted by driving the nrst input pin low. When driven, nrst should be held low for the minimum time detailed in Section 5.5.3, "Power-On nrst & Configuration Strap Timing," on page 70 to ensure a proper transceiver reset. During a Hardware reset, an external clock must be supplied to the XTAL1/CLKIN signal. A hardware reset (nrst assertion) is required following power-up. Refer to Section 5.5.3, "Power-On nrst & Configuration Strap Timing," on page 70 for additional information Software Reset A Software reset is activated by setting the Soft Reset bit of the Basic Control Register to 1. All registers bits, except those indicated as NASR in the register definitions, are cleared by a Software reset. The Soft Reset bit is self-clearing. Per the IEEE 802.3u standard, clause 22 ( ) the reset process will be completed within 0.5s from the setting of this bit Carrier Sense The carrier sense (CRS) is output on the CRS_DV pin. CRS is a signal defined by the MII specification in the IEEE 802.3u standard. The device asserts CRS based only on receive activity whenever the transceiver is either in repeater mode or full-duplex mode. Otherwise the transceiver asserts CRS based on either transmit or receive activity. The carrier sense logic uses the encoded, unscrambled data to determine carrier activity status. It activates carrier sense with the detection of 2 non-contiguous zeros within any 10 bit span. Carrier sense terminates if a span of 10 consecutive ones is detected before a /J/K/ Start-of Stream Delimiter pair. If an SSD pair is detected, carrier sense is asserted until either /T/R/ End of-stream Delimiter pair or a pair of IDLE symbols is detected. Carrier is negated after the /T/ symbol or the first IDLE. If /T/ is not followed by /R/, then carrier is maintained. Carrier is treated similarly for IDLE followed by some non-idle symbol. SMSC LAN8720A/LAN8720Ai 39 Revision 1.4 ( )

40 3.8.7 Link Integrity Test The device performs the link integrity test as outlined in the IEEE 802.3u (Clause 24-15) Link Monitor state diagram. The link status is multiplexed with the 10Mbps link status to form the Link Status bit in the Basic Status Register and to drive the LINK LED (LED1). The DSP indicates a valid MLT-3 waveform present on the RXP and RXN signals as defined by the ANSI X3.263 TP-PMD standard, to the Link Monitor state-machine, using the internal DATA_VALID signal. When DATA_VALID is asserted, the control logic moves into a Link-Ready state and waits for an enable from the auto-negotiation block. When received, the Link-Up state is entered, and the Transmit and Receive logic blocks become active. Should auto-negotiation be disabled, the link integrity logic moves immediately to the Link-Up state when the DATA_VALID is asserted. To allow the line to stabilize, the link integrity logic will wait a minimum of 330 μsec from the time DATA_VALID is asserted until the Link-Ready state is entered. Should the DATA_VALID input be negated at any time, this logic will immediately negate the Link signal and enter the Link-Down state. When the 10/100 digital block is in 10BASE-T mode, the link status is derived from the 10BASE-T receiver logic Loopback Operation The device may be configured for near-end loopback and far loopback. These loopback modes are detailed in the following subsections Near-end Loopback Near-end loopback mode sends the digital transmit data back out the receive data signals for testing purposes, as indicated by the blue arrows in Figure The near-end loopback mode is enabled by setting the Loopback bit of the Basic Control Register to 1. A large percentage of the digital circuitry is operational in near-end loopback mode because data is routed through the PCS and PMA layers into the PMD sublayer before it is looped back. The transmitters are powered down regardless of the state of TXEN. 10/100 Ethernet MAC TXD RXD Digital Analog X X TX RX XFMR CAT-5 SMSC Ethernet Transceiver Figure 3.12 Near-end Loopback Block Diagram Far Loopback Far loopback is a special test mode for MDI (analog) loopback as indicated by the blue arrows in Figure The far loopback mode is enabled by setting the FARLOOPBACK bit of the Mode Control/Status Register to 1. In this mode, data that is received from the link partner on the MDI is looped back out to the link partner. The digital interface signals on the local MAC interface are isolated. Revision 1.4 ( ) 40 SMSC LAN8720A/LAN8720Ai

41 Far-end system 10/100 Ethernet MAC TXD RXD X X Digital Analog TX RX XFMR CAT-5 Link Partner SMSC Ethernet Transceiver Connector Loopback Figure 3.13 Far Loopback Block Diagram The device maintains reliable transmission over very short cables, and can be tested in a connector loopback as shown in Figure An RJ45 loopback cable can be used to route the transmit signals an the output of the transformer back to the receiver inputs, and this loopback will work at both 10 and /100 Ethernet MAC TXD RXD Digital Analog TX RX XFMR SMSC Ethernet Transceiver RJ45 Loopback Cable. Created by connecting pin 1 to pin 3 and connecting pin 2 to pin 6. Figure 3.14 Connector Loopback Block Diagram 3.9 Application Diagrams This section provides typical application diagrams for the following: Simplified System Level Application Diagram Power Supply Diagram (1.2V Supplied by Internal Regulator) Power Supply Diagram (1.2V Supplied by External Source) Twisted-Pair Interface Diagram (Single Power Supply) Twisted-Pair Interface Diagram (Dual Power Supplies) SMSC LAN8720A/LAN8720Ai 41 Revision 1.4 ( )

42 3.9.1 Simplified System Level Application Diagram RMII LAN8720A/LAN8720Ai 10/100 PHY 24-QFN MDIO RMII MDC nint TXP Mag RJ45 TXD[1:0] TXN 2 TXEN RXD[1:0] RXP RXN 2 RXER LED[2:1] XTAL1/CLKIN 2 25MHz nrst XTAL2 Interface Figure 3.15 Simplified System Level Application Diagram Revision 1.4 ( ) 42 SMSC LAN8720A/LAN8720Ai

43 3.9.2 Power Supply Diagram (1.2V Supplied by Internal Regulator) LAN8720A/LAN8720Ai 24-QFN Core Logic Ch.2 3.3V Circuitry Power Supply 3.3V 1 uf 470 pf VDDCR OUT Internal Regulator IN VDD2A C BYPASS VDDDIO Supply V C F C BYPASS VDDIO Ch.1 3.3V Circuitry VDD1A C BYPASS RBIAS LED1/ REGOFF VSS 12.1k ~270 Ohm Figure 3.16 Power Supply Diagram (1.2V Supplied by Internal Regulator) SMSC LAN8720A/LAN8720Ai 43 Revision 1.4 ( )

44 3.9.3 Power Supply Diagram (1.2V Supplied by External Source) LAN8720A/LAN8720Ai 24-QFN Core Logic Ch.2 3.3V Circuitry Power Supply 3.3V VDDCR Supply 1.2V 1 uf 470 pf VDDCR OUT Internal Regulator (Disabled) IN VDD2A C BYPASS VDDDIO Supply V C F C BYPASS VDDIO Ch.1 3.3V Circuitry VDD1A C BYPASS RBIAS LED1/ REGOFF VSS 12.1k ~270 Ohm 10k Figure 3.17 Power Supply Diagram (1.2V Supplied by External Source) Revision 1.4 ( ) 44 SMSC LAN8720A/LAN8720Ai

45 3.9.4 Twisted-Pair Interface Diagram (Single Power Supply) LAN8720A/LAN8720Ai 24-QFN Power Supply 3.3V Ferrite bead 49.9 Ohm Resistors VDD2A C BYPASS VDD1A C BYPASS Magnetics TXP TXN RXP RJ RXN 1000 pf 3 kv C BYPASS Figure 3.18 Twisted-Pair Interface Diagram (Single Power Supply) SMSC LAN8720A/LAN8720Ai 45 Revision 1.4 ( )

46 3.9.5 Twisted-Pair Interface Diagram (Dual Power Supplies) LAN8720A/LAN8720Ai 24-QFN Power Supply 3.3V 49.9 Ohm Resistors Power Supply 2.5V - 3.3V VDD2A C BYPASS VDD1A C BYPASS Magnetics TXP TXN RXP RJ RXN 1000 pf 3 kv C BYPASS Figure 3.19 Twisted-Pair Interface Diagram (Dual Power Supplies) Revision 1.4 ( ) 46 SMSC LAN8720A/LAN8720Ai

47 Chapter 4 Register Descriptions Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support This chapter describes the various control and status registers (CSR s). All registers follow the IEEE (clause ) management register set. All functionality and bit definitions comply with these standards. The IEEE specified register index (in decimal) is included with each register definition, allowing for addressing of these registers via the Serial Management Interface (SMI) protocol. 4.1 Register Nomenclature Table 4.1 describes the register bit attribute notation used throughout this document. Table 4.1 Register Bit Types REGISTER BIT TYPE NOTATION R W RO WO WC WAC RC LL LH SC SS RO/LH NASR RESERVED REGISTER BIT DESCRIPTION Read: A register or bit with this attribute can be read. Read: A register or bit with this attribute can be written. Read only: Read only. Writes have no effect. Write only: If a register or bit is write-only, reads will return unspecified data. Write One to Clear: writing a one clears the value. Writing a zero has no effect Write Anything to Clear: writing anything clears the value. Read to Clear: Contents is cleared after the read. Writes have no effect. Latch Low: Clear on read of register. Latch High: Clear on read of register. Self-Clearing: Contents are self-cleared after the being set. Writes of zero have no effect. Contents can be read. Self-Setting: Contents are self-setting after being cleared. Writes of one have no effect. Contents can be read. Read Only, Latch High: Bits with this attribute will stay high until the bit is read. After it is read, the bit will either remain high if the high condition remains, or will go low if the high condition has been removed. If the bit has not been read, the bit will remain high regardless of a change to the high condition. This mode is used in some Ethernet PHY registers. Not Affected by Software Reset. The state of NASR bits do not change on assertion of a software reset. Reserved Field: Reserved fields must be written with zeros to ensure future compatibility. The value of reserved bits is not guaranteed on a read. Many of these register bit notations can be combined. Some examples of this are shown below: R/W: Can be written. Will return current setting on a read. R/WAC: Will return current setting on a read. Writing anything clears the bit. SMSC LAN8720A/LAN8720Ai 47 Revision 1.4 ( )

48 4.2 Control and Status Registers Table 4.2 provides a list of supported registers. Register details, including bit definitions, are provided in the proceeding subsections. Table 4.2 SMI Register Map REGISTER INDEX (DECIMAL) REGISTER NAME GROUP 0 Basic Control Register Basic 1 Basic Status Register Basic 2 PHY Identifier 1 Extended 3 PHY Identifier 2 Extended 4 Auto-Negotiation Advertisement Register Extended 5 Auto-Negotiation Link Partner Ability Register Extended 6 Auto-Negotiation Expansion Register Extended 17 Mode Control/Status Register Vendor-specific 18 Special Modes Vendor-specific 26 Symbol Error Counter Register Vendor-specific 27 Control / Status Indication Register Vendor-specific 29 Interrupt Source Register Vendor-specific 30 Interrupt Mask Register Vendor-specific 31 PHY Special Control/Status Register Vendor-specific Revision 1.4 ( ) 48 SMSC LAN8720A/LAN8720Ai

49 4.2.1 Basic Control Register Index (In Decimal): 0 Size: 16 bits BITS DESCRIPTION TYPE DEFAULT 15 Soft Reset 1 = software reset. Bit is self-clearing. When setting this bit do not set other bits in this register. The configuration (as described in Section 3.7.2, "MODE[2:0]: Mode Configuration," on page 31) is set from the register bit values, and not from the mode pins. 14 Loopback 0 = normal operation 1 = loopback mode R/W SC R/W 13 Speed Select 0 = 10Mbps 1 = 100Mbps Ignored if Auto-negotiation is enabled (0.12 = 1). 12 Auto-Negotiation Enable 0 = disable auto-negotiate process 1 = enable auto-negotiate process (overrides 0.13 and 0.8) R/W Note 4.1 R/W Note Power Down 0 = normal operation 1 = General power down mode The Auto-Negotiation Enable must be cleared before setting the Power Down. 10 Isolate 0 = normal operation 1 = electrical isolation of PHY from the RMII 9 Restart Auto-Negotiate 0 = normal operation 1 = restart auto-negotiate process Bit is self-clearing. R/W R/W R/W SC 8 Duplex Mode 0 = half duplex 1 = full duplex Ignored if Auto-Negotiation is enabled (0.12 = 1). R/W Note 4.1 7:0 RESERVED RO - Note 4.1 The default value of this bit is determined by the MODE[2:0] configuration straps. Refer to Section 3.7.2, "MODE[2:0]: Mode Configuration," on page 31 for additional information. SMSC LAN8720A/LAN8720Ai 49 Revision 1.4 ( )

50 4.2.2 Basic Status Register Index (In Decimal): 1 Size: 16 bits BITS DESCRIPTION TYPE DEFAULT BASE-T4 0 = no T4 ability 1 = T4 able BASE-TX Full Duplex 0 = no TX full duplex ability 1 = TX with full duplex BASE-TX Half Duplex 0 = no TX half duplex ability 1 = TX with half duplex 12 10BASE-T Full Duplex 0 = no 10Mbps with full duplex ability 1 = 10Mbps with full duplex 11 10BASE-T Half Duplex 0 = no 10Mbps with half duplex ability 1 = 10Mbps with half duplex BASE-T2 Full Duplex 0 = PHY not able to perform full duplex 100BASE-T2 1 = PHY able to perform full duplex 100BASE-T BASE-T2 Half Duplex 0 = PHY not able to perform half duplex 100BASE-T2 1 = PHY able to perform half duplex 100BASE-T2 8 Extended Status 0 = no extended status information in register 15 1 = extended status information in register 15 RO RO RO RO RO RO RO RO 1b 1b 1b 1b 7:6 RESERVED RO - 5 Auto-Negotiate Complete 0 = auto-negotiate process not completed 1 = auto-negotiate process completed 4 Remote Fault 1 = remote fault condition detected 0 = no remote fault 3 Auto-Negotiate Ability 0 = unable to perform auto-negotiation function 1 = able to perform auto-negotiation function 2 Link Status 0 = link is down 1 = link is up 1 Jabber Detect 0 = no jabber condition detected 1 = jabber condition detected 0 Extended Capabilities 0 = does not support extended capabilities registers 1 = supports extended capabilities registers RO RO/LH RO RO/LL RO/LH RO 1b 1b Revision 1.4 ( ) 50 SMSC LAN8720A/LAN8720Ai

51 4.2.3 PHY Identifier 1 Register Index (In Decimal): 2 Size: 16 bits BITS DESCRIPTION TYPE DEFAULT 15:0 PHY ID Number Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier (OUI), respectively. R/W 0007h SMSC LAN8720A/LAN8720Ai 51 Revision 1.4 ( )

52 4.2.4 PHY Identifier 2 Register Index (In Decimal): 3 Size: 16 bits BITS DESCRIPTION TYPE DEFAULT 15:10 PHY ID Number Assigned to the 19th through 24th bits of the OUI. 9:4 Model Number Six-bit manufacturer s model number. R/W R/W b 3:0 Revision Number Four-bit manufacturer s revision number. R/W Note 4.2 Note 4.2 The default value of this field will vary dependant on the silicon revision number. Revision 1.4 ( ) 52 SMSC LAN8720A/LAN8720Ai

53 4.2.5 Auto Negotiation Advertisement Register Index (In Decimal): 4 Size: 16 bits BITS DESCRIPTION TYPE DEFAULT 15:14 RESERVED RO - 13 Remote Fault 0 = no remote fault 1 = remote fault detected R/W 12 RESERVED RO - 11:10 Pause Operation 00 = No PAUSE 01 = Symmetric PAUSE 10 = Asymmetric PAUSE toward link partner 11 = Advertise support for both Symmetric PAUSE and Asymmetric PAUSE toward local device When both Symmetric PAUSE and Asymmetric PAUSE are set, the device will only be configured to, at most, one of the two settings upon auto-negotiation completion. R/W 0 9 RESERVED RO BASE-TX Full Duplex 0 = no TX full duplex ability 1 = TX with full duplex R/W Note BASE-TX 0 = no TX ability 1 = TX able R/W 1b 6 10BASE-T Full Duplex 0 = no 10Mbps with full duplex ability 1 = 10Mbps with full duplex 5 10BASE-T 0 = no 10Mbps ability 1 = 10Mbps able R/W Note 4.3 R/W Note 4.3 4:0 Selector Field = IEEE R/W 00001b Note 4.3 The default value of this bit is determined by the MODE[2:0] configuration straps. Refer to Section 3.7.2, "MODE[2:0]: Mode Configuration," on page 31 for additional information. SMSC LAN8720A/LAN8720Ai 53 Revision 1.4 ( )

54 4.2.6 Auto Negotiation Link Partner Ability Register Index (In Decimal): 5 Size: 16 bits BITS DESCRIPTION TYPE DEFAULT 15 Next Page 0 = no next page ability 1 = next page capable This device does not support next page ability. 14 Acknowledge 0 = link code word not yet received 1 = link code word received from partner 13 Remote Fault 0 = no remote fault 1 = remote fault detected RO RO RO 12:11 RESERVED RO - 10 Pause Operation 0 = No PAUSE supported by partner station 1 = PAUSE supported by partner station 9 100BASE-T4 0 = no T4 ability 1 = T4 able This device does not support T4 ability BASE-TX Full Duplex 0 = no TX full duplex ability 1 = TX with full duplex 7 100BASE-TX 0 = no TX ability 1 = TX able 6 10BASE-T Full Duplex 0 = no 10Mbps with full duplex ability 1 = 10Mbps with full duplex 5 10BASE-T 0 = no 10Mbps ability 1 = 10Mbps able 4:0 Selector Field = IEEE RO RO RO RO RO RO RO 00001b Revision 1.4 ( ) 54 SMSC LAN8720A/LAN8720Ai

55 4.2.7 Auto Negotiation Expansion Register Index (In Decimal): 6 Size: 16 bits BITS DESCRIPTION TYPE DEFAULT 15:5 RESERVED RO - 4 Parallel Detection Fault 0 = no fault detected by parallel detection logic 1 = fault detected by parallel detection logic 3 Link Partner Next Page Able 0 = link partner does not have next page ability 1 = link partner has next page ability 2 Next Page Able 0 = local device does not have next page ability 1 = local device has next page ability 1 Page Received 0 = new page not yet received 1 = new page received 0 Link Partner Auto-Negotiation Able 0 = link partner does not have auto-negotiation ability 1 = link partner has auto-negotiation ability RO/LH RO RO RO/LH RO SMSC LAN8720A/LAN8720Ai 55 Revision 1.4 ( )

56 4.2.8 Mode Control/Status Register Index (In Decimal): 17 Size: 16 bits BITS DESCRIPTION TYPE DEFAULT 15:14 RESERVED RO - 13 EDPWRDOWN Enable the Energy Detect Power-Down mode: 0 = Energy Detect Power-Down is disabled 1 = Energy Detect Power-Down is enabled R/W 12:10 RESERVED RO - 9 FARLOOPBACK Enables far loopback mode (i.e., all the received packets are sent back simultaneously (in 100BASE-TX only)). This mode works even if the Isolate bit (0.10) is set. 0 = Far loopback mode is disabled 1 = Far loopback mode is enabled Refer to Section , "Far Loopback," on page 40 for additional information. R/W 8:7 RESERVED RO - 6 ALTINT Alternate Interrupt Mode: 0 = Primary interrupt system enabled (Default) 1 = Alternate interrupt system enabled Refer to Section 3.6, "Interrupt Management," on page 29 for additional information. R/W 5:2 RESERVED RO - 1 ENERGYON Indicates whether energy is detected. This bit transitions to 0 if no valid energy is detected within 256ms. It is reset to 1 by a hardware reset and is unaffected by a software reset. Refer to Section , "Energy Detect Power-Down," on page 38 for additional information. RO 1b 0 RESERVED R/W Revision 1.4 ( ) 56 SMSC LAN8720A/LAN8720Ai

57 4.2.9 Special Modes Register Index (In Decimal): 18 Size: 16 bits BITS DESCRIPTION TYPE DEFAULT 15 RESERVED RO - 14 RESERVED Write as 1, ignore on read. R/W NASR 1b 13:8 RESERVED RO - 7:5 MODE Transceiver mode of operation. Refer to Section 3.7.2, "MODE[2:0]: Mode Configuration," on page 31 for additional details. 4:0 PHYAD PHY Address. The PHY Address is used for the SMI address and for initialization of the Cipher (Scrambler) key. Refer to Section 3.7.1, "PHYAD[0]: PHY Address Configuration," on page 31 for additional details. R/W NASR R/W NASR Note 4.4 Note 4.5 Note 4.4 Note 4.5 The default value of this field is determined by the MODE[2:0] configuration straps. Refer to Section 3.7.2, "MODE[2:0]: Mode Configuration," on page 31 for additional information. The default value of this field is determined by the PHYAD[0] configuration strap. Refer to Section 3.7.1, "PHYAD[0]: PHY Address Configuration," on page 31 for additional information. SMSC LAN8720A/LAN8720Ai 57 Revision 1.4 ( )

58 Symbol Error Counter Register Index (In Decimal): 26 Size: 16 bits BITS DESCRIPTION TYPE DEFAULT 15:0 SYM_ERR_CNT The symbol error counter increments whenever an invalid code symbol is received (including IDLE symbols) in 100BASE-TX mode. The counter is incremented only once per packet, even when the received packet contains more than one symbol error. This counter increments up to 65,536 (2 16 ) and rolls over to 0 after reaching the maximum value. This register is cleared on reset, but is not cleared by reading the register. This register does not increment in 10BASE-T mode. RO 0000h Revision 1.4 ( ) 58 SMSC LAN8720A/LAN8720Ai

59 Special Control/Status Indications Register Index (In Decimal): 27 Size: 16 bits BITS DESCRIPTION TYPE DEFAULT 15 AMDIXCTRL HP Auto-MDIX control: 0 = Enable Auto-MDIX 1 = Disable Auto-MDIX (use to control channel) R/W 14 RESERVED RO - 13 CH_SELECT Manual channel select: 0 = MDI (TX transmits, RX receives) 1 = MDIX (TX receives, RX transmits) R/W 12 RESERVED RO - 11 SQEOFF Disable the SQE test (Heartbeat): 0 = SQE test is enabled 1 = SQE test is disabled R/W NASR 10:5 RESERVED RO - 4 XPOL Polarity state of the 10BASE-T: 0 = Normal polarity 1 = Reversed polarity RO 3:0 RESERVED RO - SMSC LAN8720A/LAN8720Ai 59 Revision 1.4 ( )

60 Interrupt Source Flag Register Index (In Decimal): 29 Size: 16 bits BITS DESCRIPTION TYPE DEFAULT 15:8 RESERVED RO - 7 INT7 0 = not source of interrupt 1 = ENERGYON generated 6 INT6 0 = not source of interrupt 1 = Auto-Negotiation complete 5 INT5 0 = not source of interrupt 1 = Remote Fault Detected 4 INT4 0 = not source of interrupt 1 = Link Down (link status negated) 3 INT3 0 = not source of interrupt 1 = Auto-Negotiation LP Acknowledge 2 INT2 0 = not source of interrupt 1 = Parallel Detection Fault 1 INT1 0 = not source of interrupt 1 = Auto-Negotiation Page Received RO/LH RO/LH RO/LH RO/LH RO/LH RO/LH RO/LH 0 RESERVED RO Revision 1.4 ( ) 60 SMSC LAN8720A/LAN8720Ai

61 Interrupt Mask Register Index (In Decimal): 30 Size: 16 bits BITS DESCRIPTION TYPE DEFAULT 15:8 RESERVED RO - 7:1 Mask Bits 0 = interrupt source is masked 1 = interrupt source is enabled Refer to Section , "Interrupt Source Flag Register," on page 60 for details on the corresponding interrupt definitions. R/W RESERVED RO - SMSC LAN8720A/LAN8720Ai 61 Revision 1.4 ( )

62 PHY Special Control/Status Register Index (In Decimal): 31 Size: 16 bits BITS DESCRIPTION TYPE DEFAULT 15:13 RESERVED RO - 12 Autodone Auto-negotiation done indication: 0 = Auto-negotiation is not done or disabled (or not active) 1 = Auto-negotiation is done RO 11:5 RESERVED - Write as , ignore on read. R/W :2 Speed Indication HCDSPEED value: 001 = 10BASE-T half-duplex 101 = 10BASE-T full-duplex 010 = 100BASE-TX half-duplex 110 = 100BASE-TX full-duplex RO XXX 1:0 RESERVED RO - Revision 1.4 ( ) 62 SMSC LAN8720A/LAN8720Ai

63 Chapter 5 Operational Characteristics Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support 5.1 Absolute Maximum Ratings* Supply Voltage (VDDIO, VDD1A, VDD2A) (Note 5.1) V to +3.6V Digital Core Supply Voltage (VDDCR) (Note 5.1) V to +1.5V Ethernet Magnetics Supply Voltage V to +3.6V Positive voltage on signal pins, with respect to ground (Note 5.2) V Negative voltage on signal pins, with respect to ground (Note 5.3) V Positive voltage on XTAL1/CLKIN, with respect to ground V Positive voltage on XTAL2, with respect to ground V Ambient Operating Temperature in Still Air (T A ) Note 5.40 Storage Temperature o C to +150 o C Junction to Ambient (θ JA ) o C/W Junction to Case (θ JC ) o C/W Lead Temperature Range Refer to JEDEC Spec. J-STD-020 HBM ESD Performance per JEDEC JESD22-A Class 3A IEC Contact Discharge ESD Performance (Note 5.5) /-8kV IEC Air-Gap Discharge ESD Performance (Note 5.5) /-15kV Latch-up Performance per EIA/JESD /-150mA Note 5.1 Note 5.2 Note 5.3 Note 5.4 Note 5.5 When powering this device from laboratory or system power supplies, it is important that the absolute maximum ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used. This rating does not apply to the following pins: XTAL1/CLKIN, XTAL2, RBIAS. This rating does not apply to the following pins: RBIAS. 0 o C to +85 o C for extended commercial version, -40 o C to +85 o C for industrial version. Performed by independent 3rd party test facility. *Stresses exceeding those listed in this section could cause permanent damage to the device. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at any condition exceeding those indicated in Section 5.2, "Operating Conditions**", Section 5.1, "Absolute Maximum Ratings*", or any other applicable section of this specification is not implied. Note, device signals are NOT 5 volt tolerant unless specified otherwise. SMSC LAN8720A/LAN8720Ai 63 Revision 1.4 ( )

64 5.2 Operating Conditions** Supply Voltage (VDDIO) V to +3.6V Analog Port Supply Voltage (VDD1A, VDD2A) V to +3.6V Digital Core Supply Voltage (VDDCR) V to +1.26V Ethernet Magnetics Supply Voltage V to +3.6V Ambient Operating Temperature in Still Air (T A ) Note 5.4 **Proper operation of the device is guaranteed only within the ranges specified in this section. After the device has completed power-up, VDDIO and the magnetics power supply must maintain their voltage level with +/-10%. Varying the voltage greater than +/-10% after the device has completed power-up can cause errors in device operation. Do not drive input signals without power supplied to the device. 5.3 Power Consumption This section details the device power measurements taken over various operating conditions. Unless otherwise noted, all measurements were taken with power supplies at nominal values (VDDIO, VDD1A, VDD2A = 3.3V, VDDCR = 1.2V). See Section 3.8.3, "Power-Down Modes," on page 38 for a description of the power down modes. For more information on the REF_CLK modes, see Section 3.7.4, "nintsel: nint/refclko Configuration," on page REF_CLK In Mode Table 5.1 Device Only Current Consumption and Power Dissipation (REF_CLK In Mode) POWER PIN GROUP VDDA3.3 POWER PINS(mA) VDDCR POWER PIN(mA) VDDIO POWER PIN(mA) TOTAL CURRENT (ma) TOTAL POWER (mw) Max BASE-TX /W TRAFFIC Typical Min Note 5.6 Max BASE-T /W TRAFFIC Typical Min Note 5.6 Max ENERGY DETECT POWER DOWN Typical Min Note 5.6 Max GENERAL POWER DOWN Typical Min Note 5.6 Revision 1.4 ( ) 64 SMSC LAN8720A/LAN8720Ai

65 The current at VDDCR is either supplied by the internal regulator from current entering at VDD2A, or from an external 1.2V supply when the internal regulator is disabled. Current measurements do not include power applied to the magnetics or the optional external LEDs. The Ethernet component current is typically 41mA in 100BASE-TX mode and 100mA in 10BASE-T mode, independent of the 2.5V or 3.3V supply rail of the transformer. Note 5.6 Calculated with full flexpwr features activated: VDDIO=1.8V & internal regulator disabled REF_CLK Out Mode Table 5.2 Device Only Current Consumption and Power Dissipation (REF_CLK Out Mode) POWER PIN GROUP VDDA3.3 POWER PINS(MA) VDDCR POWER PIN(MA) VDDIO POWER PIN(MA) TOTAL CURRENT (MA) TOTAL POWER (MW) Max BASE-T /W TRAFFIC Typical Min Note 5.7 Max BASE-T /W TRAFFIC Typical Min Note 5.7 Max ENERGY DETECT POWER DOWN Typical Min Note 5.7 Max GENERAL POWER DOWN Typical Min Note 5.7 The current at VDDCR is either supplied by the internal regulator from current entering at VDD2A, or from an external 1.2V supply when the internal regulator is disabled. Current measurements do not include power applied to the magnetics or the optional external LEDs. The Ethernet component current is typically 41mA in 100BASE-TX mode and 100mA in 10BASE-T mode, independent of the 2.5V or 3.3V supply rail of the transformer. Note 5.7 Calculated with full flexpwr features activated: VDDIO=1.8V & internal regulator disabled. SMSC LAN8720A/LAN8720Ai 65 Revision 1.4 ( )

66 5.4 DC Specifications Table 5.3 details the non-variable I/O buffer characteristics. These buffer types do not support variable voltage operation. Table 5.4 details the variable voltage I/O buffer characteristics. Typical values are provided for 1.8V, 2.5V, and 3.3V VDDIO cases. Table 5.3 Non-Variable I/O Buffer Characteristics PARAMETER SYMBOL MIN TYP MAX UNITS NOTES IS Type Input Buffer Low Input Level V ILI -0.3 V High Input Level V IHI 3.6 V Negative-Going Threshold V ILT V Schmitt trigger Positive-Going Threshold V IHT V Schmitt trigger Schmitt Trigger Hysteresis (V IHT - V ILT ) V HYS mv Input Leakage (V IN = VSS or VDDIO) I IH ua Note 5.8 Input Capacitance C IN 2 pf O12 Type Buffers Low Output Level V OL 0.4 V I OL = 12mA High Output Level V OH VDD2A V I OH = -12mA ICLK Type Buffer (XTAL1 Input) Note 5.9 Low Input Level High Input Level V ILI -0.3 V IHI VDD2A V V Note 5.8 Note 5.9 This specification applies to all inputs and tri-stated bi-directional pins. Internal pull-down and pull-up resistors add +/- 50uA per-pin (typical). XTAL1/CLKIN can optionally be driven from a 25MHz single-ended clock oscillator. Revision 1.4 ( ) 66 SMSC LAN8720A/LAN8720Ai

67 Table 5.4 Variable I/O Buffer Characteristics PARAMETER SYMBOL MIN 1.8V TYP 2.5V TYP 3.3V TYP MAX UNITS NOTES VIS Type Input Buffer Low Input Level V ILI -0.3 V High Input Level V IHI 3.6 V Neg-Going Threshold V ILT V Schmitt trigger Pos-Going Threshold V IHT V Schmitt trigger Schmitt Trigger Hysteresis (V IHT - V ILT ) V HYS mv Input Leakage (V IN = VSS or VDDIO) I IH ua Note 5.10 Input Capacitance C IN 2 pf VO8 Type Buffers Low Output Level V OL 0.4 V I OL = 8mA High Output Level V OH VDDIO V I OH = -8mA VOD8 Type Buffer Low Output Level V OL 0.4 V I OL = 8mA Note 5.10 This specification applies to all inputs and tri-stated bi-directional pins. Internal pull-down and pull-up resistors add +/- 50uA per-pin (typical). Table BASE-TX Transceiver Characteristics PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Peak Differential Output Voltage High V PPH mvpk Note 5.11 Peak Differential Output Voltage Low V PPL mvpk Note 5.11 Signal Amplitude Symmetry V SS % Note 5.11 Signal Rise and Fall Time T RF ns Note 5.11 Rise and Fall Symmetry T RFS ns Note 5.11 Duty Cycle Distortion D CD % Note 5.12 Overshoot and Undershoot V OS % Jitter 1.4 ns Note 5.13 Note 5.11 Note 5.12 Note 5.13 Measured at line side of transformer, line replaced by 100Ω (+/- 1%) resistor. Offset from 16nS pulse width at 50% of pulse peak. Measured differentially. SMSC LAN8720A/LAN8720Ai 67 Revision 1.4 ( )

68 Table BASE-T Transceiver Characteristics PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Transmitter Peak Differential Output Voltage V OUT V Note 5.14 Receiver Differential Squelch Threshold V DS mv Note 5.14 Min/max voltages guaranteed as measured with 100Ω resistive load. 5.5 AC Specifications This section details the various AC timing specifications of the device. The SMI timing adheres to the IEEE specification. Refer to the IEEE specification for additional timing information. The RMII timing adheres to the RMII Consortium RMII Specification R Equivalent Test Load Output timing specifications assume a 25pF equivalent test load, unless otherwise noted, as illustrated in Figure 5.1 below. OUTPUT 25 pf Figure 5.1 Output Equivalent Test Load Revision 1.4 ( ) 68 SMSC LAN8720A/LAN8720Ai

69 5.5.2 Power Sequence Timing This diagram illustrates the device power sequencing requirements. The VDDIO, VDD1A, VDD2A and magnetics power supplies can turn on in any order provided they all reach operational levels within the specified time period t pon. Device power supplies can turn off in any order provided they all reach 0 volts within the specified time period p off. t pon t poff VDDIO Magnetics Power VDD1A, VDD2A Figure 5.2 Power Sequence Timing Table 5.7 Power Sequence Timing Values SYMBOL DESCRIPTION MIN TYP MAX UNITS t pon Power supply turn on time 50 ms t poff Power supply turn off time 500 ms When the internal regulator is disabled, a power-up sequencing relationship exists between VDDCR and the 3.3V power supply. For additional information refer to Section 3.7.3, "REGOFF: Internal +1.2V Regulator Configuration," on page 32. SMSC LAN8720A/LAN8720Ai 69 Revision 1.4 ( )

70 5.5.3 Power-On nrst & Configuration Strap Timing This diagram illustrates the nrst reset and configuration strap timing requirements in relation to power-on. A hardware reset (nrst assertion) is required following power-up. For proper operation, nrst must be asserted for no less than t rstia. The nrst pin can be asserted at any time, but must not be deasserted before t purstd after all external power supplies have reached 80% of their nominal operating levels. In order for valid configuration strap values to be read at power-up, the t css and t csh timing constraints must be followed. Refer to Section 3.8.5, "Resets," on page 39 for additional information. All External Power Supplies 80% t purstd nrst t purstv t rstia Configuration Strap Pins Input t css t csh Configuration Strap Pins Output Drive t otaa t odad Figure 5.3 Power-On nrst & Configuration Strap Timing Table 5.8 Power-On nrst & Configuration Strap Timing Values SYMBOL DESCRIPTION MIN TYP MAX UNITS t purstd External power supplies at 80% to nrst deassertion 25 ms t purstv External power supplies at 80% to nrst valid 0 ns t rstia nrst input assertion time 100 μs t css Configuration strap pins setup to nrst deassertion 200 ns t csh Configuration strap pins hold after nrst deassertion 1 ns t otaa Output tri-state after nrst assertion 50 ns t odad Output drive after nrst deassertion (Note 5.15) ns nrst deassertion must be monotonic. Device configuration straps are latched as a result of nrst assertion. Refer to Section 3.7, "Configuration Straps," on page 31 for details. Configuration straps must only be pulled high or low and must not be driven as inputs. Note clock cycles for 25MHz, or 40 clock cycles for 50MHz. Revision 1.4 ( ) 70 SMSC LAN8720A/LAN8720Ai

71 5.5.4 RMII Interface Timing RMII Timing (REF_CLK Out Mode) The 50MHz REF_CLK OUT timing applies to the case when nintsel is pulled-low. In this mode, a 25MHz crystal or clock oscillator must be input on the XTAL1/CLKIN and XTAL2 pins. For more information on REF_CLK Out Mode, see Section , "REF_CLK Out Mode," on page 34. t clkp REFCLKO t clkh t oval t clkl t oval t ohold RXD[1:0], RXER CRS_DV t ohold t oval t su t ihold t su t ihold t ihold TXD[1:0] t ihold t su TXEN Figure 5.4 RMII Timing (REF_CLK Out Mode) Table 5.9 RMII Timing Values (REF_CLK Out Mode) SYMBOL DESCRIPTION MIN MAX UNITS NOTES t clkp REFCLKO period 20 ns t clkh REFCLKO high time t clkp *0.4 t clkp *0.6 ns t clkl REFCLKO low time t clkp *0.4 t clkp *0.6 ns t oval t ohold t su t ihold RXD[1:0], RXER, CRS_DV output valid from rising edge of REFCLKO RXD[1:0], RXER, CRS_DV output hold from rising edge of REFCLKO TXD[1:0], TXEN setup time to rising edge of REFCLKO TXD[1:0], TXEN input hold time after rising edge of REFCLKO 5.0 ns Note ns Note ns Note ns Note 5.16 Note 5.16 Timing was designed for system load between 10 pf and 25 pf. SMSC LAN8720A/LAN8720Ai 71 Revision 1.4 ( )

72 RMII Timing (REF_CLK In Mode) The 50MHz REF_CLK IN timing applies to the case when nintsel is floated or pulled-high. In this mode, a 50MHz clock must be input on the CLKIN pin. For more information on REF_CLK In Mode, see Section , "REF_CLK In Mode," on page 34. t clkp CLKIN (REF_CLK) t clkh t oval t clkl t oval t ohold RXD[1:0], RXER CRS_DV t ohold t oval t su t ihold t su t ihold t ihold TXD[1:0] t ihold t su TXEN Figure 5.5 RMII Timing (REF_CLK In Mode) Table 5.10 RMII Timing Values (REF_CLK In Mode) SYMBOL DESCRIPTION MIN MAX UNITS NOTES t clkp CLKIN period 20 ns t clkh CLKIN high time t clkp *0.35 t clkp *0.65 ns t clkl CLKIN low time t clkp *0.35 t clkp *0.65 ns t oval t ohold t su t ihold RXD[1:0], RXER, CRS_DV output valid from rising edge of CLKIN RXD[1:0], RXER, CRS_DV output hold from rising edge of CLKIN TXD[1:0], TXEN setup time to rising edge of CLKIN TXD[1:0], TXEN input hold time after rising edge of CLKIN 14.0 ns Note ns Note ns Note ns Note 5.17 Note 5.17 Timing was designed for system load between 10 pf and 25 pf. Revision 1.4 ( ) 72 SMSC LAN8720A/LAN8720Ai

73 RMII CLKIN Requirements Table 5.11 RMII CLKIN (REF_CLK) Timing Values PARAMETER MIN TYP MAX UNITS NOTES CLKIN frequency 50 MHz CLKIN Frequency Drift ± 50 ppm CLKIN Duty Cycle % CLKIN Jitter 150 psec p-p not RMS SMI Timing This section specifies the SMI timing of the device. Please refer to Section 3.5, "Serial Management Interface (SMI)," on page 28 for additional details. t clkp MDC t val t clkh t ohold t clkl MDIO (Data-Out) t ohold t su t ihold MDIO (Data-In) Figure 5.6 SMI Timing Table 5.12 SMI Timing Values SYMBOL DESCRIPTION MIN MAX UNITS NOTES t clkp MDC period 400 ns t clkh MDC high time 160 (80%) ns t clkl MDC low time 160 (80%) ns t val t ohold t su t ihold MDIO (read from PHY) output valid from rising edge of MDC MDIO (read from PHY) output hold from rising edge of MDC MDIO (write to PHY) setup time to rising edge of MDC MDIO (write to PHY) input hold time after rising edge of MDC 300 ns 0 ns 10 ns 10 ns SMSC LAN8720A/LAN8720Ai 73 Revision 1.4 ( )

74 5.6 Clock Circuit The device can accept either a 25MHz crystal or a 25MHz single-ended clock oscillator (±50ppm) input. If the single-ended clock oscillator method is implemented, XTAL2 should be left unconnected and XTAL1/CLKIN should be driven with a nominal 0-3.3V clock signal. See Table 5.13 for the recommended crystal specifications. Table 5.13 Crystal Specifications PARAMETER SYMBOL MIN NOM MAX UNITS NOTES Crystal Cut AT, typ Crystal Oscillation Mode Fundamental Mode Crystal Calibration Mode Parallel Resonant Mode Frequency F fund MHz Frequency 25 o C F tol - - ±50 PPM Note 5.18 Frequency Stability Over Temp F temp - - ±50 PPM Note 5.18 Frequency Deviation Over Time F age - +/-3 to 5 - PPM Note 5.19 Total Allowable PPM Budget - - ±50 PPM Note 5.20 Shunt Capacitance C O - 7 typ - pf Load Capacitance C L - 20 typ - pf Drive Level P W uw Equivalent Series Resistance R Ohm Operating Temperature Range Note o C XTAL1/CLKIN Pin Capacitance - 3 typ - pf Note 5.22 XTAL2 Pin Capacitance - 3 typ - pf Note 5.22 Note 5.18 Note 5.19 Note 5.20 Note 5.21 Note 5.22 The maximum allowable values for Frequency Tolerance and Frequency Stability are application dependant. Since any particular application must meet the IEEE ±50 PPM Total PPM Budget, the combination of these two values must be approximately ±45 PPM (allowing for aging). Frequency Deviation Over Time is also referred to as Aging. The total deviation for the Transmitter Clock Frequency is specified by IEEE 802.3u as ±100 PPM. 0 o C for extended commercial version, -40 o C for industrial version. This number includes the pad, the bond wire and the lead frame. PCB capacitance is not included in this value. The XTAL1/CLKIN pin, XTAL2 pin and PCB capacitance values are required to accurately calculate the value of the two external load capacitors. The total load capacitance must be equivalent to what the crystal expects to see in the circuit so that the crystal oscillator will operate at MHz. Revision 1.4 ( ) 74 SMSC LAN8720A/LAN8720Ai

75 Chapter 6 Package Outline MIN NOMINAL MAX REMARKS A Overall Package Height A Standoff A Mold Cap Thickness D/E X/Y Body Size D1/E X/Y Mold Cap Size D2/E X/Y Exposed Pad Size L Terminal Length b Terminal Width k Terminal to Exposed Pad Clearance e 0.50 BSC Terminal Pitch Notes: 1. All dimensions are in millimeters unless otherwise noted. 2. Dimension b applies to plated terminals and is measured between 0.15 and 0.30 mm from the terminal tip. 3. The pin 1 identifier may vary, but is always located within the zone indicated. SMSC LAN8720A/LAN8720Ai 75 Revision 1.4 ( )

76 Revision 1.4 ( ) 76 SMSC LAN8720A/LAN8720Ai

77 Standard reel size is 4000 pieces per reel. SMSC LAN8720A/LAN8720Ai 77 Revision 1.4 ( )