Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/ 100 Mbps PHY Transceivers

Transcription

1 Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/ 100 Mbps PHY Transceivers The Cortina Systems LXT9785 and LXT9785E are 8-port Fast Ethernet PHY Transceivers supporting IEEE physical layer applications at 10 Mbps and 100 Mbps. These devices provide Serial/Source Synchronous Serial Media Independent Interfaces (SMII/SS-SMII) and Reduced Media Independent Interface (RMII) for switching and other independent port applications. The LXT9785 and LXT9785E are identical except for the IP telephony features included in the LXT9785E transceiver. The LXT9785E is an enhanced version of the LXT9785 that detects Data Terminal Equipment (DTE) requiring power from the switch over a CAT5 cable. The system uses the information collected by the LXT9785E to apply power if the DTE at the far end requires power over the cable, such as an IP telephone. Each network port can provide a twisted-pair (TP) or Low-Voltage Positive Emitter Coupled Logic (LVPECL) interface. The twisted-pair interface supports 10 Mbps and 100 Mbps (10BASE-T and 100BASE-TX) Ethernet over twisted-pair. The LVPECL interface supports 100 Mbps (100BASE-FX) Ethernet over fiber-optic media. The LXT9785/LXT9785E provides three discrete LED driver outputs for each port. The devices support both half-duplex and full-duplex operation at 10 Mbps and 100 Mbps and require only a single 2.5 V power supply. Applications Enterprise switches IP telephony switches Storage Area Networks Multi-port Network Interface Cards (NICs) Product Features Eight IEEE compliant 10BASE-T or 100BASE-TX ports with integrated filters. 100BASE-FX fiber-optic capability on all ports. 2.5 V operation. Low power consumption; 250 mw per port typical. Multiple RMII or SMII/SS-SMII ports for independent PHY port operation. Auto MDI/MDIX crossover capability. Proprietary Optimal Signal Processing architecture improves SNR by 3 db over ideal analog filters. Optimized for dual-high stacked RJ-45 applications. MDIO sectionalization into 2x4 or 1x8 configurations. Supports both auto-negotiation systems and legacy systems without auto-negotiation capability. Robust baseline wander correction. Configurable through the MDIO port or external control pins. JTAG boundary scan. 208-pin PQFP: LXT9785HC, LXT9785EHC, LXT9785HE. 241-ball BGA: LXT9785BC, LXT9785EBC. 196-ball BGA: LXT9785MBC (includes DTE detection similar to the LXT9785E) DTE detection for remote powering applications (LXT9785E and LXT9785MBC only). Extended temperature operation of -40 o C to +85 o C (LXT9785E only).

2 Contents Contents 1.0 Introduction What You Will Find in This Document Related Documents Block Diagram Pin/Ball Assignments and Signal Descriptions PQFP Pin Assignments PQFP Pin Assignments RMII Configuration PQFP Pin Assignments SMII Configuration PQFP Pin Assignments SS-SMII Configuration PQFP Signal Descriptions Signal Name Conventions PQFP Signal Descriptions RMII, SMII, and SS-SMII Configurations BGA23 Ball Assignments RMII BGA23 Ball List SMII BGA23 Ball List SS-SMII BGA23 Ball List BGA23 Signal Descriptions Signal Name Conventions Signal Descriptions RMII, SMII, and SS-SMII Configurations BGA15 Ball Assignments BGA15 Ball List BGA15 Signal Descriptions Signal Name Conventions Signal Descriptions SMII and SS-SMII Configurations Functional Description Introduction OSP Architecture Comprehensive Functionality Sectionalization Interface Descriptions /100 Network Interface Twisted-Pair Interface MDI Crossover (MDIX) Fiber Interface Media Independent Interface (MII) Interfaces Global MII Mode Select Internal Loopback RMII Data Interface Serial Media Independent Interface (SMII) and Source Synchronous- Serial Media Independent Interface (SS-SMII) SMII Interface Source Synchronous-Serial Media Independent Interface Configuration Management Interface MII Isolate MDIO Management Interface MII Sectionalization Page 2

3 Contents MII Interrupts Global Hardware Control Interface FIFO Initial Fill Values Operating Requirements Power Requirements Clock/SYNC Requirements Reference Clock TxCLK Signal (SS-SMII only) TxSYNC Signal (SMII/SS-SMII) RxSYNC Signal (SS-SMII only) RxCLK Signal (SS-SMII Only) Initialization MDIO Control Mode Hardware Control Mode Power-Down Mode Global (Hardware) Power Down Port (Software) Power Down Reset Hardware Configuration Settings Link Establishment Auto-Negotiation Base Page Exchange Manual Next Page Exchange Controlling Auto-Negotiation Link Criteria Parallel Detection Reliable Link Establishment While Auto MDI/MDIX is Enabled in Forced Speed Mode Serial MII Operation SMII Reference Clock TxSYNC Pulse (SMII/SS-SMII) Transmit Data Stream Transmit Enable Transmit Error Receive Data Stream Carrier Sense Receive Data Valid Receive Error Receive Status Encoding Collision Source Synchronous-Serial Media Independent Interface RMII Operation RMII Reference Clock Transmit Enable Carrier Sense & Data Valid Receive Error Out-of-Band Signaling Mbps Operation BASE-X Network Operations BASE-X Protocol Sublayer Operations PCS Sublayer Page 3

4 Contents PMA Sublayer Link Link Failure Override Carrier Sense/Data Valid (RMII) Carrier Sense (SMII) Receive Data Valid (SMII) Twisted-Pair PMD Sublayer Fiber PMD Sublayer Mbps Operation Preamble Handling Dribble Bits Link Test Link Failure Jabber DTE Discovery Process Definitions Interaction between Processor, MAC, and PHY Management Interface and Control DTE Discovery Process Flow DTE Discovery Behavior Monitoring Operations Monitoring Auto-Negotiation Per-Port LED Driver Functions Out-of-Band Signaling Boundary Scan Interface State Machine Instruction Register Boundary Scan Register Cable Diagnostics Overview Features Operation Short and Long Cable Testing Requirements Precision Implementation Considerations Basic Implementation Link Hold-Off Overview Features Operation Application Information Design Recommendations General Design Guidelines Power Supply Filtering Power and Ground Plane Layout Considerations Chassis Ground MII Terminations Twisted-Pair Interface Magnetic Requirements The Fiber Interface LED Circuit Typical Application Circuits Page 4

5 Contents 6.0 Test Specifications Register Definitions Package Specifications Top Label Markings Ordering Information Page 5

6 Figures Figures 1 Block Diagram RMII 208-Pin PQFP Assignments SMII 208-Pin PQFP Assignments SS-SMII 208-Pin PQFP Assignments Ball BGA23 Assignments (Top View) Ball BGA15 Assignments (Top View) Interface Signals Internal Loopback Management Interface Read Frame Structure Management Interface Write Frame Structure Port Address Scheme Interrupt Logic Initialization Sequence Auto-Negotiation Operation Typical SMII Interface Typical SMII Quad Sectionalization Mbps Serial MII Data Flow Serial MII Transmit Synchronization Serial MII Receive Synchronization Typical SS-SMII Interface Typical SS-SMII Quad Sectionalization SS-SMII Transmit Timing SS-SMII Receive Timing RMII Data Flow Typical RMII Interface Typical RMII Quad Sectionalization BASE-X Frame Format Protocol Sublayers Typical IP Telephone System Connection Cortina Systems LXT9785E Negotiation Flow Chart LED Pulse Stretching RMII Programmable Out-of-Band Signaling LED Circuit Power and Ground Supply Connections Typical Twisted-Pair Interface Recommended LXT9785/LXT9785E-to-3.3 V Fiber Transceiver Interface Circuitry Recommended LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface Circuitry ON Semiconductor Triple PECL-to-LVPECL Translator SMII - 100BASE-TX Receive Timing SMII - 100BASE-TX Transmit Timing SMII - 100BASE-FX Receive Timing SMII - 100BASE-FX Transmit Timing SMII - 10BASE-T Receive Timing SMII - 10BASE-T Transmit Timing SS-SMII - 100BASE-TX Receive Timing SS-SMII - 100BASE-TX Transmit Timing SS-SMII - 100BASE-FX Receive Timing SS-SMII - 100BASE-FX Transmit Timing Page 6

7 Figures 49 SS-SMII - 10BASE-T Receive Timing SS-SMII - 10BASE-T Transmit Timing RMII - 100BASE-TX Receive Timing RMII - 100BASE-TX Transmit Timing RMII - 100BASE-FX Receive Timing RMII - 100BASE-FX Transmit Timing RMII - 10BASE-T Receive Timing RMII - 10BASE-T Transmit Timing Auto-Negotiation and Fast Link Pulse Timing Fast Link Pulse Timing MDIO Write Timing (MDIO Sourced by MAC) MDIO Read Timing (MDIO Sourced by PHY) Power-Up Timing RESET_L Recovery Timing PHY Identifier Bit Mapping Pin PQFP Plastic Package Specification Ball BGA23 Package Specificationss - Top/Side Views (LXT9785BC) Ball BGA23 Package Specificationss - Bottom View (LXT9785BC) Ball BGA15 Package Specs - Top/Side Views (LXT9785MBC) Ball BGA15 Package Bottom View (LXT9785MBC ) Example of Top Marking Information Labeled as Cortina Systems, Inc Example of Top Marking Information Labeled as Intel Corporation* Example of Top Marking Information Labeled as Level One Communications* Ordering Information - Sample Page 7

8 Tables Tables 1 Signal Type Descriptions RMII PQFP Pin List SMII PQFP Pin List SS-SMII PQFP Pin List RMII Signal Descriptions PQFP SMII/SS-SMII Common Signal Descriptions PQFP SMII Specific Signal Descriptions PQFP SS-SMII Specific Signal Descriptions PQFP MDIO Control Interface Signals PQFP Signal Detect PQFP Network Interface Signal Descriptions PQFP JTAG Test Signal Descriptions PQFP Miscellaneous Signal Descriptions PQFP LED Signal Descriptions PQFP Power Supply Signal Descriptions PQFP Unused/Reserved Pins PQFP Receive FIFO Depth Considerations RMII BGA23 Ball List in Alphanumeric Order by Signal Name RMII BGA23 Ball List in Alphanumeric Order by Ball Location SMII BGA23 Ball List in Alphanumeric Order by Signal Name SMII BGA23 Ball List in Alphanumeric Order by Ball Location SS-SMII BGA23 Ball List in Alphanumeric Order by Signal Name SS-SMII BGA23 Ball List in Alphanumeric Order by Ball Location RMII Signal Descriptions BGA SMII/SS-SMII Common Signal Descriptions BGA SMII Specific Signal Descriptions BGA SS-SMII Specific Signal Descriptions BGA MDIO Control Interface Signals BGA Signal Detect BGA Network Interface Signal Descriptions BGA JTAG Test Signal Descriptions BGA Miscellaneous Signal Descriptions BGA LED Signal Descriptions BGA Power Supply Signal Descriptions BGA Unused/Reserved Pins BGA Receive FIFO Depth Configurations LXT9785MBC BGA15 Ball List in Alphanumeric Order by Signal Name LXT9785MBC BGA15 Ball List in Alphanumeric Order by Ball Location (SMII/SS-SMII) BGA15 Signal Descriptions MDIX Selection MII Mode Select Global Hardware Configuration Settings SMII Signal Summary RX Status Encoding Bit Definitions SS-SMII B/5B Coding DTE Terms Next Page Message #5 Code Word Definitions Page 8

9 Tables 49 BSR Mode of Operation Supported JTAG Instructions Magnetics Requirements Absolute Maximum Ratings Operating Conditions Digital I/O DC Electrical Characteristics (VCCIO = 2.5 V +/- 5%) Digital I/O DC Electrical Characteristics (VCCIO = 3.3 V +/- 5%) Digital I/O DC Electrical Characteristics SD Pins Required Clock Characteristics BASE-TX Transceiver Characteristics BASE-FX Transceiver Characteristics BASE-T Transceiver Characteristics SMII - 100BASE-TX Receive Timing Parameters SMII - 100BASE-TX Transmit Timing Parameters SMII - 100BASE-FX Receive Timing Parameters SMII - 100BASE-FX Transmit Timing Parameters SMII - 10BASE-T Receive Timing Parameters SMII-10BASE-T Transmit Timing Parameters SS-SMII - 100BASE-TX Receive Timing Parameters SS-SMII - 100BASE-TX Transmit Timing SS-SMII - 100BASE-FX Receive Timing Parameters SS-SMII - 100BASE-FX Transmit Timing Parameters SS-SMII - 10BASE-T Receive Timing Parameters SS-SMII - 10BASE-T Transmit Timing Parameters RMII - 100BASE-TX Receive Timing Parameters RMII - 100BASE-TX Transmit Timing Parameters RMII - 100BASE-FX Receive Timing Parameters RMII - 100BASE-FX Transmit Timing Parameters RMII - 10BASE-T Receive Timing Parameters RMII - 10BASE-T Transmit Timing Parameters Auto-Negotiation and Fast Link Pulse Timing Parameters MDIO Timing Parameters Power-Up Timing Parameters RESET_L Recovery Timing Parameters Register Set Control Register (Address 0) Status Register (Address 1) PHY Identification Register 1 (Address 2) PHY Identification Register 2 (Address 3) Auto-Negotiation Advertisement Register (Address 4) Auto-Negotiation Link Partner Base Page Ability Register (Address 5) Auto-Negotiation Expansion Register (Address 6) Auto-Negotiation Next Page Transmit Register (Address 7) Auto-Negotiation Link Partner Next Page Receive Register (Address 8) Port Configuration Register (Address 16, Hex 10) Quick Status Register (Address 17, Hex 11) Interrupt Enable Register (Address 18, Hex 12) Interrupt Status Register (Address 19, Hex 13) LED Configuration Register (Address 20, Hex 14) Receive Error Count Register (Address 21, Hex 15) Page 9

10 Tables 99 RMII Out-of-Band Signaling Register (Address 25, Hex 19) Trim Enable Register (Address 27, Hex 1B) Cable Diagnostics Register (Address 29, Hex 1D) Register Bit Map Ball BGA23 Package Dimensions Ball BGA15 Package Dimensions (LXT9785MBC ) Product Information Page 10

11 Revision History Revision History First release of this document from Cortina Systems, Inc. Revision 11.0 Revision Date: Revision Number: 010 Revision Date: 30-Mar-2006 Page Description page 48 page 93 page 123 Modified signal description text for VCCPECL in Table 15, Power Supply Signal Descriptions PQFP. Modified signal description text for VCCPECL in Table 34, Power Supply Signal Descriptions BGA23. Added note under Section , RxCLK Signal (SS-SMII Only). page 126 Modified CFG (1,2,3) settings for Register bit 0.8 when set to 1 in Table 42, Global Hardware Configuration Settings. page 192 Added table note 6 to Register bit 0.14 (Loopback) in Table 84, Control Register (Address 0). page 195 Modified table note 6 (for Register bit 4.13) in Table 88, Auto-Negotiation Advertisement Register (Address 4). page 200 Modified note in Register bit (Collision Status) in Table 94, Quick Status Register (Address 17, Hex 11). page 217 Added Section 8.1, Top Label Markings. page 219 Modified Section 9.0, Ordering Information (Table 105, Product Information and Figure 72, Ordering Information - Sample. Revision Number: 009 Revision Date: April 30, 2004 Page Description 1 Modified 196-Ball BGA and DTE Detection bullets under Product Features. 43 Added table note 3 (regarding LINKHOLD) to Table 13, Miscellaneous Signal Descriptions PQFP, on page Added table note 3 (regarding LINKHOLD) to Table 32, Miscellaneous Signal Descriptions BGA23, on page Modified Table 18 RMII BGA23 Ball List in Alphanumeric Order by Signal Name through Table 23 SS-SMII BGA23 Ball List in Alphanumeric Order by Ball Location for ball, type, and reference page corrections. 229 Modified Table 104 Product Information [added new packaging information]. 230 Modified Figure 69 Ordering Information - Sample [changed Internal Package Designator for B and E, and added the GD and definition under Package Designator). Revision Number: 008 Revision Date: April 15, 2004 Page Description All Globally added LEDn_3 to BGA Added Figure 68 Cortina Systems LXT9785MBC 196-Ball BGA15 Package Bottom View. Page 11

12 Revision History Revision Number: 007 Revision Date: August 28, 2003 Page Description 21 Modified Figure 2 Cortina Systems LXT9785 and Cortina Systems LXT9785E RMII 208-Pin PQFP Assignments. 22 Modified Table 2 Cortina Systems LXT9785/LXT9785E RMII PQFP Pin List. 26 Modified Figure 3 Cortina Systems LXT9785/LXT9785E SMII 208-Pin PQFP Assignments. 27 Modified Table 3 Cortina Systems LXT9785/LXT9785E SMII PQFP Pin List. 31 Modified Figure 4 Cortina Systems LXT9785/LXT9785E SS-SMII 208-Pin PQFP Assignments. 32 Modified Table 4 Cortina Systems LXT9785/LXT9785 SS-SMII PQFP Pin List. 36 Modified Table 5 Cortina Systems LXT9785/LXT9785E RMII Signal Descriptions PQFP. 40 Modified Table 8 Cortina Systems LXT9785/LXT9785E SS-SMII Specific Signal Descriptions PQFP. 43 Modified Table 13 Cortina Systems LXT9785/LXT9785E Miscellaneous Signal Descriptions PQFP. 50 Modified Table 16 Cortina Systems LXT9785/LXT9785E Unused/Reserved Pins PQFP Replaced old Figures 5, 6, and 7 with Figure 5 Cortina Systems LXT9785/LXT9785E 241-Ball BGA23 Assignments (Top View). Modified Table 18 Cortina Systems LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by Signal Name. Modified Table 19 Cortina Systems LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by Ball Location. Modified Table 20 Cortina Systems LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by Signal Name. Modified Table 21 Cortina Systems LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by Ball Location Modified Table 22 Cortina Systems LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by Signal Name. Modified Table 23 Cortina Systems LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by Ball Location. 82 Modified Table 23 Cortina Systems LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by Ball Location. 86 Modified Table 27 Cortina Systems LXT9785/LXT9785E SS-SMII Specific Signal Descriptions BGA Modified Table 32 Cortina Systems LXT9785/LXT9785E Miscellaneous Signal Descriptions BGA Modified Table 35 Cortina Systems LXT9785/LXT9785E Unused/Reserved Pins BGA23. Added Section 3.5, BGA15 Ball Assignments (including Figure 6 Cortina Systems LXT9785MBC 196-Ball 98 BGA15 Assignments (Top View), Table 37 Cortina Systems LXT9785MBC BGA15 Ball List in Alphanumeric Order by Signal Name through Table 39 Cortina Systems LXT9785 BGA15 Signal Descriptions. 116 Added second paragraph under Section 4.1, Introduction. 117 Added note under Section , Sectionalization. 119 Added note under Table 40 Cortina Systems LXT9785/LXT9785E MDIX Selection. 119 Added note under Section 4.3, Media Independent Interface (MII) Interfaces. 120 Added note to Table 41 Cortina Systems LXT9785/LXT9785E MII Mode Select. 120 Modified/added text under Section 4.3.2, Internal Loopback. 121 Modified text under Section 4.3.6, MII Isolate. Page 12

13 Revision History Revision Number: 007 Revision Date: August 28, 2003 Page 121 Description Section 4.3.7, MDIO Management Interface : Added note under second paragraph. Added last paragraph. 123 Added note under Section 4.3.8, MII Sectionalization. 124 Added new Section , FIFO Initial Fill Values 125 Modified paragraph three under Section 4.4.1, Power Requirements. 127 Added notes under second and last paragraphs under Section 4.5.3, Power-Down Mode. 128 Modified last bullet under Section , Global (Hardware) Power Down. 128 Added last paragraph to Section 4.5.4, Reset. 129 Modified Table 42 Cortina Systems LXT9785/LXT9785E Global Hardware Configuration Settings. 130 Change heading and modified last line under Section , Manual Next Page Exchange. 130 Section , Link Criteria : Changed scrambler to descrambler in first line. Modified second paragraph. Added two new paragraphs. 131 Added second paragraph under Section , Parallel Detection. 131 Modified paragraphs under Section , Reliable Link Establishment While Auto MDI/MDIX is Enabled in Forced Speed Mode. 136 Changed 1110 to 0101 under Section , Receive Error. 141 Added note under first paragraph of Section 4.8, RMII Operation 148 Changed asynchronously to synchronously in second paragraph under Section , Carrier Sense/Data Valid (RMII). 148 Modified last sentence in first paragraph under Section , Carrier Sense (SMII). 149 Modified paragraph under Section , Polarity Correction. 149 Added note under Section , Fiber PMD Sublayer. 149 Added second paragraph under Section , Far End Fault Indications. 150 Modified/added text under Section , Preamble Handling. 151 Modified text under Section , Jabber. 152 Modified first paragraph under Section 4.11, DTE Discovery Process. 153 Modified Item 1 of Section , Interaction between Processor, MAC, and PHY. 154 Modified second paragraph under Section , DTE Discovery Process Flow. 155 Added Section , DTE Discovery Behavior 157 Added BGA15 information into first paragraph under Section , Per-Port LED Driver Functions. 158 Added last sentence to first paragraph and note under first paragraph under Section , Out-of-Band Signaling. 160 Added Section 4.13, Cable Diagnostics Overview. 161 Modified/added text under Section , Implementation Considerations. 162 Added Section 4.14, Link Hold-Off Overview. 173 Modified Table 52 Cortina Systems LXT9785/LXT9785E Operating Conditions 176 Modified Table 58 Cortina Systems LXT9785/LXT9785E 100BASE-FX Transceiver Characteristics Page 13

14 Revision History Revision Number: 007 Revision Date: August 28, 2003 Page Description Added note to Table 60 Cortina Systems LXT9785/LXT9785E SMII - 100BASE-TX Receive Timing Parameters through Table 77 Cortina Systems LXT9785/LXT9785E RMII - 10BASE-T Transmit Timing Parameters Added table note to Table 60 Cortina Systems LXT9785/LXT9785E SMII - 100BASE-TX Receive Timing Parameters. Added table note to Table 66 Cortina Systems LXT9785/LXT9785E SS-SMII - 100BASE-TX Receive Timing Parameters. Added table note to Table 72 Cortina Systems LXT9785/LXT9785E RMII - 100BASE-TX Receive Timing Parameters 198 Added software power-down and note to Table 80 Cortina Systems LXT9785/LXT9785E Power-Up Timing Parameters. 199 Modified paragraphs and added last paragraph under Section 7.0, Register Definitions. 199 Modified Table 82 Cortina Systems LXT9785/LXT9785E Register Set. 200 Modified Table 83 Control Register (Address 0). 201 Modified Table 84 Status Register (Address 1). 203 Modified Table 85 PHY Identification Register 1 (Address 2). 203 Modified Table 86 PHY Identification Register 2 (Address 3) 204 Modified Table 87 Auto-Negotiation Advertisement Register (Address 4) 205 Modified Table 88 Auto-Negotiation Link Partner Base Page Ability Register (Address 5). 206 Modified Table 89 Auto-Negotiation Expansion Register (Address 6). 206 Modified Table 90 Auto-Negotiation Next Page Transmit Register (Address 7). 206 Modified Table 91 Auto-Negotiation Link Partner Next Page Receive Register (Address 8). 207 Modified Table 92 Port Configuration Register (Address 16, Hex 10). (Register bits 16.6, 16.4:3) 209 Modified Table 93 Quick Status Register (Address 17, Hex 11). (Register bit 17.8) 211 Modified Table 94 Interrupt Enable Register (Address 18, Hex 12) 212 Modified Table 95 Interrupt Status Register (Address 19, Hex 13) 213 Modified Table 96 LED Configuration Register (Address 20, Hex 14) 214 Modified Table 97 Receive Error Count Register (Address 21, Hex 15). 215 Modified Table 98 RMII Out-of-Band Signaling Register (Address 25, Hex 19). 216 Modified Table 99 Trim Enable Register (Address 27, Hex 1B). (Register bit 27.6) 217 Added Table 100 Cable Diagnostics Register (Address 29, Hex 1D). 219 Modified Table 101 Cortina Systems LXT9785/LXT9785E Register Bit Map. 226 Added Figure 102 Cortina Systems LXT9785MBC 196-Ball BGA15 Package Dimensions 227 Modified table and figure under Section 9.0, Ordering Information. Page 14

15 Revision History Revision Number: 006 (INTERNAL RELEASE) Revision Date: June 10, 2003 Page Description 1 Changed "pseudo-ecl (PECL)" to "Low Voltage Positive Emitter Coupled Logic (LVPECL)" in the second paragraph, front page. 36 Modified Table 5 Cortina Systems LXT9785/LXT9785E RMII Signal Descriptions PQFP. Added last sentence to RXER0 through RXER7 signal description. 42 Modified Table 10 Cortina Systems LXT9785/LXT9785E Signal Detect PQFP. 42 Modified Table 11 Cortina Systems LXT9785/LXT9785E Network Interface Signal Descriptions PQFP, 43 Modified Table 13 Cortina Systems LXT9785/LXT9785E Miscellaneous Signal Descriptions PQFP. Added note to PREASEL signal description. 116 Modified Section 4.1, Introduction. Changed "Pseudo-ECL (PECL)" to "Low Voltage PECL (LVPECL)" in the first paragraph, second sentence. 119 Replace text under Section , Fiber Interface. 120 Modified Section 4.3.2, Internal Loopback. 130 Modified last sentence under Section , Link Criteria. 131 Modified text under Section , Parallel Detection. Added second paragraph. 136 Modified text under Section , Receive Error. 145 Changed "PECL" to "LVPECL in third paragraph, first sentence under Section 4.9.1, 100BASE-X Network Operations. 146 Modified Figure 28 Cortina Systems LXT9785/LXT9785E Protocol Sublayers. 148 Modified Section , Carrier Sense/Data Valid (RMII). Changed asynchronously to synchronously. 148 Modified text under Section , Carrier Sense (SMII). Revised last sentence in first paragraph. 149 Modified paragraph under Section , Polarity Correction. 149 Replaced text under Section , Fiber PMD Sublayer. 150 Modified Section , Preamble Handling. Added text to last paragraph. 151 Modified first sentence under Section , Jabber. 152 Modified first paragraph of Section 4.11, DTE Discovery Process. 153 Modified Item 1 of Section , Interaction between Processor, MAC, and PHY. 158 Modified Section , Out-of-Band Signaling. Added sentence to end of first paragraph. 166 Replaced text under Section 5.2.5, The Fiber Interface. 170 Replaced Figure 36 Recommended Cortina Systems LXT9785/LXT9785E-to-3.3 V Fiber Transceiver Interface Circuitry. 171 Replaced Figure 37 Recommended Cortina Systems LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface Circuitry. 173 Modified Table 52 Cortina Systems LXT9785/LXT9785E Operating Conditions. 174 Modified Table 53 Cortina Systems LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO = 2.5 V +/- 5%). 175 Modified Table 54 Cortina Systems LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO = 3.3 V +/- 5%). 175 Added Table 55 Cortina Systems LXT9785/LXT9785E Digital I/O DC Electrical Characteristics SD Pins. 176 Modified Table 58 Cortina Systems LXT9785/LXT9785E 100BASE-FX Transceiver Characteristics. Page 15

16 Revision History Revision Number: 006 (INTERNAL RELEASE) Revision Date: June 10, 2003 Page Description 200 Modified Table 83 Control Register (Address 0). 201 Modified Table 84 Status Register (Address 1). 204 Modified Table 87 Auto-Negotiation Advertisement Register (Address 4). 205 Modified Table 88 Auto-Negotiation Link Partner Base Page Ability Register (Address 5). 207 Modified Table 91 Auto-Negotiation Link Partner Next Page Receive Register (Address 8). 207 Modified Table 92 Port Configuration Register (Address 16, Hex 10). 209 Modified Table 93 Quick Status Register (Address 17, Hex 11). 211 Modified Table 94 Interrupt Enable Register (Address 18, Hex 12) 212 Modified Table 95 Interrupt Status Register (Address 19, Hex 13). Changed all references of RO/SC to R/LH. 214 Modified Table 97 Receive Error Count Register (Address 21, Hex 15). 215 Modified Table 98 RMII Out-of-Band Signaling Register (Address 25, Hex 19). Added note to Register bit Modified Table 99 Trim Enable Register (Address 27, Hex 1B). 227 Modified Table 103 Product Information. Revision Number: 005 Revision Date: January 2002 Page Description 1 Added bullet to Product Features 49 Modified Table 12 Cortina Systems LXT9785/LXT9785E Miscellaneous Signal Descriptions (Added FIFOSEL1 and FIFOSEL0) 70 Added Section , Reliable Link Establishment While Auto MDI/MDIX is Enabled in Forced Speed Mode 109 Modified Figure 38 Recommended Cortina Systems LXT9785/LXT9785E-to-3.3 V Fiber Transceiver Interface Circuitry 110 Added Figure 39 Recommended Cortina Systems LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface Circuitry 111 Added Figure 40 ON Semiconductor Triple PECL-to-LVPECL Translator 112 Modified Table 28 Absolute Maximum Ratings 112 Modified Table 29 Operating Conditions Modified Table 31 Digital I/O DC Electrical Characteristics (VCCIO = 3.3 V +/- 5%) (Output low voltage SD pins - Max) Modified Figure 53 RMII - 100BASE-TX Receive Timing and Table 49 RMII - 100BASE-TX Receive Timing Parameters Modified Figure 55 RMII - 100BASE-FX Receive Timing and Table 51 RMII - 100BASE-FX Receive Timing Parameters Modified Figure 57 RMII - 10BASE-T Receive Timing and Table 53 RMII - 10BASE-T Receive Timing Parameters Page 16

17 Revision History Revision Number: 005 Revision Date: January 2002 Page Description 146 Modified Table 69 Port Configuration Register (Address 16, Hex 10) (Bits 16.5 and 16.6) 148 Modified Table 71 Interrupt Enable Register (Address 18, Hex 12) 168 Added product ordering table and diagram. Revision Number: 003 Revision Date: April 2001 Page Description 1 Modified and added new language to front page. 61 Reset: Modified language in first paragraph. 85 Added new section on DTE discovery. 93 Supported JTAG Instructions table: replaced long hit streams with hex. 97 LED Circuit: Modified paragraph language. 97 LED Circuit diagram: Modified diagram. 99 Replaced Typical Fiber Interface diagram. 102 Required Clock Characteristics table: Replaced SMII Input frequency and RMII Input frequency symbol with f. 122 Auto-Negotiation and Fast Link Pulse Timing Parameters: FLP burst width under Typ = Control Register table: Modified table and table notes. 128 PHY Identification Register 2 (Address 3): Modified table. 128 PHY Identifier Bit Mapping: Modified diagram. 131 Auto-Negotiation Expansion: Modified table and table notes. 133 Port Configuration Register table: Modified table and table notes. 140 Trim Enable Register: Modified table (DTE Discovery). 141 Modified Register Bit Map table. Page 17

18 1.0 Introduction 1.0 Introduction This document contains information on the Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers. 1.1 What You Will Find in This Document This document contains the following sections: Section 2.0, Block Diagram, on page 19 Section 3.0, Pin/Ball Assignments and Signal Descriptions, on page 20 This section contains pin/ball assignments and signal descriptions for the following: Section 3.1, PQFP Pin Assignments, on page 20 Section 3.2, PQFP Signal Descriptions, on page 36 Section 3.3, BGA23 Ball Assignments, on page 51 Section 3.4, BGA23 Signal Descriptions, on page 79 Section 3.5, BGA15 Ball Assignments, on page 97 Section 3.6, BGA15 Signal Descriptions, on page 106 Section 4.0, Functional Description, on page 113 Section 5.0, Application Information, on page 161 Section 6.0, Test Specifications, on page 170 Section 7.0, Register Definitions, on page 191 Section 8.0, Package Specifications, on page 212 Section 9.0, Ordering Information, on page Related Documents Document Document Number Cortina Systems LXT9785/LXT9785E Design and Layout Guide Cortina Systems LXT9785/LXT9785E Specification Update Cortina Systems LXT9785/LXT9785E 100BASE-FX Fiber Optic Transceivers: Connecting a PECL/LVPECL Interface IP Telephony and DTE Discovery Using Cortina Systems Ethernet PHYs Page 18

19 2.0 Block Diagram 2.0 Block Diagram Figure 1 provides the LXT9785/LXT9785E block diagram. Figure 1 Block Diagram RMII/SMII Contr ADD_[4:0] MDIO MDC MDINT_L TxDatan TX PCS Mgmt Counters Register Set Management / Mode Select Logic & LED Drivers Register Set Parallel/Serial Converter Auto Negotiation Manchester 10 Encoder Scrambler 100 & Encoder 8-Port Global Functions Pulse Shaper TP Driver ECL Driver Clock Generator TP / Fiber Out RESET_L PWRDN REFCLK SYNC (SMII only) TPFOPn TPFONn Fiber selectn LEDn_[3:1]_L RxDatan 3 RX PCS Port LED Drivers Carrier Sense Data Valid Error Detect Serial to Parallel Converter Clock Generator Manchester Decoder Decoder & Descrambler Slicer Media Select Per-Port Functions Adaptive EQ with BL Wander Cancellation 100TX 100FX 10BT - PORT 0 PORT 1 PORT 2 PORT 3 PORT 4 PORT 5 PORT 6 PORT TP / Fiber In TPFIPn TPFINn B Page 19

20 3.0 Pin/Ball Assignments and Signal Descriptions 3.0 Pin/Ball Assignments and Signal Descriptions 3.1 PQFP Pin Assignments The following sections show PQFP pin assignments and signal descriptions: Section 3.1.1, PQFP Pin Assignments RMII Configuration, on page 20 Section 3.1.2, PQFP Pin Assignments SMII Configuration, on page 26 Section 3.1.3, PQFP Pin Assignments SS-SMII Configuration, on page 31 Table 1 lists the acronyms and descriptions for signal types. Table 1 Signal Type Descriptions Acronym AI AO I O OD ST TS SL IP ID Description Analog Input Analog Output Input Output Open Drain Output Schmitt Triggered Input Three-State-able Output Slew-rate Limited Output Weak Internal Pull-Up Weak Internal Pull-Down PQFP Pin Assignments RMII Configuration Figure 2 and Table 2, RMII PQFP Pin List, on page 22 provide LXT9785/LXT9785E RMII PQFP pin assignments. Page 20

21 3.1 PQFP Pin Assignments Figure 2 RMII 208-Pin PQFP Assignments CRS_DV RxER6/LINKHOLD..2 TxEN TxData6_ TxData6_ REFCLK RxData5_ RxData5_ GNDIO... 9 CRS_DV RxER5/FIFOSEL TxEN TxData5_ TxData5_ RxData4_ RxData4_ CRS_DV VCCIO GNDIO RxER4/FIFOSEL TxEN TxData4_ TxData4_ MDC MDIO MDINT1_L...26 RxData3_ RxData3_ VCCIO...29 GNDIO...30 CRS_DV RxER TxEN TxData3_ TxData3_ RxData2_ RxData2_ GNDIO...38 CRS_DV RxER2/PREASEL...40 TxEN TxData2_ TxData2_ REFCLK RxData1_ RxData1_ VCCIO...47 GNDIO...48 CRS_DV RxER1/PAUSE...50 TxEN TxData1_ VCCIO GNDIO RxData6_ RxData6_ TxData7_ TxData7_ TxEN RxER CRS_DV GNDIO RxData7_ RxData7_ VCCD GNDD LED7_3_L LED7_2_L LED7_1_L LED6_3_L LED6_2_L LED6_1_L GNDIO LED5_3_L LED5_2_L LED5_1_L VCCD GNDD LED4_3_L LED4_2_L LED4_1_L SGND ModeSel ModeSel Section RESET_L PWRDWN G_FX/TP_L NC TRST_L TCK TMS TDO TDI SD SD VCCPECL GNDPECL SD SD NC NC VCCR TPFIP7 Part # FPO # LXT9785/9785E XX XXXXXXXX BSMC Rev # TPFIN GNDR TPFOP TPFON VCCT6/ TPFON TPFOP GNDR GNDT6/ TPFIN TPFIP VCCR VCCR TPFIP TPFIN GNDR TPFOP TPFON VCCT4/ TPFON TPFOP GNDR GNDT4/ TPFIN TPFIP VCCR VCCR TPFIP TPFIN GNDT2/ GNDR TPFOP TPFON VCCT2/ TPFON TPFOP GNDR TPFIN TPFIP VCCR VCCR TPFIP TPFIN GNDT0/ GNDR TPFOP TPFON VCCT0/ TPFON TPFOP GNDR TPFIN0 TxData1_ RxData0_ RxData0_ VCCIO...56 GNDIO...57 CRS_DV RxER0/MDIX...59 TxEN TxData0_ TxData0_ MDC MDIO VCCD...65 GNDD...66 MDINT0_L...67 LED3_3_L...68 LED3_2_L...69 LED3_1_L...70 LED2_3_L...71 LED2_2_L...72 LED2_1_L...73 GNDIO...74 LED1_3_L...75 LED1_2_L...76 LED1_1_L...77 VCCD...78 GNDD...79 LED0_3_L...80 LED0_2_L...81 LED0_1_L...82 AMDIX_EN...83 MDDIS...84 CFG_ CFG_ CFG_ ADD_ ADD_ ADD_ ADD_ ADD_ TxSlew_ TxSlew_ SD_2P5V...95 SD SD VCCPECL...98 GNDPECL...99 SD SD NC VCCR TPFIP Page 21

22 3.1 PQFP Pin Assignments Table 2 RMII PQFP Pin List Pin Symbol Type Reference for Full Description Pin Symbol Type Reference for Full Description 1 CRS_DV6 2 RxER6/ LINKHOLD O, TS, SL O, TS, SL, ID, I, ST Table 5 Table 5 Table 13 3 TxEN6 I, ID Table 5 4 TxData6_0 I, ID Table 5 5 TxData6_1 I, ID Table 5 6 REFCLK1 I Table 5 7 RxData5_1 O, TS, ID Table 5 8 RxData5_0 O, TS Table 5 9 GNDIO Table CRS_DV5 11 RxER5 / FIFOSEL1 O, TS, SL O, TS, SL, ID, I, ST Table 5 Table 5 Table TxEN5 I, ID Table 5 13 TxData5_0 I, ID Table 5 14 TxData5_1 I, ID Table 5 15 RxData4_1 O, TS,ID Table 5 16 RxData4_0 O, TS Table 5 17 CRS_DV4 O, TS, SL Table 5 18 VCCIO Table GNDIO Table RxER4 / FIFOSEL0 O, TS, SL, ID, I, ST Table 5 Table TxEN4 I, ID Table 5 22 TxData4_0 I, ID Table 5 23 TxData4_1 I, ID Table 5 24 MDC1 I, ST, ID Table 8 25 MDIO1 26 MDINT1_L I/O, TS, Table 8 Table 8 27 RxData3_1 O, TS, ID Table 5 28 RxData3_0 O, TS Table 5 30 GNDIO Table CRS_DV3 O, TS, SL Table 5 32 RxER3 O, TS, SL, ID Table 5 33 TxEN3 I, ID Table 5 34 TxData3_0 I, ID Table 5 35 TxData3_1 I, ID Table 5 36 RxData2_1 O, TS, ID Table 5 37 RxData2_0 O, TS Table 5 38 GNDIO Table CRS_DV2 40 RxER2 (PREASEL) O, TS, SL O, TS, SL, ID, I, ST Table 5 Table 5 Table TxEN2 I, ID Table 5 42 TxData2_0 I, ID Table 5 43 TxData2_1 I, ID Table 5 44 REFCLK0 I Table 5 45 RxData1_1 O, TS, ID Table 5 46 RxData1_0 O, TS Table 5 47 VCCIO Table GNDIO Table CRS_DV1 50 RxER1/ PAUSE O, TS, SL O, TS, SL, ID, I, ST Table 5 Table 5 51 TxEN1 I, ID Table 5 52 TxData1_0 I, ID Table 5 53 TxData1_1 I, ID Table 5 54 RxData0_1 O, TS, ID Table 5 55 RxData0_0 O, TS Table 5 56 VCCIO Table GNDIO Table CRS_DV0 O, TS, SL Table 5 29 VCCIO Table 15 Page 22

23 3.1 PQFP Pin Assignments Pin Symbol Type Reference for Full Description Pin Symbol Type Reference for Full Description 59 RxER0/ MDIX O, TS, SL, ID, I, ST Table 5 60 TxEN0 I, ID Table 5 61 TxData0_0 I, ID Table 5 62 TxData0_1 I, ID Table 5 63 MDC0 I, ST, ID Table 8 64 MDIO0 I/O, TS, Table 8 65 VCCD Table GNDD Table MDINT0_L 68 LED3_3_L 69 LED3_2_L 70 LED3_1_L 71 LED2_3_L 72 LED2_2_L SO, IP Table 8 Table 14 Table 14 Table 14 Table 14 Table LED2_1_L Table GNDIO Table LED1_3_L 76 LED1_2_L Table 14 Table LED1_1_L Table VCCD Table GNDD Table LED0_3_L 81 LED0_2_L Table 14 Table LED0_1_L Table AMDIX_EN I, ST, IP Table MDDIS I, ST, ID Table 9 85 CFG_3 I, ST, ID Table CFG_2 I, ST, ID Table CFG_1 I, ST, ID Table ADD_4 I, ST, ID Table ADD_3 I, ST, ID Table ADD_2 I, ST, ID Table ADD_1 I, ST, ID Table ADD_0 I, ST, ID Table TxSLEW_1 I, ST, ID Table TxSLEW_0 I, ST, ID Table SD_2P5V I, ST, ID Table SD0 I Table SD1 I Table VCCPECL Table GNDPECL Table SD2 I Table SD3 I Table NC Table VCCR0 Table TPFIP0 AO/AI Table TPFIN0 AO/AI Table GNDR0 Table TPFOP0 AO/AI Table TPFON0 AO/AI Table VCCT0/1 Table TPFON1 AO/AI Table TPFOP1 AO/AI Table GNDR1 Table GNDT0/1 Table TPFIN1 AO/AI Table TPFIP1 AO/AI Table VCCR1 Table VCCR2 Table TPFIP2 AO/AI Table TPFIN2 AO/AI Table GNDR2 Table TPFOP2 AO/AI Table TPFON2 AO/AI Table VCCT2/3 Table TPFON3 AO/AI Table 11 Page 23

24 3.1 PQFP Pin Assignments Pin Symbol Type Reference for Full Description Pin Symbol Type Reference for Full Description 125 TPFOP3 AO/AI Table GNDR3 Table GNDT2/3 Table TPFIN3 AO/AI Table TPFIP3 AO/AI Table VCCR3 Table VCCR4 Table TPFIP4 AO/AI Table TPFIN4 AO/AI Table GNDT4/5 Table GNDR4 Table TPFOP4 AO/AI Table TPFON4 AO/AI Table VCCT4/5 Table TPFON5 AO/AI Table TPFOP5 AO/AI Table GNDR5 Table TPFIN5 AO/AI Table TPFIP5 AO/AI Table VCCR5 Table VCCR6 Table TPFIP6 AO/AI Table TPFIN6 AO/AI Table GNDT6/7 Table GNDR6 Table TPFOP6 AO/AI Table TPFON6 AO/AI Table VCCT6/7 Table TPFON7 AO/AI Table TPFOP7 AO/AI Table GNDR7 Table TPFIN7 AO/AI Table TPFIP7 AO/AI Table VCCR7 Table NC Table NC Table SD4 I Table SD5 I Table GNDPECL Table VCCPECL Table SD6 I Table SD7 I Table TDI I, ST, IP Table TDO O, TS Table TMS I, ST, IP Table TCK I, ST, ID Table TRST_L I, ST, IP Table NC Table G_FX/TP_L I, ST, ID Table PWRDWN I, ST, ID Table RESET_L I, ST, IP Table SECTION I, ST, ID Table ModeSel0 I, ST, ID Table ModeSel1 I, ST, ID Table SGND Table LED4_1_L 181 LED4_2_L Table 14 Table LED4_3_L Table GNDD Table VCCD Table LED5_1_L 186 LED5_2_L Table 14 Table LED5_3_L Table GNDIO Table LED6_1_L 190 LED6_2_L 191 LED6_3_L 192 LED7_1_L 193 LED7_2_L Table 14 Table 14 Table 14 Table 14 Table 14 Page 24

25 3.1 PQFP Pin Assignments Pin Symbol Type Reference for Full Description 194 LED7_3_L Table GNDD Table VCCD Table RxData7_1 O, TS, ID Table RxData7_0 O, TS Table GNDIO Table CRS_DV7 O, TS, SL Table RxER7 O, TS, SL, ID Table TxEN7 I, ID Table TxData7_0 I, ID Table TxData7_1 I, ID Table RxData6_1 O, TS, ID Table RxData6_0 O, TS Table GNDIO Table VCCIO Table 15 Page 25

26 3.1 PQFP Pin Assignments PQFP Pin Assignments SMII Configuration Figure 3 and Table 3, SMII PQFP Pin List, on page 27 provide the LXT9785/LXT9785E SMII PQFP pin assignments. Figure 3 SMII 208-Pin PQFP Assignments NC... 1 NC/LINKHOLD... 2 NC... 3 TxData NC... 5 REFCLK NC... 7 RxData GNDIO... 9 NC FIFOSEL NC TxData NC NC RxData NC VCCIO GNDIO FIFOSEL NC TxData NC MDC MDIO MDINT1_L NC RxData VCCIO GNDIO NC NC NC TxData SYNC NC RxData GNDIO NC PREASEL NC TxData NC REFCLK NC RxData VCCIO GNDIO NC PAUSE NC TxData VCCIO GNDIO RxData NC SYNC TxData NC NC NC GNDIO RxData NC VCCD GNDD LED7_3_L LED7_2_L LED7_1_L LED6_3_L LED6_2_L LED6_1_L GNDIO LED5_3_L LED5_2_L LED5_1_L VCCD GNDD LED4_3_L LED4_2_L LED4_1_L SGND ModeSel_ ModeSel_ Section RESET_L PWRDWN G_FX/TP_L NC TRST_L TCK TMS TDO TDI SD SD VCCPECL GNDPECL SD SD NC NC VCCR TPFIP7 Part # FPO # LXT9785/9785E XX XXXXXXXX BSMC Rev # TPFIN GNDR TPFOP TPFON VCCT6/ TPFON TPFOP GNDR GNDT6/ TPFIN TPFIP VCCR VCCR TPFIP TPFIN GNDR TPFOP TPFON VCCT4/ TPFON TPFOP GNDR GNDT4/ TPFIN TPFIP VCCR VCCR TPFIP TPFIN GNDT2/ GNDR TPFOP TPFON VCCT2/ TPFON TPFOP GNDR TPFIN TPFIP VCCR VCCR TPFIP TPFIN GNDT0/ GNDR TPFOP TPFON VCCT0/ TPFON TPFOP GNDR TPFIN0 NC NC RxData VCCIO GNDIO NC MDIX NC TxData NC MDC MDIO VCCD GNDD MDINT0_L LED3_3_L LED3_2_L LED3_1_L LED2_3_L LED2_2_L LED2_1_L GNDIO LED1_3_L LED1_2_L LED1_1_L VCCD GNDD LED0_3_L LED0_2_L LED0_1_L AMDIX_EN MDDIS CFG_ CFG_ CFG_ ADD_ ADD_ ADD_ ADD_ ADD_ TxSlew_ TxSlew_ SD_2P5V SD SD VCCPECL GNDPECL SD SD NC VCCR TPFIP Page 26

27 3.1 PQFP Pin Assignments Table 3 SMII PQFP Pin List Pin Symbol Type 1 Reference for Full Description 1 NC Table 16 2 NC/ LINKHOLD I, ID, Table 16 Table 13 3 NC Table 16 4 TxData6 I, ID Table 6 5 NC Table 16 6 REFCLK1 I Table 5 7 NC Table 16 8 RxData5 O, TS Table 6 9 GNDIO Table NC Table FIFOSEL1 I, ID, ST Table NC Table TxData5 I, ID Table 6 14 NC Table NC Table RxData4 O, TS Table 6 17 NC Table VCCIO Table GNDIO Table FIFOSEL0 I, ID, ST Table NC I, ID Table TxData4 I, ID Table 6 23 NC Table MDC1 I, ST, ID Table 9 25 MDIO1 26 MDINT1_L I/O, TS, OD, TS, SL, IP Table 9 Table 9 27 NC Table RxData3 O, TS Table 6 29 VCCIO Table GNDIO Table NC Table NC Table NC Table TxData3 I, ID Table 6 Pin Symbol Type 1 Reference for Full Description 35 SYNC0 I, ID Table 7 36 NC Table RxData2 O, TS Table 6 38 GNDIO Table NC Table PREASEL I, ID, ST Table NC Table TxData2 I, ID Table 6 43 NC Table REFCLK0 I Table 5 45 NC Table RxData1 O, TS Table 6 47 VCCIO Table GNDIO Table NC Table PAUSE I, ID, ST Table NC Table TxData1 I, ID Table 6 53 NC Table NC Table RxData0 O, TS Table 6 56 VCCIO Table GNDIO Table NC Table MDIX I, ID, ST Table NC Table TxData0 I, ID Table 6 62 NC Table MDC0 I, ST, ID Table 9 64 MDIO0 I/O, TS, Table 9 65 VCCD Table GNDD Table MDINT0_L OD, TS, SL, IP Table 9 Page 27

28 3.1 PQFP Pin Assignments Pin Symbol Type 1 Reference for Full Description 68 LED3_3_L 69 LED3_2_L 70 LED3_1_L 71 LED2_3_L 72 LED2_2_L 73 LED2_1_L OD, TS, SO, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP Table 14 Table 14 Table 14 Table 14 Table 14 Table GNDIO Table LED1_3_L 76 LED1_2_L 77 LED1_1_L OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP Table 14 Table 14 Table VCCD Table GNDD Table LED0_3_L 81 LED0_2_L 82 LED0_1_L OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP Table 14 Table 14 Table AMDIX_EN I, ST, IP Table MDDIS I, ST, ID Table 8 85 CFG_3 I, ST, ID Table CFG_2 I, ST, ID Table CFG_1 I, ST, ID Table ADD_4 I, ST, ID Table ADD_3 I, ST, ID Table ADD_2 I, ST, ID Table ADD_1 I, ST, ID Table 13 Pin Symbol Type 1 Reference for Full Description 92 ADD_0 I, ST, ID Table TxSLEW_1 I, ST, ID Table TxSLEW_0 I, ST, ID Table SD_2P5V I, ST, ID Table SD0 I Table SD1 I Table VCCPECL Table GNDPECL Table SD2 I Table SD3 I Table NC Table VCCR0 Table TPFIP0 AI/AO Table TPFIN0 AI/AO Table GNDR0 Table TPFOP0 AO/AI Table TPFON0 AO/AI Table VCCT0/1 Table TPFON1 AO/AI Table TPFOP1 AO/AI Table GNDR1 Table GNDT0/1 Table TPFIN1 AI/AO Table TPFIP1 AI/AO Table VCCR1 Table VCCR2 Table TPFIP2 AI/AO Table TPFIN2 AI/AO Table GNDR2 Table TPFOP2 AO/AI Table TPFON2 AO/AI Table VCCT2/3 Table TPFON3 AO/AI Table TPFOP3 AO/AI Table GNDR3 Table GNDT2/3 Table TPFIN3 AI/AO Table TPFIP3 AI/AO Table 11 Page 28