Figure 2.2. Block Diagram of Carry Look-ahead Adder

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1 Volume 115 No , ISSN: (printed version); ISSN: (on-line version) url: COMPARISON OF POWER DISSIPATION OF ALU BY USING DIFFERENT TECHNOLOGIES ijpam.eu K.Hari Kishore 1, P. Sri Vidhya 2, A. Bhavana 3, O. Venkata Krishna 4 1,2,3,4 Department of ECE, K L University, Vaddeswaram, Guntur, A.P, India 1 kakarla.harikishore@kluniversity.in Abstract: Arithmetic and Logic Unit (ALU) is one of the crucial and key component of any embedded system. At present, power dissipation is the main design specification for any electronic devices. ALU has a number of different functional units, of which, the adder unit is our design concern. In order to minimise the power consumption without compromising speed we go for comparison between two types of adders namely ripple carry adder and carry look-ahead adder circuits implemented in technologies mentioned below which meets with our design criteria. Here in this paper a comparative analysis is done among adders designed by using convectional CMOS technology, Hybrid and GDI (Gate Diffusion Input) technologies. Keywords: ALU, CMOS VLSI, Adders, GDI, Power Dissipation comparisons, Ripple carry adder, carry look ahead adder 1. Introduction An ALU is a component of CPU that performs complex mathematical operations. As the name indicates ALU performs arithmetic and logical operations. Arithmetic operations include addition, subtraction. multiplication and division. But generally we prefer multiply and accumulator for multiplication purpose so we should mainly concentrate on adders. so in our paper we have designed paper by using different technologies such as cmos technology,pass transistor technology, hybrid technology and gate diffusion input technology and also we have seen which type of adders is best i.e., whether it is ripple carry adder,carry look ahead adder,carry select adder. 2. Previous methodology Ripple carry adder : In the below figure 2.1,we can observe that to get carry output there will be a delay of time because to get the present carry it should depend on previous carry which is time consuming and there will be more delay if we use this type of adder. so it is better to prefer other type of adder rather than ripple carry adder if we consider power dissipation and delay as the major parameters while designing ALU. Figure 2.1.Block Diagram of Ripple Carry Adder 3. Proposed technique In ripple carry adder, if the delay is more, the power consumption will also be more which is a major design issue. So we go for carry look ahead adder where most significant bit s carry in doesn t depend on least significant bit s carryout and hence both delay and power are considerably reduced. carry look ahead adder (CLA) is considered as the best type of adder when compared with RCA in terms of delay and power dissipation.so it is best to consider CLA rather than RCA. CLA is designed in such a way that the present carry will not depend on previous carry but it will depend only on the input carry and the present carry can be calculated from the input carry by some mathematical calculations where we consider two signals known as generate and propagate which are represented gi and pi. But while differentiating RCA and CLA, the delay and power dissipation for CLA is less but chip size is greater when compared with RCA. Figure 2.2. Block Diagram of Carry Look-ahead Adder 399

2 C 1=G 0+P 0C 0 adders ; i=0 using different technologies such as CMOS C 2=G 1+P 1G 0 +P 1P 0C 0 technology ; i=1 and pass transistor technology C 3=G 2+P 2G 1+P 2P 1G 0+P 2P 1P 0C 0 ; i=2 C 4=G 3+ P 3G 2+P 3P 2G 1+P 3P 2P 1G 0+P 3P 2P 1P 0C 0 ; i=3 we have also seen whether what will happen if we implement adders in different technologies like cmos technology,pass transistor technology,hybrid and GDI technology and have seen which technology is best for the physical design of the adder where we have considered power dissipation as the crucial parameter. we have implemented these adders using microwind tool and we have also implemented ALU operations by using software tool i.e.,xilinx and implemented by using Verilog. 4. Results and discussion Figure 4.3. Design of full adder using CMOS technology In figure 4.3 we have designed adder which is veryimportant component in ALU and is designed byusing CMOS technology in micro wind tool and have seen the power consumption. Figure 4.1. shows the subtraction operation As in the figure op code is 3'h1 A[15:0]-16'h003f, B[15:0]-16'h007f then Y[15:0]-16'hffc0 and the flags such as zero flag-active LOW, carry flag-active HIGH,negative flag-active HIGH,overflow flag -Active ZERO performed by the ALU. Figure 4.4. Design of full adder using GDI technology In figure 4.4 we have designed adder which is very important component in ALU and is designed by using GDI (gate diffusion input) technology in micro wind tool and have seen the power consumptionand have observed that the power consumption by using GDI technique is less when compared with cmos technology and Hybrid technology. Figure 4.2. shows the addition operation done by ALU. This ALU has inputs with op code-3'h0,a[15:0]- 16'h007f.B[15:0]-16'h003f then the Y[15:0]-16'h00be and the carry flag, overflow flag and zero flag are active LOW.As we know that the main part of ALU is adder, we have calculated the power consumed by 400

3 Figure 4.5. Design of Full Adder using Hybrid Technology. In figure 4.5 we have designed adder which is very important component in ALU and is designed by using Hybrid technology in micro wind tool and have seen the power consumptionand have observed that the power consumption by using GDI technique is less when compared with cmos technology Table 4.1 Comparison of power consumptions for different technologies S.no Type of transistors /technology From the table 4.1 we can observe that power consumption of the adders by using GDI technology is less ie.,4.878microwattswhen compared with hybrid technology ie.,9.62 microwatts and cmos technology adders ie., microwatts. 5. Conclusion In this paper we have designed the ALU by using rca once and next with carry look ahead adder and observed that by using ripple carry adder there is a carry delay but by using carry look ahead adder we have seen that the output delay is very less compared to ripple carry adder and also power consumption is less when compared to ripple carry adder. Additionally to this we have designed adders in different technologies such as CMOS technology and pass transistor technology analysed power dissipation in both cases and came to a conclusion that it is better to design a carry look ahead adder in the pass transistor logic than CMOS logic will be lost just there will be change in state and hence power dissipation can be reduced. References Power consumed (microwatts) 1. CMOS technology Hybrid GDI [1] M. Morris Mano, Register transfer and Micro operations, in Computer System Architecture, 3rd ed. Pearson, India, pp [2] S. Salivahanan and S. Arvazhagan, Digital Circuits and Design, 3rd ed. Vikas publishing, India, pp [3] KanikaKaur and Arti Noor (2011,May). Strategies and Methodologies for low power VLSI designs: A review. International Journal of Advances in Engineering & Technology.[online]. ISSN: pp [4] Performance Comparison of Pass Transistor and CMOS Logic Configuration based De-Multiplexers by Arun Pratap Singh Rathod, Praveen Lakhera, A. K. Baliga, Poornima Mittal and Brijesh Kumar IEEE. [5] Korraprolu Brahma Reddy, K Hari Kishore, A Mixed Approach for Power Dissipation Reduction in Nanometer CMOS VLSI circuits, International Journal of Applied Engineering Research, ISSN Volume 9, Number 18, pp , July [6] Samuel L. SanGregory, Raymond E. Siferd, Charles Brother, and David Gallagher, A fast, low-power logarithm approximation with CMOS VLSI implementation, IEEE Midwest Symposium on Circuits and Systems, August [7] M. D. Ciletti and M. Morris Mano: Digital design, 4th Ed., Pearson, India, [8] Bandlamoodi Sravani, K Hari Kishore, An FPGA Implementation of Phase Locked Loop (PLL), International Journal of Applied Engineering Research, ISSN , Volume 10, pp , August 2015 [9] P Bala Gopal, K Hari Kishore, B.Praveen Kittu An FPGA Implementation of On Chip UART Testing with BIST Techniques, International Journal of Applied Engineering Research, ISSN , Volume 10, pp , August 2015 [10] P. SIVA SANKAR, A Secure and Fast Authentication implementationbetween the Entities using Trust Aware Algorithm International Innovative Research Journal of Engineering and Technology, ISSN NO: , Vol.2, no.1, pp.34-40, sep [11] M.A Srivatsav, K Hari Kishore Functional Coverage for DDR4 Memory Controller, International Journal of Applied Engineering Research, ISSN , Volume 10, pp , June 2015 [12] K Hari Kishosre, CVRN Aswin Kumar, T Vijay Srinivas, GV Govardhan, Ch Naga Pavan Kumar, R Venkatesh Design and Analysis of High Efficient UART on Spartran-6 and Virtex-7 Devices, International Journal of Applied 401

4 Engineering Research, ISSN , Volume 10, pp , June 2015 [13] K Bindu Bhargavi, K Hari Kishore Low Power BIST on Memory Interface Logic, International Journal of Applied Engineering Research, ISSN , Volume 10, pp , May 2015 [14] Avinash Yadlapati, Dr.Hari Kishore Kakarla, An Advanced AXI Protocol Verification using Verilog HDL, Wulfenia Journal, ISSN: X, Volume 22, pp , April [15] A.Sivannarayana, K.HariKishore, Design and Modeling of Modulo Multipliers Using RNS, International Journal of Innovative Technology and Exploring Engineering, ISSN: , Volume-3, Issue-2, July [16] T. Padmapriya and V.Saminadan, Handoff Decision for Multi-user Multiclass Traffic in MIMO-LTE-A Networks, 2nd International Conference on Intelligent Computing, Communication & Convergence (ICCC-2016) Elsevier - PROCEDIA OF COMPUTER SCIENCE, vol. 92, pp: , August

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