Efficient Implementation of Combinational Circuits Using PTL

Transcription

1 Efficient Implementation of Combinational Circuits Using PTL S. Kiruthiga, Assistant Professor, Sri Krishna College of Technology. S. Vaishnavi, Assistant Professor, Sri Krishna College of Technology. S. Vimal Raj, Assistant Professor, Sri Krishna College of Technology. Abstract--- CMOS circuit based applications are widely used in markets now a days. CMOS logic implementation requires larger number of transistor compared to other logic families in spite of its several salient features. This research paper focuses on implementing basic combinational circuits like multiplexer and priority encoder using pass transistor logic(ptl). The key feature of PTL is reduction of transistor based on redundancies. The proposed Mux, priority encoder and 1 bit magnitude comparator compromises in transistor count, reduction in supply voltage consumption, less inter connects, Delay minimization and power reduction in comparison with CMOS implementation. Keywords--- MUX, Priority Encoder, 1 Bit Magnitude Comparator, CMOS, PTL. I. Introduction Now a days Microcontrollers, Microprocessors, Static Ram and several other digital circuits employ Complementary Metal Oxide Semiconductor(CMOS) Circuit design since those circuits are power efficient and having better switching activities[1]. Also CMOS Design has important features like high noise immunity and less static power consumption [2]. But the problem in CMOS Circuit design is that the design will contain lot of transistors which in turn increases the chip area. As today every device is turning to potable, it is important to have design which contains less number of transistors in a design which leads to lesser area. Pass Transistor logic gives a good solution in reducing the transistor count. It is achieved by eliminating the redundant transistor while making different logic gates and other logic operation. Pass transistors requires less number of transistor, runs faster compared to CMOS transistors. And most important thing is requires less power compared to the power drawn by CMOS logic. As it is understood, Power is the predominant factor in optimization of any design [3]. Many adders, mux, demux, encoder, decoder and other combinational circuits are designed using many technology with wide range of transistors used. In one of the existing methods adders are constructed using transmission gates where the number of gates forming the circuit is very high which leads to more area. When the area gets increased the compactness inside the IC which indicates maximum capacity of devices to be in built with in an chip gets reduced. Due to the increase in size of the chip, it cannot be brought into the market with the leading competitors all over the world in the present. Hence a proper tradeoff is required between area, power, delay, etc. The design of combinational circuits like 1-bit full adder, 1-bit hybrid adders has much complexity where delay plays a major role which affects the entire system performance compared to the existing method. Design of circuits using CMOS also generallyrequires more memory where a normal half adder requires more than more than 15 transistors which is not needed in the upcoming future era. Interconnect complexities also gets high when the number of transistors gets increased. Floor-planning and routing becomes difficult when it comes to backend design of the circuit. Earlier, in submicron technology, 8, 16, 32 bit adders are designed using CMOS and transmission gates. The performance comparison shows that transmission gates are better which has the design with less number of transistors and less delay[4]. Further implementations show that adder construction using CMOS, Transmission Gates and Complementary Pass Transistor Logic. It shows that again transmission gates are better than other two implementations. Various technologies have been used for the comparison of energy, delay and area. Using CMOS only PMOS and NMOS is used for construction of circuit, by using CPL complementary part of the inputs are given and complementary part of the output is generated. In Transmission Gates combination of NMOS and PMOS in parallel manner gives the output based on the control signal inputs forced into the gates. By the usage of Transmission Gates speed of operations can be made better which in turn increases the speed of the end product chip. Power dissipation is very high in static and dynamic CMOS wherein gates are little reduced by usage of transmission gates. CMOS circuits cannot limit to the certainty of ceramic packages too. 32 transistors are needed in general to construct 1- bit adder using Complementary Pass Transistor Logic. 28 transistors are needed in general to ISSN X 331

2 construct 1- bit adder using CMOS logic. 20 transistors are needed in general to construct 1- bit adder using Complementary Pass Transistor Logic which proves that this technique is efficient [5] The research paper is organized as few sections including this introduction section I.Section II explains the CMOS implementation of Multiplexers(both 2:1 and 4:1), Priority encoder, 1 bit Magnitude comparator, Section III introduces the Pass Transistor logic implementation of Multiplexer, Priority encoder, 1 bit Magnitude comparator. Section IV summarizes the few comparison analysis came out from previous section. Finally section V concludes with result. II. CMOS Logic Implementation A CMOS circuit is having a unique feature that is duality which presents between its PMOS transistors and NMOS transistors.in CMOS circuits, a path is created either from the output to power source or from output to ground. This can be achieved only when the set of all paths from output to the voltage source should be the complement of the set of all paths from output to ground. And hence always the NMOS will be in parallel combination with PMOS are in series and NMOS will be in series combination with PMOS are in parallel. The dynamic power consumption is given by the formula Where C is the Load Capacitance. V is the supply voltage. f is the clock frequency. Figure 1: CMOS based 4X2 Priority Encoder In CMOS circuit design the power dissipation in PMOS network is half of the total power dissipation. During discharging phase of clock cycle the heat is dissipated in the output load. Based on switching activity reduction and input voltage scaling methods many power reduction techniques have been proposed in CMOS design. But in most of the methods the energy drawn from the input supply is dissipated in the form of heat. ISSN X 332

3 Figure 2: CMOS based 4X1 MUX Figure 3: CMOS based 2X1 MUX ISSN X 333

4 III. Figure 4: CMOS based 1 Bit Magnitude Comparator Pass Transistor Logic Implementation The Pass transistor logic has many advantages like the usage of few transistors, small input capacitance, less wiring overhead. Hardware reduction is the final output of using the Pass transistor logic. Delay also plays a major role in many of the complex circuits which leads to failure of chips at times.minimization of delay and increase of speed are some of the parameters that can be achieved using the pass transistor logic. When the logic implementation of certain circuits is very complex, sometimes buffer insertion may be required. Many conditions and criteria also posed to insert buffer in the circuits during signal restoration. Although the problem is tend to be NP-Hard many linear methods can be used to solve this issues[6]. A periodic clock signal drives Pass transistors and depending on the input signal V in, the parasitic capacitance C x gets charged up or discharged. The capacitance of pass transistors charged to logic high when it receives clk = 1 and capacitance discharged to logic low when it receives clk=0.[7] [8]. Pass transistors use NMOS devices for logic implementation. NMOS devices are designed in such a way that it is good in passing a 0 and poor in passing the voltage from supply voltage V DD. When the node is connected to logic high the pass transistor will get charged to V DD V TN (V S ) where VVs = VDD (VTN0 + g 2φf + Vs 2φf ) ISSN X 334

5 Figure 5: Pass Transistor based 4X2 Priority Encoder Priority encoder is categorized under the parallel-prefix computations and it is one of the basic digital circuits. Its main function includes mediation among various stages of different priority and it gives access to a shared resources. In general, the bit which is provided the highest priority and its incrementing bits are selected and all the other lower priority bits are discarded. The priority encoder has 2 N inputs and N outputs. Time delay is calculated by the formula Td= (T f +T r )/2 = (K*C L /(β n *VDD) + K*C L /(β p *V DD ). Figure 6: Pass Transistor based 4X1 MUX ISSN X 335

6 Figure 7: Pass Transistor based 2X1 MUX 4:1 MUX is constructed using two 2:1 MUX. Select lines based on the input requirements are made. Input reordering is incorporated in 4:1 MUX where the pass transistors are connected in such a manner that proper output is selected based on the selection lines and with few inputs ordering properly. Pass transistors work in such a way that the source of pass transistors is connected to the respective inputs and drain terminal of the pass transistor is connected to the output or to the other stage of the circuit. The input terminals of pass transistor is also connected to the select lines in case of MUX by which Pass transistors make the circuit simple and reduces complexity compared to the MUX created using CMOS. Input reordering is also one of the optimum method to reduce the power consumption of the circuit as well as to reduce the delay produced during the working of the circuit. The internal parasitic capacitance can also be reduced because of this reduced terminals and interconnections. Figure 8: Pass Transistor based 1 bit Magnitude Comparator ISSN X 336

7 Comparators are widely used in many analog to digital converters as well as in many applications like PLL. High speed comparators can be created using pass transistor logic where area becomes quite small in the designing. Power delay product also becomes less using pass transistor logic. Output voltage swing is less which produce more or less stable output voltage without distortions. Shutdown techniques also proposed wherein when the lower bits of the inputs are compared higher bits are kept in idle state. When the higher bits of the inputs are compared lower bits are kept in idle state. By this way the extra power consumed can be reduced and cooling techniques for many circuits need not be proposed. Serial architectures may be used to pose the inputs into the circuit where only few bits can be given as input. Serial architectures can be combined together to feed the long chain inputs. For better efficiency of power consumption an auxiliary power measurement circuit construction can be made to measure the power efficiency. The pass transistors operates in linear region and hence it is considered as resistance RR = 1 kk(vvvvvv VVVVVV ) aa /2at Vgs=(Vdd-Vtn)/2 IV. Simulation Results The transistor count, power consumption and the delay of the above circuits are found out by simulation. The comparison for CMOS Logic and Pass transistor logic implementation of circuits are noted in tabular column. Table I: Parameters Comparison Circuit Logic No of Transistors Power(W) Delay (ns) 2:1 mux CMOS e pass e :1 mux CMOS e pass e x2 priority encoder CMOS e pass e bit comparator CMOS e pass e A. Graphical Comparison of Parameters for CMOS Logic and Pass Transistor Logic Implementation ISSN X 337

8 V. Conclusion and Future Wok In this paper pass transistor logic based mux, priority encoder and magnitude comparator are designed and simulated. The CMOS logic implementation is also resented and simulated. The simulation results shows that the pass transistor based digital circuit implementation provides better results in reduction in transistor count, delay, power consumption and reduction in interconnect length compared to CMOS logic implementation. The reduction in transistor count will lead to lesser chip area which is the most needed criteria for many applications. Basic digital circuits can be implemented with Pass transistors. The pass transistors can be evolved to have less power consumption by making threshold voltage of pass transistor as lesser. References [1] Chandrakasan, A.P., Sheng, S. and Brodersen, R.W. Low-power CMOS digital design. IEICE Transactions on Electronics 75 (4) (1992) [2] Ding, L. and Mazumder, P. A novel technique to improve noise immunity of CMOS dynamic logic circuits. Proceedings of the 41st annual Conference on Design Automation, 2004, [3] Zimmermann, R. and Fichtner, W. Low-power logic styles: CMOS versus pass-transistor logic. IEEE journal of solid-state circuits 32 (7) (1997) [4] Baliga, A. and Yagain, D. Design of High speed adders using CMOS and Transmission gates in Submicron Technology: a Comparative Study. 4th International Conference on Emerging Trends in Engineering and Technology (ICETET), 2011, [5] Sharma, S. and Soni, G. Comparison analysis of FinFET based 1-bit full adder cell implemented using different logic styles at 10, 22 and 32NM. International Conference on Energy Efficient Technologies for Sustainability (ICEETS), 2016, [6] Zhou, H. and Aziz, A. Buffer minimization in pass transistor logic. IEEE transactions on computer-aided design of integrated circuits and systems 20 (5) (2001) [7] Pedron, C. and Stauffer, A. Analysis and synthesis of combinational pass transistor circuits. IEEE transactions on computer-aided design of integrated circuits and systems 7 (7) (1988) [8] Pucknell, D.A. and Eshraghian, K. Basic VLSI design: systems and circuits. Prentice-Hall, Inc., [9] Ciletti, M.D. and Morris Mano, M. Digital design, 4th Ed., Pearson, India, [10] Gao, L. High performance Complementary Pass transistor Logic full adder. International Conference on Electronic and Mechanical Engineering and Information Technology (EMEIT), 2011, [11] Kumar, R. and Pandey, V.K. A New 5-Transistor XOR-XNOR circuit based on the pass transistor logic. In World Congress on Information and Communication Technologies (WICT), 2011, [12] Ramakrishnan, L.N., Chakkaravarthy, M., Manchanda, A.S., Borowczak, M. and Vemuri, R. SDMLp: On the use of complementary Pass transistor Logic for design of DPA resistant circuits. IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), 2012, [13] Berg, Y. and Azadmehr, M. Novel ultra low-voltage and high-speed CMOS pass transistor logic. Faible Tension Faible Consommation (FTFC), 2012, 1-4. ISSN X 338