A Hierarchical ZVS Battery Equalizer Based on Bipolar CCM Buck-Boost Units

Transcription

1 F. Peg, H. Wag*, ad L. u, "A hierarchical ZVS battery equalizer based o bipolar CCM buck-boost uits," i Proc. IEEE Eergy Coversio Cogress ad Expositio (ECCE), Portlad, OR, Sept pp A Hierarchical ZVS Battery Equalizer Based o Bipolar CCM Buck-Boost Uits Faxiag Peg, Studet Meber, IEEE, Haoyu Wag, Meber, IEEE, ad Liag u School of Iforatio Sciece ad Techology ShaghaiTech Uiversity, Shaghai, Chia waghy.shaghaitech@gail.co Abstract Covetioal battery equalizers rely o uipolar cotiuous-coductio ode of power electroic coverters. This causes substatial eergy losses durig the switchig trasitios. To cope with this issue, this paper proposes a ovel hierarchical battery equalizer based o bipolar cotiuouscoductio ode buck-boost uits. I the proposed structure, the iductor curret is cotrolled to eter ito the egative regio at the ed of each switchig period. Thus, the body diode of power MOSFET provides a freewheelig path for the iductor curret durig the dead bad. This esures zerovoltage switchig of both power MOSFETs. Therefore, the switchig losses are sigificatly reduced. Meawhile, the itegral of the iductor egative curret is precisely cotrolled to iiize the circulatig curret. This guaratees both iiized coductio losses ad suitable equalizatio speed. The operatio priciple ad cotrol strategy of the equalizer are aalyzed. The copariso of equalizatio speed betwee differet equalizer is preseted. A experietal prototype to balace four series-coected Lithiu-io battery cells is ipleeted. Both siulatio ad experietal results validate the fuctioality ad aalysis of this battery equalizer. Keywords battery equalizer, bipolar cotiuous-coductio ode (CCM), buck-boost coverter, Lithiu-io battery, zerovoltage switchig (ZVS). I. ITRODUCTIO I high power applicatios such as electric vehicles, the Lithiu-io batteries ust be coected i series to boost the power capability [1]-[3]. Due to the aufacturig ad eviroetal variaces, the iteral ipedace of each battery cell i the battery strig ay vary. This causes the isatch of cell voltages whe the battery strig is charged or discharged [4]-[6]. Thus, certai cells ay be overcharged or depleted, which leads to the decay of battery capacity ad lifetie, ad eve icurs safety issues (e.g. fire or explosio) [7]-[10]. Therefore, battery equalizers are required to effectively itigate cell isatch issues, ad to iprove the syste perforace. Differet battery equalizatio techiques have bee reported i the literature. Those techiques ca be divided ito passive ethods ad active ethods. The passive ethods usually have a resistor paralleled with each battery cell. The resistor cosues the excessive eergy of the overcharged battery cells [1]. These ethods are easy to ipleet ad are featured with low cost ad sall size. However, the power dissipatio is large which degrades the efficiecy ad causes theral issues to the battery aageet syste. I copariso with the passive ethods, the active ethods are preferable due to their advatages of high efficiecy ad fast equalizig speed. I [4], the switchedcapacitor based equalizer is proposed. This techique provides a direct equalizatio path betwee two arbitrary cells. However, the equalizatio speed decays whe the battery cell voltage differece is trivial. The referece [6] uses a bidirectioal Fly-back coverter to trasfer the eergy of the overcharged battery cells to the battery strig. While a coplicated cotrol algorith is required to esure robust syste perforace. Soe trasforer based equalizers are proposed i [7]-[9]. The techique proposed i [7] is based o a ulti-secodary widigs trasforer. This ethod achieves relatively fast equalizatio speed, but it is ipractical to desig the trasforer whe the cell uber scales up. I order to iprove the equalizatio speed, the hierarchical equalizatio architecture is proposed i [11]-[14]. I [1], a hierarchical equalizatio architecture based o buck-boost uits is proposed. However, the equalizatio uit operates at uipolar CCM, substatial switchig loss occurs durig the switchig trasitios. This jeopardizes the syste efficiecy, especially i high-frequecy scearios. Moreover, all equalizer uits operate siultaeously, while the C 1 C C 3 C 4 C i C i+1 C -3 C - C -1 C Level_1 Level_ Level_3 Level_ Equalizer Uit Fig. 1 The hierarchical equalizer scheatic based o buck-boost coverter /18/$ IEEE 10

2 s w1 DTs Td Ts Cell S w Cell S w s w Q (a) (b) i cell1 Cell S w Cell S w i cell V DS1 V C1+V C (c) (d) Fig. 3 The equivalet circuit of four odes. (a) Mode 1; (b) Mode ; (c) Mode 3; (d) Mode 4. V C1+V C V DS ' t t 0 t 1 t t 3 t 0 M 1 M M 3 M 4 Fig. The key wavefors of the basic equalizatio uit. optiizatio betwee differet levels is ot addressed. This is ot preferred as it ay cause the overcharged cells eve further charged at the begiig of the equalizatio process. To boost the coversio efficiecy ad to optiize the equalizatio strategy, the paper presets a hierarchical battery voltage equalizer based o buck-boost uits operatig at bipolar CCM. The scheatic of the proposed equalizer with series-coected cells is plotted i Fig. 1. As show, each uit is cofigured by a odified buck-boost circuit. Differet uits are placed at differet levels to provide flexible balacig paths for correspodig cells or strigs. The equalizer ca realize bidirectioal eergy flow. Furtherore, all the power MOSFETs are tured o with zero voltage. This reduces the switchig losses rearkably. A advaced cotrol strategy is itroduced to optiize both the coversio efficiecy ad the equalizatio speed. II. OPERATIO PRICIPLES The proposed equalizer ca trasfer eergy betwee two adjacet battery cells or strigs via the basic uits located at differet levels. I order to siplify the aalysis, we focus o oe basic equalizatio uit to iterpret the operatio odes. The key wavefors of the basic equalizatio uit at steady state are show i Fig.. Soe assuptios are ade as follows, 1. The voltage of is higher tha Cell (V C1 > V C);. The voltage of the cell ca be see as a costat durig a specific switchig period; 3. The forward voltage drops of body diodes of MOSFETs are cosidered, while the equivalet series resistace (ESR) is igored; 4. All the equalizatio uits (odified buck-boost coverter) operate i bipolar CCM. ad S w tur o ad off copleetarily followig the buck-boost switchig patter. The operatio of the equalizatio uit ca be divided ito four odes. Mode 1 [t 0-t 1): The equivalet circuit of ode 1 is show i Fig. 3 (a). Whe turs o, Mode 1 starts. I Mode 1, the voltage of (V C1) is applied to the iductor (), ad the iductor curret () builds up. is equal to the equalizatio curret i this sub-iterval. Sice the cell voltage ca be see as a costat, the iductor curret icreases liearly. The discharge curret of the also icreases liearly. Thus, the excessive eergy of the is trasferred to. Mode [t 1-t ): The equivalet circuit of ode is show i Fig. 3 (b). Whe turs off, Mode starts. Sice could ot chage abruptly, the body diode of S w provides a freewheelig path. Therefore, the body diode coducts before the coductio of MOSFET chael, which establishes the zero voltage turig-o coditio for S w. I this ode, the iductor is paralleled with Cell via S w. Thus, the polarity of the iductor voltage is iverted ad decreases liearly. Mode 3[t -t 3): The equivalet circuit of ode 3 is show i Fig. 3 (c). Whe S w turs o, Mode 3 starts. cotiues to decrease liearly. Thus, the stored eergy i the iductor is trasferred to the target cell (Cell ). The charge curret of Cell also decreases siultaeously. Cosequetly, the draisource voltage of (v ds1) is claped to the su of the cell voltages. Mode 4[t 3-t 0 ): The equivalet circuit of ode 4 is show i Fig. 3 (d). Whe S w turs off, Mode 4 starts. The voltage stresses of the switches are derived as, v = V + V + V v = V + V + V (1) ds1 C1 C D ds C1 C D Durig Modes ad 3, the aalytical expressio of the iductor curret is derived as, V V + V V i () t = DT ( T ) ( t t ) () C1 C D C L11 s d L11 L11 L11 III. DESIG COSIDERATIOS A. The Coditio of Bipolar CCM I order to achieve high coversio efficiecy, the equalizer is desiged to operate at the bipolar CCM ad all the power MOSFETs are tured o at zero voltage. Therefore, durig Mode 3, the iductor curret ust be slightly egative after S w turs off to esure both the ZVS of ad the bipolar 11

3 Start 0.65 D: Syste iitialatio Duty cycle Voltage of target cell(v) Voltage of source cell(v).5.5 Fig. 4 The variatio scope of duty cycle. CCM operatio. Moreover, the dead bad of Mode should be large eough to secure the ZVS of S w. Hece, based o Eq. (), the coditio of bipolar CCM ca be derived as, (1 AT ) V d C + AT V d D Td D AT = (3) d VC1+ VC Ts where A Td is the ratio betwee the dead bad ad the switchig period. The boudary coditio defied by Eq. (3) is plotted i Fig 4. Practically, the ope-circuit terial voltage of the Lithiu-Io battery cell varies betwee.5 V ad 4. V. With this voltage rage ad accordig to Eq. (3), the axiu value of duty cycle varies betwee 0.36 ad 0.61, as show i Fig. 4. I order to esure both bipolar CCM ad ZVS, the accurate desig of duty cycle ad the dead bad should be cosidered. This requires iiized circulatig curret durig the coutatio i Mode 4. Moreover, discharges ad charges the output capacitors of ad S w i Mode 4, respectively. The correspodig voltages of the output capacitors of ad S w are discharged ad charged to V D ad V C1+V C+V D, respectively. Thus, the voltage variatios (ΔV) of the two capacitors are equal to V C1+V C. The charge trasferred betwee the two capacitors durig this period is expressed as, Q =Δ VC = ( V + V ) C (4) oss C1 C oss where C oss is the output capacitace of the power MOSFETs. I Mode 4, the iiu charge trasferred fro to the output capacitors of the two MOSFETs ca be derived as, 1 1 V qi = T i = T (5) c1 d Li d L11 Fro equatios (4) ad (5), the dead bad should be desiged as follows, T ( V + V ) L C C1 C 11 oss d (6) VC1 B. Iductor Desig The iductor peak curret (I peak) ca be derived fro the specified average equalizatio curret (I ave), Ipeak = Iave (7) D ax D: fro C i+1 to C i The axiu iductace is deteried by the switchig frequecy (f s), the axiu battery cell voltage (V Cax), the axiu duty cycle, as well as I peak. This relatioship is defied as, VC axdax L = ax I f (8) C. Cotrol Strategy A cotrol strategy is eforced to evaluate the perforace of proposed battery equalizer. The correspodig cotrol flowchart is plotted i Fig. 5. As show, whe the voltage isatch is detected, the correspodig equalizers i the first layer is activated util the balace is achieved. Whe the equalizatio of the first level is fully achieved, the idetical cotrol strategy spreads up to higher levels. Therefore, the overall cell voltage equalizatio ca be achieved after the equalizatio of the th level. Moreover, the adopted cotrol strategy eables a flexible equalizatio path. This helps to iprove the equalizatio speed. It should be oted that the proposed equalizatio ethod is based o the ope circuit voltage of the cell. This is because i battery chargig/dischargig ode, the voltage drop across the iteral resistace of cell affects the accuracy of equalizatio evaluatio. Sice we ca oly easure the terial voltage of each cell durig chargig/dischargig ode, the copesatio of the iteral resistace voltage drop should be addressed i the cotrol algorith. Especially, the detected terial voltage of the dischargig/chargig cell is copesated with a estiated iteral resistace voltage drop i real tie. This guaratees the accuracy of the equalizatio judgeet. IV. Level_1 V V V > Δ ci ci+1 V fro C i to C i+1 Detect cell voltage to copute D ad T d ci > V ci+1 Level_ Level_3 Level_i Vci Vci <ΔV +1 Stop equalizatio Ed Fig. 5 The cotrol flowchart of the equalizer. peak fro C 1-C / to C /+1-C COMPARATIVE AALSIS OF THE PROPOSED EQUALIZER A. Copariso of Equalizatio Speed The equalizatio speed is the ai criteria of the battery equalizatio perforace. Geerally, the higher the power ratig of the equalizer is, the shorter the equalizatio tie becoes. Thus, if the power ratig of the equalizer circuit is s Level_ 1 ci 1 ci >Δ V V V V 1 ci > V 1 ci fro C /+1-C to C 1-C / 1 ci 1 ci < Δ V V V 1

4 fixed, the average uber of equalizatio cycles ca be chose as the figure of erit to evaluate the equalizatio speed [9]. The proposed equalizer ca be see as oe of the adjacet cell-to-cell ethods. This is because differet equalizers placed at differet levels trasfer charge betwee two adjacet cells or strigs. I order to siplify the aalysis, it assues that there is oly oe isatched battery cell i the battery strig, while the other cells are balaced to the sae voltage. A battery strig with series-coected battery cells is cosidered. The required average uber of cycles to achieve fial balace ca be defied as, Cycleij Cycleave = (9) utotal where Cycle ij is the required uber of charge trasfer cycles fro the ith cell to the jth cell. u total is the uber of all possible ibalace cases. For the above-etioed assuptios, u total =. For the bidirectioal cell-to-cell (CC) ethod, the equalizers are coupled i series. The required trasfer cycles fro the i th cell to the j th cell are listed i Table I. Based o Table I, the average uber of required cycles of the bidirectioal CC ethod ca be calculated as, Cycleij = k + k + k + + k + k k= 1 k= 1 k= 1 k= 1 k= 1 ( 1) = 3 Cycle ave ( 1) (10) = (11) 3 The direct cell-to-cell (CC) ethod trasfers charge betwee the two selected battery cells. Oly two battery cells of the whole battery strig ca be equalized at oe specific istat. Therefore, the iiu value of the su of the required cycles ad its average value ca be derived as, Cycle ij = ( 1) (1) Cycleave TABLE I THE REQUIRED CCLES FOR BIDIRECTIOAL CELL-TO-CELL METHOD positio of i th cell positio of j th cell C 1 C C 3 C 4 C -1 C C C C C C C = 1 (13) For the proposed equalizer, whe is equal to a power of, the su of required cycles is expressed as, Cycleij = log = if = (14) Average cycles :Bidirectioal CC ethod :Direct CC ethod :Proposed ethod uber of battery cell [] Fig. 6 The average cycles for charge trasfer of each ethod. 1 ( 1) log if = 1 1 ( ) log +, if = Cycleij = 1 ( 3) log + + 1,if = 3 Cycle log = ij where is the uber of levels i the equalizer. whe -1 < < the su of required cycles is expressed as Eq. (15). As show, it is difficult to obtai a accurate value for the su of required cycles, especially whe is large. The worst case is that the required equalizatio cycles of each ibalaced cell are estiated to the axiu value. I this worst case, the axiu average value of the proposed ethod ca be expressed as, Cycleave = (16) Fro equatios (11), (13) ad (16), the average cycles of each ethod ca be depicted i Fig. 6. The proposed ethod i the worst case deostrates the less uber of average cycles tha the bidirectioal CC ethod ad the direct CC ethod. Especially, for applicatios with a large uber of series cells, the proposed ethod deostrates better equalizatio speed. B. Efficiecy Aalysis The coversio efficiecy is a iportat figure of erit to evaluate the perforace of the battery equalizer. Sice the proposed equalizer is cofigured by a odified buck-boost circuit, this paper focuses o the basic buck-boost uit to evaluate the efficiecy. As show i Eq. (17), the power loss icludes the coductio loss ad switchig loss of the MOSFETs ad coductio loss ad core loss of the iductor. P = P + P + P + P (17) loss S _ coductio S _ switchig L _ coductio L _ core Typically, the coductio loss of the MOSFETs ca be evaluated as, D PSw 1_ coductio = i R = S_ RMS o ipeak Ro 3 1 D P = i R = i R 3 Sw_ coductio S_ RMS o peak o (15) (18) where R o is the o-resistace of the MOSFETs. The switchig loss geerally cosists of tur-o loss ad the tur- 13

5 off loss. Sice the proposed equalizer is cotrolled to operate at the bipolar CCM, the ZVS is achieved whe the MOSFETs turs o. Thus, the switchig loss of the odified buck-boost coverter oly cotais the tur-off loss ad ca be derived as, Pswitchig = Pswitchig _ o + Pswitchig _ off 1 (19) = ipeak ( Vc1 + Vc ) toff fs where t off is the tur-off tie of MOSFET, f s is the switchig frequecy. The coductio loss ad core loss of the iductor ca be expressed as, ipeak l e PL _ coductio = i R = L_ RMS L ρ 3 Ae P α β L_ core s core (0) = η f B V (1) where R L is the resistace of the iductor wire. B is the AC flux swig,, ad are the coefficiets of the core loss, deteried by the agetic aterial of iductor core. V core is the effective volue of the iductor core. Thus, the power efficiecy of the basic buck-boost coverter uit ca be calculated as, η equa lizer _ uit p p p i loss = () Fro equatios (17)-(), the theoretical efficiecy of the basic buck-boost coverter ca be evaluated. If the required uber of cycles to coplete equalizatio icreases, the overall efficiecy decreases due to the required trasfer cycles. C. Copariso of Switchig Loss For the equalizer proposed i [11], the buck-boost coverter operates at the uipolar cotiuous coductio ode (CCM). The correspodig switchig loss ca be expressed as, Pswitchig = Pswitchig _ o + Pswitchig _ off 1 1 = i ( V + V ) t f + i ( V + V ) t f peak c1 c o s peak c1 c off s i (3) I copariso with Eq. (19), this equalizatio ethod suffers fro higher switchig loss. I high switchig frequecy applicatios, this deteriorates the coversio efficiecy. V. SIMULATIO AD EXPERIMETAL RESULTS A. Siulatio Results I order to validate the aalysis of the proposed equalizer ad cotrol strategy, a equalizer to balace four isatched eergy storage uits is desiged ad siulated i PSIM. To accelerate the siulatio speed, the battery cells are eulated by capacitors with extreely large capacitaces. The siulatio results are captured i Fig. 7. The iitial capacitor voltages distribute radoly i the oial operatio regio of Lithiu-Io batteries, (i.e. 3.6, 3.8, 3.85 ad 3.9 V). As show, the voltages of the four series-coected capacitors coverge to be equal after the equalizatio progress V Cell1 V Cell 0.5V/div V Cell3 V Cell4 500s/div Fig. 7. Siulated balacig process of four series- coected capacitors. Copoet Type Lithiu-Io battery Microcotroller Moitor IC MOSFET Iductor TABLE II DESIG PARAMETERS OF THE EQUALIZER DC Power Source DSP Cotrol ler Moitor Board Paraeters CR18650PF (3.6 V/.7 Ah) TMS30F8335 BQ76PL536 AUIRF4104 (R o = 4.3 Ω, C oss = 850 pf, t off = 33 s) 15 µh 4 A (V core = 0.8 c 3, R L = 65 Ω) Equalizer Fig. 8 The photo of experiet setup. Osilloscope I yrio Batteries B. Experietal Results A experietal prototype for four series-coected Lithiu-io battery cells is ipleeted to verify the theoretical ad siulatio results. The desig paraeters are listed i Table II. CR18650PF Lithiu-Io battery cells, which are widely used i idustrial applicatios, are eployed i the prototype. The experietal setup is illustrated i Fig. 8. As show, a oitor IC (BQ76PL536) is used to sese the cell voltages, leadig to the coveiece of voltage detectio for series-coected battery strigs. A digital sigal processor (DSP) reads the voltage through the protocol of serial peripheral iterface (SPI). A DC power source provides power to DSP, oitor IC ad the isolated drivers of MOSFETs. The key wavefors of the experietal are captured i figures 9 ad 10. Fig. 9 presets the critical switchig wavefors of S w ad. Fig. 10 shows the key switchig 14

6 ZVS v gs1 v ds1 argi. Thus, the equalizer is eabled agai at poit D. At poit E, it is judged that fial equalizatio is achieved ad the battery equalizer is switched to idle ode agai. The iitial voltage differece is 90 V. The total equalizatio process takes 68 iutes, ad the ope-circuit voltage differece is reduced to 5 V. This validates the cotrol algorith ad the siulatio results show i figures 5 ad 7, respectively. v gs Fig. 9 v gs1, v ds1 of, v gs of S w ad the iductor curret i L. ZVS v gs v ds v gs1 Fig. 10 v gs, v ds of S w, v gs1 of ad the iductor curret i L. Terial Voltage [V] Ope-circuit Voltage [V] VCT1 VCT VCT3 VCT tie [i] 68 i VOC1 VOC VOC3 VOC tie [i] ΔV = 5 V wavefors of ad. As show i figures 9 ad 10, the MOSFET drai to source voltage drops to zero before the gate sigal is applied. This idicates good ZVS perforaces for the MOSFETs. Figures 9 ad 10 validate the bipolar CCM operatio of the equalizer. Fig. 11 shows the experietal ope-circuit voltages ad the terial voltages of the four series-coected Lithiu-Io battery cells durig the equalizatio process. The voltage data is sapled by the I yrio 1900 platfor. As show i Fig. 11, the iitial voltages are 3.9, 3.84, 3.80 ad 3.63 V, respectively. Specifically, the iitial voltage differece betwee Cell3 ad Cell4 is saller tha that of Cell1 ad Cell. Hece, this leads to a earlier equalizatio (at poit A) betwee Cell3 ad Cell4. Whe the equalizatio process of level_1 is copleted, level_ starts. The voltages of the four cells coverge to the predefied average value at poit C. Thus, the equalizer is switched to idle ode. However, the battery cells self-recover i this idle ode. The certai ope circuit voltage isatch is agai sesed. This isatch is evaluated as higher the tolerated A B C D Fig. 11 The ope circuit voltage (V OC) ad terial voltage (V CT) of the four cells E VI. COCLUSIO I this paper, a hierarchical battery voltage equalizer for series-coected battery strig is preseted. Its basic equalizatio uit is based o the odified buck-boost circuit. I the proposed equalizer, the basic coverter operates at bipolar CCM with a accurate cotrol of the circulatig curret. All the MOSFETs operate with ZVS to reduce the switchig loss. Moreover, the hierarchical architecture provides flexible equalizatio paths for cell or strigs. Thus, the equalizatio speed is iproved. A advaced cotrol strategy based o the ope-circuit voltage is itroduced to optiize both the coversio efficiecy ad the equalizatio speed. The copariso of equalizatio speed betwee differet cell-to-cell architectures is coducted to verify the equalizatio perforace. I additio, The fuctioality of the equalizer is validated by the siulatio ad experiet results. ACKOWLEDGEMET This work was supported i part by the atioal atural Sciece Foudatio of Chia uder Grat , ad i part by the Shaghai Sailig Progra uder Grat 16F REFERECES [1] J. Gallardo-Lozao, E. Roero-Cadaval, M. I. Milaes-Motero, ad M. A. Guerrero-Martiez, Battery equalizatio active ethods, J. Power Sources, vol. 46, pp , 014. [] H. Wag ad Z. Li, "A PWM LLC type resoat coverter adapted to wide output rage i PEV chargig applicatios," IEEE Tras. o Power Electro., vol. 33, o. 5, pp , May 018. [3] H. Wag, M. Shag, ad A. Khaligh, "A PSFB based itegrated PEV oboard charger with exteded ZVS rage ad zero duty cycle loss," IEEE Tras. o Id. Appl., vol. 53, o. 1, pp , Ja [4]. Shag, F. Lu, B. Xia, C. Zhag,. Cui ad C. Mi, "A switchedcouplig-capacitor equalizer for series-coected battery strigs," 017 IEEE Applied Power Electroics Coferece ad Expositio (APEC), Tapa, FL, pp , 017. [5]. e ad K. W. E. Cheg, Aalysis ad Desig of Zero-Curret Switchig Switched-Capacitor Cell Balacig Circuit for Series- Coected Battery/Supercapacitor, IEEE Tras. Veh. Techol., vol. 9545, o. c, pp. 1 1, 017. [6] M. A. Haa, M. M. Hoque, S. E. Peg, ad M.. Uddi, Lithiu- Io Battery Charge Equalizatio Algorith for Electric Vehicle Applicatios, IEEE Tras. Id. Appl., vol. 53, o. 3, pp , 017. [7]. Che, X. Liu,. Cui, J. Zou, ad S. ag, A MultiWidig Trasforer Cell-to-Cell Active Equalizatio Method for Lithiu-Io Batteries with Reduced uber of Drivig Circuits, IEEE Tras. Power Electro., vol. 31, o. 7, pp , 016. [8] C. Li, K. Lee,. Ku, D. Hyu, ad R. Ki, A odularized equalizatio ethod based o agetizig eergy for a seriescoected lithiu-io battery strig battery balace, IEEE Tras. power Electro., 014. [9] S. H. Park, K. B. Park, H. S. Ki, G. W. Moo, ad M. J. ou, Sigle-agetic cell-to-cell charge equalizatio coverter with reduced uber of trasforer widigs, IEEE Tras. Power Electro., vol. 7, o. 6, pp , 01. [10] M.. Ki, J. H. Ki, ad G. W. Moo, Ceter-cell cocetratio structure of a cell-to-cell balacig circuit with a reduced uber of switches, IEEE Tras. Power Electro., vol. 9, o. 10, pp ,

7 [11] F. Mestrallet, L. Kerachev, J. C. Crebier, ad A. Collet, Multiphase iterleaved coverter for lithiu battery active balacig, IEEE Tras. Power Electro., vol. 9, o. 6, pp , 014. [1] B. Dog,. Li, ad. Ha, Parallel architecture for battery charge equalizatio, IEEE Tras. Power Electro., vol. 30, o. 9, pp , 015. [13] S. Wag, L. Kag, X. Guo, Z. Wag, ad M. Liu, A ovel Layered Bidirectioal Equalizer Based o a Buck-Boost Coverter for Series- Coected Battery Strigs, Eergies, vol. 10, o. 7, p. 1011, 017. [14] Z. Zhag, H. Gui, D. J. Gu,. ag, ad X. Re, A hierarchical active balacig architecture for lithiu-io batteries, IEEE Tras. Power Electro., vol. 3, o. 4, pp ,