LSI Computer Systems, Inc Walt Whitman Road, Melville, NY (631) FAX (631) BIT QUADRATURE COUNTER

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1 LSI/CSI LS UL LSI Computer Systems, Inc. Walt Whitman Road, Melville, NY () - FAX () - A -BIT QUADRATURE COUNTER January FEATURES: Programmable modes are: Up/Down, Binary, BCD, Hour Clock, Divide-by-N, x or x or x Quadrature and Single-Cycle. DC to MHz Count Frequency. -Bit I/O Bus for Microprocessor Communication and Control. -Bit comparator for pre-set count comparison. Readable status register. Input/Output TTL and CMOS compatible. V operation (Vdd - Vss). LS (DIP); LS-S (SOIC); LS-TS (-Pin TSSOP)* - See Fig. GENERAL DESCRIPTION: The LS is a CMOS, -bit counter that can be programmed to operate in several different modes. The operating mode is set up by writing control words into internal control registers (see Figure ). There are three -bit and one -bit control registers for setting up the circuit functional characteristics. In addition to the control registers, there is a -bit output status register (OSR) that indicates the current counter status. The IC communicates with external circuits through an -bit three state I/O bus. Control and data words are written into the LS through the bus. In addition to the I/O bus, there are a number of discrete inputs and outputs to facilitate instantaneous hardware based control functions and instantaneous status indication. REGISTER DESCRIPTION: Internal hardware registers are accessible through the I/O bus (D - D) for READ or WRITE when CS =. The C/D input selects between the control registers (C/D = ) and the data registers (C/D = ) during a READ or WRITE operation. (See Table ) (Write Input) WR (Chip Select Input) CS (Load Counter/Load Latch) LCTR/LLTC (A, B Gate/Reset Counter)ABGT/RCTR -Pin Package PIN ASSIGNMENT - Top View *(Contact factory for -Pin TSSOP Package Pinout) VDD (+V) (Count Input) A (Count Input) B D D D LSI LS FIGURE VSS (GND) RD (Read Input) C/D (Control/ Data Input) BW (Borrow Output) CY (Carry Output) The information included herein is believed to be accurate and reliable. However, LSI Computer Systems, Inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use. D D D D D --

2 PR (Preset register). The PR is the input port for the CNTR. The CNTR is loaded with a bit data via the PR. The data is first written into the PR in WRITE cycle sequence of Byte (PR), Byte (PR) and Byte (PR). The address pointer for PR/PR/PR is automatically incremented with each write cycle. Accessed by: WRITE when C/D =, CS =. Bit # PR PR PR (BYTE ) (BYTE ) (BYTE ) Standard Sequence for Loading PR and Reading CNTR: MCR ; Reset PR address pointer WRITE PR ; Load Byte and into PR increment address WRITE PR ; Load Byte and into PR increment address WRITE PR ; Load Byte and into PR increment address MCR ; Transfer PR to CNTR MCR (Master Control Register). Performs register reset and load operations. Writing a "non-zero word to MCR does not require a follow-up write of an all-zero word to terminate a designated operation. Accessed by: WRITE when C/D =, CS =. Bit # : Reset PR/OL address pointer : Transfer CNTR to OL ( bits) : Reset CNTR, BWT and CYT. Set SIGN bit. (CNTR =, BWT =, CYT =, SIGN = ) : Transfer PR to CNTR ( bits) : Reset COMPT (COMPT = ) : Master reset. Reset CNTR, ICR, OCCR, QR, BWT, CYT, OL COMPT, and PR/OL address pointer. Set PR (PR = FFFFFF) and SIGN. : Select MCR : NOTE: Control functions may be combined. ICR (Input Control Register). Initializes counter input operating modes. Accessed by: WRITE when C/D =, CS =. Bit # : Input A = Up count input, Input B = Down count input : Input A = Count input, Input B = Count direction input (overridden in quadrature mode) where B = selects up count mode and B = selects Down count mode. (NOTE: During counting operation B may switch only when A =.) : NOP : Increment CNTR once (A/B =, if enabled) : NOP : Decrement CNTR once (A/B =, if enabled) : Disable inputs A/B : Enable inputs A/B : Initialize Pin as CNTR Reset input (Pin = RCTR) : Initialize Pin as Enable/Disable gate for A/B inputs (Pin = ABGT) : Initialize Pin as CNTR load input (Pin = LCTR) : Initialize Pin as OL load input (Pin = LLTC) : Select ICR : NOTE: Control functions may be combined. --

3 TABLE - Register Addressing Modes D D C/D RD WR CS COMMENT X X X X X Disable Chip for READ/WRITE Write to Master Control Register (MCR) Write to input control register (ICR) Write to output/counter control register (OCCR) Write to quadrature register (QR) X X Write to preset register (PR) and increment register address counter. X X Read output latch (OL) and increment register address counter X X Read output status register (OSR). X = Don't Care OSR (Output Status Register). Indicates CNTR status: Accessed by: READ when C/D =, CS =. Bit # U U U / / / / / U = Undefined BWT. Borrow Toggle Flip-Flop. Toggles everytime CNTR underflows generating a borrow. CYT. Carry Toggle Flip-Flop. Toggles everytime CNTR overflows generating a carry. COMPT. Compare Toggle Flip-Flop. Toggles everytime CNTR equals PR SIGN. Sign bit. Reset ( = ) when CNTR underflows Set ( = ) when CNTR overflows UP/DOWN. Count direction indicatior in quadrature mode. Reset ( = ) when counting down Set ( = ) when counting up (Forced to in non-quadrature mode) OL(Output latch). The OL is the output port for the CNTR. The bit CNTR Value at any instant can be accessed by performing a CNTR to OL transfer and then reading the OL in READ cycle sequence of Byte (OL), Byte (OL) and Byte (OL). The address pointer for OL/OL/OL is automatically incremented with each READ cycle. Accessed by: READ when C/D =, CS =. Bit # OL OL OL (BYTE ) (BYTE ) (BYTE ) Standard Sequence for Loading and Reading OL: MCR ; Reset OL address pointer and Transfer CNTR to OL READ OL ; Read Byte and increment address READ OL ; Read Byte and increment address READ OL ; Read Byte and increment address --

4 OCCR (Output Control Register) Initializes CNTR and output operating modes. Accessed by : WRITE when C/D =, CS =. Bit # : Binary count mode (Overridden by D = ). : BCD count mode (Overridden by D = ) : Normal count mode : Non-Recycle count mode. (CNTR enabled with a Load or Reset CNTR and disabled with generation of Carry or Borrow. In this mode no external CY or BW is generated. Instead CYT or BWT should be used as cycle completion indicator.) : Normal count mode : Divide by N count mode (CNTR is reloaded with PR data upon Carry or Borrow). : Binary or BCD count mode (see D) : Hour Clock mode with Byte = Sec, Byte = Min and Byte = Hr. (Overrides BCD/Binary Modes) Pin = CY, Pin = BW. (Active Low) Pin = CYT, Pin = BWT Pin = CY, Pin = BW. (Active high) Pin = COMP, Pin = COMPT Select OCCR QR (Quadrature Register). Selects quadrature count mode (See Fig. ) Accessed by: WRITE when C/D =, CS =. Bit # X X X X X = Don t Care Disable quadrature mode Enable x quadrature mode Enable x quadrature mode Enable x quadrature mode Select QR --

5 I/O DESCRIPTION: (See REGISTER DESCRIPTION for I/O Prgramming.) Data-Bus (D - D) (Pin - Pin ). The -line data bus is a three-state I/O bus for interfacing with the system bus. CS (Chip Select Input) (Pin ). A logical "" at this input enables the chip for Read and Write. RD (Read Input) (Pin ). A logical "" at this input enables the OSR and the OL to be read on the data bus. WR (Write Input) (Pin ). A logical "" at this input enables the data bus to be written into the control and data registers. C/D (Control/Data Input) (Pin ). A logical "" at this input enables a control word to be written into one of the four control registers or the OSR to be read on the I/O bus. A logical "" enables a data word to be written into the PR, or the OL to be read on the I/O bus. A (Pin ). Input A is a programmable count input capable of functioning in three different modes, such as up count input, down count input and quadrature input. B (Pin ). Input B is also a programmable count input that can be programmed to function either as down count input, or count direction control gate for input A, or quadrature input. When B is programmed as count direction control gate, B = enables A as the Up Count input and B = enables A as the Down Count input. When programmed as the direction input, B can switch state only when A is high. ABGT/RCTR (PIN ). This input can be programmed to function as either inputs A and B enable gate or as external counter reset input. A logical "" is the active level on this input. In non-quadrature mode, if Pin is programmed as A and B enable gate input, it may switch state only when A is high (if A is clock and B is direction) or when both A and B are high (if A and B are clocks. In quadrature mode, if Pin is programmed as A and B enable gate, it may switch state only when either A or B switches. LCTR/LLTC (PIN ). This input can be programmed to function as the external load command input for either the CNTR or the OL. When programmed as counter load input, the counter is loaded with the data contained in the PR. When programmed as the OL load input, the OL is loaded with data contained in the CNTR. A logical "" is the active level on this input. CY (Pin ). This output can be programmed to serve as one of the following: A. CY. Complemented Carry out (active ""). B. CY. True Carry out (active ""). C. CYT. Carry Toggle flip-flop out. D. COMP. Comparator out (active "") BW (Pin ). This output can be programmed to serve as one of the following: A. BW. Complemented Borrow out (active ""). B. BW. True Borrow out (active ""). C. BWT. Borrow Toggle flip-flop out. D. COMPT. Comparator Toggle output. VDD (Pin ). Supply voltage positive terminal. VSS (Pin ). Supply voltage negative terminal. Absolute Maximum Ratings: Parameter Symbol Values Unit Voltage at any input VIN VSS -. to VDD +. V Operating Temperature TA to + oc Storage Temperature TSTG - to + oc Supply Voltage VDD - VSS +. V DC Electrical Characteristics. (All voltages referenced to VSS. TA = to C, VDD =.V to.v, fc =, unless otherwise specified) Parameter Symbol Min. Value Max.Value Unit Remarks Supply Voltage VDD.. V - Supply Current IDD - µa Outputs open Input Low Voltage VIL. V - Input High Voltage VIH. VDD V - Output Low Voltage VOL -. V ma Sink Output High Voltage VOH. - V µa Source Input Current - - na Leakage Current Output Source Current ISRC - µa VOH =.V Output Sink Current ISINK - ma VOL =.V Data Bus Off-State Leakage Current - - na - --

6 TRANSIENT CHARACTERISTICS (See Timing Diagrams in Fig. thru Fig., VDD =.V to.v, TA = to C, unless otherwise specified) Parameter Symbol Min.Value Max.Value Unit Clock A/B "Low TCL No Limit ns Clock A/B "High" TCH No Limit ns Clock A/B Frequency fc MHz (See NOTE ) Clock UP/DN Reversal TUDD - ns Delay LCTR Positive edge to TLC - ns the next A/B positive or negative edge delay Clock A/B to TCBL - ns CY/BW/COMP "low" propagation delay Clock A/B to TCBH - ns CY/BW/COMP "high" propagation delay LCTR and LLTC pulse TLCW - ns width Clock A/B to CYT, BWT TTFH - ns and COMPT "high" propagation delay Clock A/B to CYT, BWT TTFL - ns and COMPT "low" progagation delay WR pulse width TWW - ns RD to data out delay TR - ns (CL = pf) CS, RD Terminate to TRT - ns Data-Bus Tri-State Data-Bus set-up TDS - ns (see Note ) time for WR Data-Bus hold time for WR TDH - ns (see Note ) C/D set-up time for RD TCRS - ns C/D hold time for RD TCRH - ns C/D set-up time for WR TCWS - ns (see Note ) C/D hold time for WR TCWH - ns (see Note ) CS set-up time for WR TSWS - ns (see Note ) CS holdtime for WR TSWH - ns (see Note ) Quadrature Mode: Clock A/B Validation delay TCQV - ns (See NOTE ) A and B phase delay TPH - ns Clock A/B frequency fcq -. MHz CY, BW, COMP pulse width TCBW ns NOTE : A) In Divide-by-N mode, the maximum clock frequency is MHz. B) The maximum frequency for valid CY, BW, CYT, BWT, COMP, COMPT is MHz. NOTE : In quadrature mode A/B inputs are filtered and required to be stable for at least TCQV length to be valid. NOTE : All WR specifications are critical for proper operation of LS --

7 LTCR TLCW UP CLK (A) TLC TCL DN CLK (B) TCH TUDD TCH TCL Q Q Q-Q CNTR=FFFFFD (PR=CNTR) CNTR=FFFFFE CNTR=FFFFFF CNTR= CNTR= CNTR= CNTR=FFFFFF CNTR=FFFFFE CNTR=FFFFFD (PR=CNTR) COMP NOTE CY BW FIGURE. LOAD COUNTER, UP CLOCK, DOWN CLOCK, COMPARE OUT, CARRY, BORROW NOTE : The counter in this example is assumed to be operating in the binary mode. NOTE : No COMP output is generated here, although PR = CNTR. COMP output is disabled with a counter load command and enabled with the rising edge of the next clock, thus eliminating invalid COMP outputs whenever the CNTR is loaded from the PR. NOTE : When UP Clock is active, the DN Clock should be held "HIGH" and vice versa. UP CLK OR DN CLK CY TCBL TCBH TTFH TTFL CYT BW TCBL TCBH TTFH TTFL BWT COMP TCBL TCBH TTFH TTFL COMPT SIGN (INTERNAL) FIGURE. CLOCK TO CY/BW OUTPUT PROPAGATION DELAYS --

8 CS, C/D RD TCRS TCRH DATA BUS TRD VALID OUTPUT TRT CS, C/D TCWS TWW TCWH WR TSWS TSWH TDS TDH DATA BUS VALID DATA FIGURE. READ/WRITE CYCLES LCTR DN CLK Q (INTERNAL) Q (INTERNAL) Q-Q (INTERNAL) CNTR= = = = = = = = = CNTR LD (INTERNAL) BW NOTE: EXAMPLE OF DIVIDE BY IN DOWN COUNT MODE FIGURE. DIVIDE BY N MODE CNTR LOAD (LCTR or MCR BASED) UP CLK OR DN CLK CY or BW CNTR DISABLED CNTR ENABLED CNTR DISABLED FIGURE. CYCLE ONCE MODE --

9 FORWARD REVERSE A B UPCLK (X) DNCLK (X) TPH TPH TCQV UPCLK (X) DNCLK (X) UPCLK (X) TCQV DNCLK (X) UP/DN(OSR Bit ) CY TCBW BW TCBW FIGURE. QUADRATURE MODE INTERNAL CLOCKS --

10 (DATA-BUS) - I/O BUFFER D - D D -D OSR (CHIP SELECT INPUT) CS D, D,D QR (READ INPUT) RD (WRITE INPUT) WR (CONTROL /DATA INPUT) C/D (COUNT INPUT) A (COUNT INPUT) B (AB GATE/LOAD LATCH) ABGT/RCTR INPUT BUFFER AND DECODE LOGIC INTERNAL DATA BUS D - D D - D D - D OCCR ICR MCR CONTROL LOGIC STATUS LOGIC CY (CARRY OUT) BW (BORROW OUT) (LOAD CTR/LOAD LATCH) LCTR/LLTC COMPARATOR N=N N N PR/OL ADDRESS (+V) VDD (GND) VSS D -D PR B - B PR B - B PR B - B CNTR Q -Q OL OL B - B OL FIGURE. LS BLOCK DIAGRAM D - D PR/OL ADDRESS UP CLOCK DN CLOCK --

11 FIGURE. C/ TO LS INTERFACE IN EXTERNAL ADDRESS MODE C P. P. P. P. P. P. P. P. ALE AD AD AD AD AD AD AD AD HC D Q C C Q C/D CS/ AD AD AD AD AD AD AD AD D D D D D D D D WR/ RD/ WR/ RD/ NOTE: Port_ is open drain output. Add pull-up resistors to all Port_ I/ lines. FIGURE. INTERFACE TO LS IN I/O MODE VCC VCC UR ER/VP X X RESET P. P. P. P. P. P. P. P. R VDD LCTR/LLTC RBGT/RCTR CY BW P. P. P. P. P. P. P. P. INT INT T T P. P. P. P. P. P. P. P. P. P. P. P. P. P. P. P. RD WR PSEN ALE/P TXO RXO /C/D /CS /RD /WR P. P. P. P. P. P. P. P. D D D D D D D D LS Vss WR RD C/D CS /WR /RD /C/D /CS --

12 ADDRESS DECODER PR Q Q CLK D HC HC CLOCK A IOR IOW A A A A A A A A A AEN D D D D D D D D D D D D D D D D Vss CS WR RD C/D IOR VDD C CAP A B LCTR/LLTC ABGT/RCTR D D D D D D D D VCC +V MC ISA BUSS FIGURE. U A INTERFACE TO LS I/O MODE --

13 GND VDD CY BW LCTR/LLTC RBGT/RCTR A COUNT IN B COUNT IN D D D D D D D D PC PC PC PC PC PC PC PC A CS/ VR/ RD/ ADDRESS DECODE D Q CLK Q CL PR HC Q Q Q Q Q Q Q Q LS +V +V HC U A U B HC HC HC U A U B HC HCA PA PA PA PA PA PB PB PB PB PB PB PB PB PC PC PC PC PC PC PC PC PD PD PD PD PD PD MODA MODB E AS R/W U XT EX RESET IRQ XIRD PA PA PA PE PE PE PE YRH YRL PC PC PC PC PC PC PC PC PC PC PC PC PC PC PC PC U OC G D D D D D D D D C/D CS VR RD FIGURE. LS TO HC INTERFACE --

14 FIGURE. INTERFACE TO LS ADDRESS D Q LS CK DATA BUS A DECODE D - D C/D CS R/W LDS/UDS +V S D S CK Q R +V RD WR AS CLOCK DTACK CLK S D S Q CK R Q S D S CK R --

LSI/CSI LS BIT MULTI-MODE COUNTER

LSI/CSI LS BIT MULTI-MODE COUNTER LSI/CSI LS766 UL LSI Computer Systems, Inc. 235 Walt Whitman Road, Melville, NY 747 (63) 27-4 FAX (63) 27-45 A38 24-BIT MULTI-MODE COUNTER December 999 FEATURES: Programmable modes are: Up/Down, Binary,