CMOS 12-Bit Serial Input Multiplying DIGITAL-TO-ANALOG CONVERTER

Transcription

1 CMOS 2-Bit Serial Input Multiplying DIGITAL-TO-ANALOG CONVETE FEATUES 2-BICCUACY IN 8-PIN SOIC FAST 3-WIE SEIAL INTEFACE LOW INL AND DNL: ±/2 LSB max GAIN ACCUACY TO ±LSB max LOW GAIN TEMPCO: 5ppm/ C max OPEATES WITH 5V SUPPLY TTL/CMOS COMPATIBLE ESD POTECTED APPLICATIONS AUTOMATIC CALIBATION MOTION CONTOL MICOPOCESSO CONTOL SYSTEMS POGAMMABLE AMPLIFIE/ ATTENUATOS DIGITALLY CONTOLLED FILTES DESCIPTION The is a 2-bit current output multiplying digital-to-analog converter (DAC) that is packaged in a space-saving, surface-mount 8-pin SOIC. Its 3-wire serial interface saves additional circuit board space which results in low power dissipation. When used with microprocessors having a serial port, the minimizes the digital noise feedthrough from its input to output. The serial port can be used as a dedicated analog bus and kept inactive while the is in use. Serial interfacing reduces the complexity of opto or transformer isolation applications. The contains a 2-bit serial-in, parallel-out shift register, a 2-bit DAC register, a 2-bit CMOS DAC, and control logic. Serial input (SI) data is clocked into the input register on the rising edge of the clock (CLK) pulse. When the new data word had been clocked in, it is loaded into the DAC register by taking the LD input low. Data in the DAC register is converted to an output current by the D/A converter. The operates from a single 5V power supply which makes the an ideal low power, small size, high performance solution for several applications. LD CLK SI Bit D/A Converter 2 2-Bit DAC egister 2 2-Bit Input Shift egister International Airport Industrial Park Mailing Address: PO Box 4, Tucson, AZ Street Address: 673 S. Tucson Blvd., Tucson, AZ 8576 Tel: (52) 746- Twx: Internet: FAXLine: (8) (US/Canada Only) Cable: BBCOP Telex: FAX: (52) Immediate Product Info: (8) Burr-Brown Corporation PDS-97B Printed in U.S.A. March, 998

2 SPECIFICATIONS ELECTICAL CHAACTEISTICS At = 5V; = V; = = V; = Full Temperature ange specified under Absolute Maximum atings, unless otherwise noted. U UC PAAMETE SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX UNITS STATIC PEFOMANCE esolution N 2 2 Bits Nonlinearity () INL ± ±/2 LSB Differential Nonlinearity (2) DNL ± ±/2 LSB Gain Error (3) FSE = 25 C ±2 ± LSB = Full Temp ange ±2 ±2 LSB Gain Tempco (5) TC FSE ±5 ±5 ppm/ C Power Supply ejection atio PS = ±5% ±.6 ±.2 ±.6 ±.2 %/% Output Leakage Current (4) I LKG = 25 C ±5 ±5 na = Full Temp ange ± ±25 na Zero Scale Error (7, 2) I ZSE = 25 C.3.3 LSB = Full Temp ange.6.5 LSB Input esistance (8) IN kω AC PEFOMANCE Output Current Settling Time (5, 6) t S = 25 C µs Digital-to-Analog Glitch = V nvs Energy (5, ) Q = Load = Ω C EXT = 3pF DAC egister Loaded Alternately with all s and all s Feedthrough Error (5, ) FT = 2Vp-p at f = khz.7.7 mvp-p ( to ) Digital Input = = 25 C Total Harmonic Distortion (5) THD = 6V MS at khz db DAC egister Loaded with all s Output Noise Voltage Density (5, 3) e N Hz to khz 7 7 nv/ Hz Between and DIGITAL INPUTS Digital Input High V IH V Digital Input Low V IL.8.8 V Input Leakage Current (9) I IL V IN = V to 5V ± ± µa Input Capacitance (5, ) C IN V IN = V 8 8 pf ANALOG OUTPUTS Output Capacitance (5) C OUT Digital Inputs = V IH pf Digital Inputs = V IL 8 8 pf TIMING CHAACTEISTICS (5, 4) Data Setup Time t DS = Full Temperature ange 4 4 ns Data Hold Time t DH = Full Temperature ange 8 8 ns Clock Pulse Width High t CH = Full Temperature ange 9 9 ns Clock Pulse Width Low t CL = Full Temperature ange 2 2 ns Load Pulse Width t LD = Full Temperature ange 2 2 ns LSB Clock into Input egister to Load DAC egister Time t ASB = Full Temperature ange ns POWE SUPPLY Supply Voltage V Supply Current I DD Digital Inputs = V IH or V IL 5 5 µa Digital Inputs = V or µa NOTES: () ±/2 LSB = ±.2% of Full Scale. (2) All grades are monotonic to 2-bits over temperature. (3) Using internal feedback resistor. (4) Applies to ; All digital inputs = V. (5) Guaranteed by design and not tested. (6) Load = Ω, C EXT = 3pF, digital input = V to or to V. Extrapolated to /2 LSB: t S = propagation delay (t PD ) 9τ where τ = measured time constant of the final C decay. (7) = V, all digital inputs = V. (8) Absolute temperature coefficient is less than ±5ppm/ C. (9) Digital inputs are CMOS gates: I IN is typically na at 25 C. () = V, all digital inputs = V to or to V. () All digital inputs = V. (2) Calculated from worst case EF : I ZSE (in LSBs) = ( EF X I LKG X 496)/. (3) Calculations from en = 4K TB where: K = Boltzmann constant, J/ K, = resistance, Ω. T = esistor temperature, K, B = bandwidth, Hz. (4) Tested at V IN = V or. The information provided herein is believed to be reliable; however, BU-BOWN assumes no responsibility for inaccuracies or omissions. BU-BOWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BU-BOWN does not authorize or warrant any BU-BOWN product for use in life support devices and/or systems. 2

3 WAFE TEST LIMITS At = 5V; = V; = = V; = 25 C. PAAMETE SYMBOL CONDITIONS LIMIT UNITS STATIC ACCUACY esolution N 2 Bits min Integral Nonlinearity INL ± LSB max Differential Nonlinearity DNL ± LSB max Gain Error G FSE Using Internal Feedback esistor ±2 LSB max Power Supply ejection atio PS = ±5% ±.2 %/% max Output Leakage Current ( ) I LKG Digital Inputs = V IL ±5 na max EFEENCE INPUT Input esistance IN 7/5 kω min/max DIGITAL INPUTS Digital Input HIGH V IH 2.4 V min Digital Input LOW V IL.8 V max Input Leakage Current I IL V IN = V to ± µa max POWE SUPPLY Supply Current I DD Digital Inputs = V IH or V IL 5 µa max Digital Inputs = V to µa max NOTE: Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. ABSOLUTE MAXIMUM ATINGS PIN CONFIGUATION to... V, 7V to... ±25V V FB to... ±25V Digital Input Voltage ange....3v to Output Voltage (Pin 3)....3 V to Operating Temperature ange AD... C to 7 C U, UC... 4 C to 85 C Junction Temperature... 5 C Storage Temperature C to 5 C Lead Temperature (soldering, s)... 3 C θ JA... C/W θ JC C/W Top View CLK SI LD 8-Pin SOIC CAUTION:. Do not apply voltages higher than or less than potential on any terminal except (Pin ) and (Pin 2). 2. The digital control inputs are ESD protected: however, permanent damage may occur on unprotected units from high-energy electrostatic fields. Keep units in conductive foam at all times until ready to use. 3. Use proper anti-static handling procedures. 4. Absolute Maximum atings apply to both packaged devices. Stresses above those listed under Absolute Maximum atings may cause permanent damage to the device. PACKAGE/ODEING INFOMATION PACKAGE TEMPEATUE DAWING PODUCT INL ANGE PACKAGE NUMBE () U LSB 4 C to 85 C 8-pin SOIC 82 UC /2LSB 4 C to 85 C 8-pin SOIC 82 NOTE: () For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. 3 ELECTOSTATIC DISCHAGE SENSITIVITY Any integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. Digital Inputs: All digital inputs of the incorporate on-chip ESD protection circuitry. This protection is designed and has been tested to withstand five 25V positive and negative discharges (pf in series with 5Ω) applied to each digital input. Analog Pins: Each analog pin has been tested to Burr- Brown s analog ESD test consisting of five V positive and negative discharges (pf in series with 5Ω) applied to each pin. and show some sensitivity.

4 WITE CYCLE TIMING DIAGAM SI Bit MSB () Bit 2 Bit Bit 2 LSB t DS t DH CLK INPUT t CH t CL 2 Load Serial Data Into Input egister t ASB LD NOTE: () Data loaded MSB first. t LD Load Input egister's Data Into DAC egister 4

5 TYPICAL PEFOMANCE CUVES At = 5V; = V; = = V; = Full Temperature ange specified under Absolute Maximum atings, unless otherwise noted. INL (LSB) LINEAITY EO vs EFEENCE VOLTAGE (V) Gain (db) Digital Input = GAIN vs FEQUENCY Digital Input = 2 k k k M M Frequency (Hz) = 5V = mv = 25 C I DD (ma) SUPPLY CUENT vs LOGIC INPUT VOLTAGE = 5V THD (db) TOTAL HAMONIC DISTOTION vs FEQUENCY (Multiplying Mode) = 5V V IN = 6Vrms = 25 C V IN (V) 2 Frequency (Hz).75 LINEAITY EO vs DIGITAL CODE = 25 C = V.5 DNL EO vs EFEENCE VOLTAGE Linearity Error (LSB) DNL (LSB) Digital Input Code (Decimal) (V) 5

6 DISCUSSION OF SPECIFICATIONS ELATIVE ACCUACY This term, also known as end point linearity or integral linearity, describes the transfer function of analog output to digital input code. elative accuracy describes the deviation from a straight line, after zero and full scale errors have been adjusted to zero. DIFFEENTIAL NONLINEAITY Differential nonlinearity is the deviation from an ideal LSB change in the output when the input code changes by LSB. A differential nonlinearity specification of LSB maximum guarantees monotonicity. GAIN EO Gain error is the difference between the full-scale DAC output and the ideal value. The ideal full scale output value for the is (495/496). Gain error may be adjusted to zero using external trims as shown in Figure 4. OUTPUT LEAKAGE CUENT The current which appears at with the DAC loaded with all zeros. OUTPUT CAPACITANCE The parasitic capacitance measured from to. FEEDTHOUGH EO The AC output error due to capacitive coupling from to with the DAC loaded with all zeros. OUTPUT CUENT SETTLING TIME The time required for the output current to settle to within.% of final value for a full scale step. DIGITAL-TO-ANALOG GLITCH ENEGY The integrated area of the glitch pulse measured in nanovoltseconds. The key contributor to digital-to-analog glitch is charge injected by digital logic switching transients. CICUIT DESCIPTION Figure shows a simplified schematic of a. The current from the pin is switched between and by 2 single-pole double-throw CMOS switches. This maintains a constant current in each leg of the ladder regardless of the input code. The input resistance at is therefore constant and can be driven by either a voltage or current, AC or DC, positive or negative polarity, and have a voltage range up to ±2V. A CMOS switch transistor, included in series with the ladder terminating resistor and in series with the feedback resistor,, compensates for the temperature drift of the ON resistance of the ladder switches. Figure 2 shows an equivalent circuit for the DAC. C OUT is the output capacitance due to the N-channel switches and varies from about 8pF to pf with digital input code. The current source I LKG is the combination of surface and junction leakages to the substrate. I LKG approximately doubles every C. O is the equivalent output resistance of the D/A and it varies with input code. D IN 496 x O I LKG FIGUE 2. Equivalent Circuit for the DAC. INSTALLATION COUT ESD POTECTION All digital inputs of the incorporate on-chip ESD protection circuitry. This protection is designed to withstand 2.5kV (using the Human Body Model, pf and 5Ω). However, industry standard ESD protection methods should be used when handling or storing these components. When not in use, devices should be stored in conductive foam or rails. The foam or rails should be discharged to the destination socket potential before devices are removed. POWE SUPPLY CONNECTIONS The is designed to operate on = 5V ±5%. For optimum performance and noise rejection, power supply decoupling capacitors C D should be added as shown in the application circuits. These capacitors (µf tantalum recommended) should be located close to the D/A. Output op amp analog common ( input) should be connected as near to the pins of the as possible. Bit (MSB) Bit 2 Bit 3 Bit 2 (LSB) WIING PECAUTIONS To minimize AC feedthrough when designing a PC board, care should be taken to minimize capacitive coupling between the lines and the lines. Coupling from any of the digital control or data lines might degrade the glitch performance. Solder the directly into the PC board without a socket. Sockets add parasitic capacitance (which can degrade AC performance). FIGUE. Simplified Circuit Diagram for the DAC. 6

7 AMPLIFIE OFFSET VOLTAGE The output amplifier used with the should have low input offset voltage to preserve the transfer function linearity. The voltage output of the amplifier has an error component which is the offset voltage of the op amp multiplied by the noise gain of the circuit. This noise gain is equal to ( F / O ) where O is the output impedance of the D/A terminal and F is the feedback network impedance. The nonlinearity occurs due to the output impedance varying with code. If the code case is excluded (where O = infinity), the O will vary from to 3 providing a noise gain variation between 4/3 and 2. In addition, the variation of O is nonlinear with code, and the largest steps in O occur at major code transitions where the worst differential nonlinearity is also likely to be experienced. The nonlinearity seen at the amplifier output is 2V OS 4V OS /3 = 2V OS /3. Thus, to maintain good nonlinearity the op amp offset should be much less than /2LSB. UNIPOLA CONFIGUATION Figure 3 shows in a typical unipolar (two-quadrant) multiplying configuration. The analog output values DATA INPUT ANALOG OUTPUT MSB LSB (495/496) (248/496) = /2 (/496) Volts TABLE I. Unipolar Output Code. versus digital input code are listed in Table I. The operational amplifiers used in this circuit can be single amplifiers such as the OPA62, or a dual amplifier such as the OPA27. C provides phase compensation to minimize settling time and overshoot when using a high speed operational amplifier. If an application requires the D/A to have zero gain error, the circuit shown in Figure 4 may be used. esistor 2 induces a positive gain error greater than worst-case initial negative gain error. Trim resistor provides a variable negative gain error and have sufficient trim range to correct for the worstcase initial positive gain error plus the error produced by 2. BIPOLA CONFIGUATION Figure 5 shows the in a typical bipolar (fourquadrant) multiplying configuration. The analog output values versus digital input code are listed in Table II. The operational amplifiers used in this circuit can be single amplifiers such as the OPA62 or a dual amplifier such as the OPA27. C provides phase compensation to minimize settling time and overshoot when using a high speed operational amplifier. The bipolar offset resistors 2 should be ratio-matched to.% to ensure the specified gain error performance. DATA INPUT ANALOG OUTPUT MSB LSB (247/248) (/248) Volts (/248) (248/248) TABLE II. Bipolar Output Code. 5V 5V V IN C D µf DAC C pf A A OPA62 or /2 OPA27. V OUT C D µf Ω DAC 2 47Ω C pf A V OUT A OPA62 or /2 OPA27. FIGUE 3. Unipolar Configuration. FIGUE 4. Unipolar Configuration with Gain Trim. 5V Ω 2k C D µf 2Ω 2k 3 kω A2 V OUT DAC C pf A AA2, OPA62 or /2 OPA27. FIGUE 5. Bipolar Configuration. 7